/* SPDX-License-Identifier: GPL-1.0+ */ /* Generic NS8390 register definitions. */ /* This file is part of Donald Becker's 8390 drivers, and is distributed * under the same license. Auto-loading of 8390.o only in v2.2 - Paul G. * Some of these names and comments originated from the Crynwr * packet drivers, which are distributed under the GPL. */ #ifndef _8390_h #define _8390_h #include <linux/if_ether.h> #include <linux/ioport.h> #include <linux/irqreturn.h> #include <linux/skbuff.h> #define TX_PAGES … /* The 8390 specific per-packet-header format. */ struct e8390_pkt_hdr { … }; #ifdef CONFIG_NET_POLL_CONTROLLER void ei_poll(struct net_device *dev); void eip_poll(struct net_device *dev); #endif /* Without I/O delay - non ISA or later chips */ void NS8390_init(struct net_device *dev, int startp); int ei_open(struct net_device *dev); int ei_close(struct net_device *dev); irqreturn_t ei_interrupt(int irq, void *dev_id); void ei_tx_timeout(struct net_device *dev, unsigned int txqueue); netdev_tx_t ei_start_xmit(struct sk_buff *skb, struct net_device *dev); void ei_set_multicast_list(struct net_device *dev); struct net_device_stats *ei_get_stats(struct net_device *dev); extern const struct net_device_ops ei_netdev_ops; struct net_device *__alloc_ei_netdev(int size); static inline struct net_device *alloc_ei_netdev(void) { … } /* With I/O delay form */ void NS8390p_init(struct net_device *dev, int startp); int eip_open(struct net_device *dev); int eip_close(struct net_device *dev); irqreturn_t eip_interrupt(int irq, void *dev_id); void eip_tx_timeout(struct net_device *dev, unsigned int txqueue); netdev_tx_t eip_start_xmit(struct sk_buff *skb, struct net_device *dev); void eip_set_multicast_list(struct net_device *dev); struct net_device_stats *eip_get_stats(struct net_device *dev); extern const struct net_device_ops eip_netdev_ops; struct net_device *__alloc_eip_netdev(int size); static inline struct net_device *alloc_eip_netdev(void) { … } /* You have one of these per-board */ struct ei_device { … }; /* The maximum number of 8390 interrupt service routines called per IRQ. */ #define MAX_SERVICE … /* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */ #define TX_TIMEOUT … #define ei_status … /* Some generic ethernet register configurations. */ #define E8390_TX_IRQ_MASK … #define E8390_RX_IRQ_MASK … #ifdef AX88796_PLATFORM #define E8390_RXCONFIG … #define E8390_RXOFF … #else /* EN0_RXCR: broadcasts, no multicast,errors */ #define E8390_RXCONFIG … /* EN0_RXCR: Accept no packets */ #define E8390_RXOFF … #endif /* EN0_TXCR: Normal transmit mode */ #define E8390_TXCONFIG … /* EN0_TXCR: Transmitter off */ #define E8390_TXOFF … /* Register accessed at EN_CMD, the 8390 base addr. */ #define E8390_STOP … #define E8390_START … #define E8390_TRANS … #define E8390_RREAD … #define E8390_RWRITE … #define E8390_NODMA … #define E8390_PAGE0 … #define E8390_PAGE1 … #define E8390_PAGE2 … /* Only generate indirect loads given a machine that needs them. * - removed AMIGA_PCMCIA from this list, handled as ISA io now * - the _p for generates no delay by default 8390p.c overrides this. */ #ifndef ei_inb #define ei_inb … #define ei_outb … #define ei_inb_p … #define ei_outb_p … #endif #ifndef EI_SHIFT #define EI_SHIFT … #endif #define E8390_CMD … /* Page 0 register offsets. */ #define EN0_CLDALO … #define EN0_STARTPG … #define EN0_CLDAHI … #define EN0_STOPPG … #define EN0_BOUNDARY … #define EN0_TSR … #define EN0_TPSR … #define EN0_NCR … #define EN0_TCNTLO … #define EN0_FIFO … #define EN0_TCNTHI … #define EN0_ISR … #define EN0_CRDALO … #define EN0_RSARLO … #define EN0_CRDAHI … #define EN0_RSARHI … #define EN0_RCNTLO … #define EN0_RCNTHI … #define EN0_RSR … #define EN0_RXCR … #define EN0_TXCR … #define EN0_COUNTER0 … #define EN0_DCFG … #define EN0_COUNTER1 … #define EN0_IMR … #define EN0_COUNTER2 … /* Bits in EN0_ISR - Interrupt status register */ #define ENISR_RX … #define ENISR_TX … #define ENISR_RX_ERR … #define ENISR_TX_ERR … #define ENISR_OVER … #define ENISR_COUNTERS … #define ENISR_RDC … #define ENISR_RESET … #define ENISR_ALL … /* Bits in EN0_DCFG - Data config register */ #define ENDCFG_WTS … #define ENDCFG_BOS … /* Page 1 register offsets. */ #define EN1_PHYS … #define EN1_PHYS_SHIFT(i) … #define EN1_CURPAG … #define EN1_MULT … #define EN1_MULT_SHIFT(i) … /* Bits in received packet status byte and EN0_RSR*/ #define ENRSR_RXOK … #define ENRSR_CRC … #define ENRSR_FAE … #define ENRSR_FO … #define ENRSR_MPA … #define ENRSR_PHY … #define ENRSR_DIS … #define ENRSR_DEF … /* Transmitted packet status, EN0_TSR. */ #define ENTSR_PTX … #define ENTSR_ND … #define ENTSR_COL … #define ENTSR_ABT … #define ENTSR_CRS … #define ENTSR_FU … #define ENTSR_CDH … #define ENTSR_OWC … #endif /* _8390_h */
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