/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Actions Semi Owl SoCs Ethernet MAC driver * * Copyright (c) 2012 Actions Semi Inc. * Copyright (c) 2021 Cristian Ciocaltea <[email protected]> */ #ifndef __OWL_EMAC_H__ #define __OWL_EMAC_H__ #define OWL_EMAC_DRVNAME … #define OWL_EMAC_POLL_DELAY_USEC … #define OWL_EMAC_MDIO_POLL_TIMEOUT_USEC … #define OWL_EMAC_RESET_POLL_TIMEOUT_USEC … #define OWL_EMAC_TX_TIMEOUT … #define OWL_EMAC_MTU_MIN … #define OWL_EMAC_MTU_MAX … #define OWL_EMAC_RX_FRAME_MAX_LEN … #define OWL_EMAC_SKB_ALIGN … #define OWL_EMAC_SKB_RESERVE … #define OWL_EMAC_MAX_MULTICAST_ADDRS … #define OWL_EMAC_SETUP_FRAME_LEN … #define OWL_EMAC_RX_RING_SIZE … #define OWL_EMAC_TX_RING_SIZE … /* Bus mode register */ #define OWL_EMAC_REG_MAC_CSR0 … #define OWL_EMAC_BIT_MAC_CSR0_SWR … /* Transmit/receive poll demand registers */ #define OWL_EMAC_REG_MAC_CSR1 … #define OWL_EMAC_VAL_MAC_CSR1_TPD … #define OWL_EMAC_REG_MAC_CSR2 … #define OWL_EMAC_VAL_MAC_CSR2_RPD … /* Receive/transmit descriptor list base address registers */ #define OWL_EMAC_REG_MAC_CSR3 … #define OWL_EMAC_REG_MAC_CSR4 … /* Status register */ #define OWL_EMAC_REG_MAC_CSR5 … #define OWL_EMAC_MSK_MAC_CSR5_TS … #define OWL_EMAC_OFF_MAC_CSR5_TS … #define OWL_EMAC_VAL_MAC_CSR5_TS_DATA … #define OWL_EMAC_VAL_MAC_CSR5_TS_CDES … #define OWL_EMAC_MSK_MAC_CSR5_RS … #define OWL_EMAC_OFF_MAC_CSR5_RS … #define OWL_EMAC_VAL_MAC_CSR5_RS_FDES … #define OWL_EMAC_VAL_MAC_CSR5_RS_CDES … #define OWL_EMAC_VAL_MAC_CSR5_RS_DATA … #define OWL_EMAC_BIT_MAC_CSR5_NIS … #define OWL_EMAC_BIT_MAC_CSR5_AIS … #define OWL_EMAC_BIT_MAC_CSR5_ERI … #define OWL_EMAC_BIT_MAC_CSR5_GTE … #define OWL_EMAC_BIT_MAC_CSR5_ETI … #define OWL_EMAC_BIT_MAC_CSR5_RPS … #define OWL_EMAC_BIT_MAC_CSR5_RU … #define OWL_EMAC_BIT_MAC_CSR5_RI … #define OWL_EMAC_BIT_MAC_CSR5_UNF … #define OWL_EMAC_BIT_MAC_CSR5_LCIS … #define OWL_EMAC_BIT_MAC_CSR5_LCIQ … #define OWL_EMAC_BIT_MAC_CSR5_TU … #define OWL_EMAC_BIT_MAC_CSR5_TPS … #define OWL_EMAC_BIT_MAC_CSR5_TI … /* Operation mode register */ #define OWL_EMAC_REG_MAC_CSR6 … #define OWL_EMAC_BIT_MAC_CSR6_RA … #define OWL_EMAC_BIT_MAC_CSR6_TTM … #define OWL_EMAC_BIT_MAC_CSR6_SF … #define OWL_EMAC_MSK_MAC_CSR6_SPEED … #define OWL_EMAC_OFF_MAC_CSR6_SPEED … #define OWL_EMAC_VAL_MAC_CSR6_SPEED_100M … #define OWL_EMAC_VAL_MAC_CSR6_SPEED_10M … #define OWL_EMAC_BIT_MAC_CSR6_ST … #define OWL_EMAC_BIT_MAC_CSR6_LP … #define OWL_EMAC_BIT_MAC_CSR6_FD … #define OWL_EMAC_BIT_MAC_CSR6_PM … #define OWL_EMAC_BIT_MAC_CSR6_PR … #define OWL_EMAC_BIT_MAC_CSR6_IF … #define OWL_EMAC_BIT_MAC_CSR6_PB … #define OWL_EMAC_BIT_MAC_CSR6_HO … #define OWL_EMAC_BIT_MAC_CSR6_SR … #define OWL_EMAC_BIT_MAC_CSR6_HP … #define OWL_EMAC_MSK_MAC_CSR6_STSR … /* Interrupt enable register */ #define OWL_EMAC_REG_MAC_CSR7 … #define OWL_EMAC_BIT_MAC_CSR7_NIE … #define OWL_EMAC_BIT_MAC_CSR7_AIE … #define OWL_EMAC_BIT_MAC_CSR7_ERE … #define OWL_EMAC_BIT_MAC_CSR7_GTE … #define OWL_EMAC_BIT_MAC_CSR7_ETE … #define OWL_EMAC_BIT_MAC_CSR7_RSE … #define OWL_EMAC_BIT_MAC_CSR7_RUE … #define OWL_EMAC_BIT_MAC_CSR7_RIE … #define OWL_EMAC_BIT_MAC_CSR7_UNE … #define OWL_EMAC_BIT_MAC_CSR7_TUE … #define OWL_EMAC_BIT_MAC_CSR7_TSE … #define OWL_EMAC_BIT_MAC_CSR7_TIE … #define OWL_EMAC_BIT_MAC_CSR7_ALL_NOT_TUE … /* Missed frames and overflow counter register */ #define OWL_EMAC_REG_MAC_CSR8 … /* MII management and serial ROM register */ #define OWL_EMAC_REG_MAC_CSR9 … /* MII serial management register */ #define OWL_EMAC_REG_MAC_CSR10 … #define OWL_EMAC_BIT_MAC_CSR10_SB … #define OWL_EMAC_MSK_MAC_CSR10_CLKDIV … #define OWL_EMAC_OFF_MAC_CSR10_CLKDIV … #define OWL_EMAC_VAL_MAC_CSR10_CLKDIV_128 … #define OWL_EMAC_VAL_MAC_CSR10_OPCODE_WR … #define OWL_EMAC_OFF_MAC_CSR10_OPCODE … #define OWL_EMAC_VAL_MAC_CSR10_OPCODE_DCG … #define OWL_EMAC_VAL_MAC_CSR10_OPCODE_WR … #define OWL_EMAC_VAL_MAC_CSR10_OPCODE_RD … #define OWL_EMAC_VAL_MAC_CSR10_OPCODE_CDS … #define OWL_EMAC_MSK_MAC_CSR10_PHYADD … #define OWL_EMAC_OFF_MAC_CSR10_PHYADD … #define OWL_EMAC_MSK_MAC_CSR10_REGADD … #define OWL_EMAC_OFF_MAC_CSR10_REGADD … #define OWL_EMAC_MSK_MAC_CSR10_DATA … /* General-purpose timer and interrupt mitigation control register */ #define OWL_EMAC_REG_MAC_CSR11 … #define OWL_EMAC_OFF_MAC_CSR11_TT … #define OWL_EMAC_OFF_MAC_CSR11_NTP … #define OWL_EMAC_OFF_MAC_CSR11_RT … #define OWL_EMAC_OFF_MAC_CSR11_NRP … /* MAC address low/high registers */ #define OWL_EMAC_REG_MAC_CSR16 … #define OWL_EMAC_REG_MAC_CSR17 … /* Pause time & cache thresholds register */ #define OWL_EMAC_REG_MAC_CSR18 … #define OWL_EMAC_OFF_MAC_CSR18_CPTL … #define OWL_EMAC_OFF_MAC_CSR18_CRTL … #define OWL_EMAC_OFF_MAC_CSR18_PQT … /* FIFO pause & restart threshold register */ #define OWL_EMAC_REG_MAC_CSR19 … #define OWL_EMAC_OFF_MAC_CSR19_FPTL … #define OWL_EMAC_OFF_MAC_CSR19_FRTL … /* Flow control setup & status register */ #define OWL_EMAC_REG_MAC_CSR20 … #define OWL_EMAC_BIT_MAC_CSR20_FCE … #define OWL_EMAC_BIT_MAC_CSR20_TUE … #define OWL_EMAC_BIT_MAC_CSR20_TPE … #define OWL_EMAC_BIT_MAC_CSR20_RPE … #define OWL_EMAC_BIT_MAC_CSR20_BPE … /* MII control register */ #define OWL_EMAC_REG_MAC_CTRL … #define OWL_EMAC_BIT_MAC_CTRL_RRSB … #define OWL_EMAC_OFF_MAC_CTRL_SSDC … #define OWL_EMAC_BIT_MAC_CTRL_RCPS … #define OWL_EMAC_BIT_MAC_CTRL_RSIS … /* Receive descriptor status field */ #define OWL_EMAC_BIT_RDES0_OWN … #define OWL_EMAC_BIT_RDES0_FF … #define OWL_EMAC_MSK_RDES0_FL … #define OWL_EMAC_OFF_RDES0_FL … #define OWL_EMAC_BIT_RDES0_ES … #define OWL_EMAC_BIT_RDES0_DE … #define OWL_EMAC_BIT_RDES0_RF … #define OWL_EMAC_BIT_RDES0_MF … #define OWL_EMAC_BIT_RDES0_FS … #define OWL_EMAC_BIT_RDES0_LS … #define OWL_EMAC_BIT_RDES0_TL … #define OWL_EMAC_BIT_RDES0_CS … #define OWL_EMAC_BIT_RDES0_FT … #define OWL_EMAC_BIT_RDES0_RE … #define OWL_EMAC_BIT_RDES0_DB … #define OWL_EMAC_BIT_RDES0_CE … #define OWL_EMAC_BIT_RDES0_ZERO … /* Receive descriptor control and count field */ #define OWL_EMAC_BIT_RDES1_RER … #define OWL_EMAC_MSK_RDES1_RBS1 … /* Transmit descriptor status field */ #define OWL_EMAC_BIT_TDES0_OWN … #define OWL_EMAC_BIT_TDES0_ES … #define OWL_EMAC_BIT_TDES0_LO … #define OWL_EMAC_BIT_TDES0_NC … #define OWL_EMAC_BIT_TDES0_LC … #define OWL_EMAC_BIT_TDES0_EC … #define OWL_EMAC_MSK_TDES0_CC … #define OWL_EMAC_BIT_TDES0_UF … #define OWL_EMAC_BIT_TDES0_DE … /* Transmit descriptor control and count field */ #define OWL_EMAC_BIT_TDES1_IC … #define OWL_EMAC_BIT_TDES1_LS … #define OWL_EMAC_BIT_TDES1_FS … #define OWL_EMAC_BIT_TDES1_FT1 … #define OWL_EMAC_BIT_TDES1_SET … #define OWL_EMAC_BIT_TDES1_AC … #define OWL_EMAC_BIT_TDES1_TER … #define OWL_EMAC_BIT_TDES1_DPD … #define OWL_EMAC_BIT_TDES1_FT0 … #define OWL_EMAC_MSK_TDES1_TBS1 … static const char *const owl_emac_clk_names[] = …; #define OWL_EMAC_NCLKS … enum owl_emac_clk_map { … }; struct owl_emac_addr_list { … }; /* TX/RX descriptors */ struct owl_emac_ring_desc { … }; struct owl_emac_ring { … }; struct owl_emac_priv { … }; #endif /* __OWL_EMAC_H__ */
Codebase Browser
linux