/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ACENIC_H_ #define _ACENIC_H_ #include <linux/interrupt.h> /* * Generate TX index update each time, when TX ring is closed. * Normally, this is not useful, because results in more dma (and irqs * without TX_COAL_INTS_ONLY). */ #define USE_TX_COAL_NOW … /* * Addressing: * * The Tigon uses 64-bit host addresses, regardless of their actual * length, and it expects a big-endian format. For 32 bit systems the * upper 32 bits of the address are simply ignored (zero), however for * little endian 64 bit systems (Alpha) this looks strange with the * two parts of the address word being swapped. * * The addresses are split in two 32 bit words for all architectures * as some of them are in PCI shared memory and it is necessary to use * readl/writel to access them. * * The addressing code is derived from Pete Wyckoff's work, but * modified to deal properly with readl/writel usage. */ struct ace_regs { … }; aceaddr; #define ACE_WINDOW_SIZE … #define ACE_JUMBO_MTU … #define ACE_STD_MTU … #define ACE_TRACE_SIZE … /* * Host control register bits. */ #define IN_INT … #define CLR_INT … #define HW_RESET … #define BYTE_SWAP … #define WORD_SWAP … #define MASK_INTS … /* * Local control register bits. */ #define EEPROM_DATA_IN … #define EEPROM_DATA_OUT … #define EEPROM_WRITE_ENABLE … #define EEPROM_CLK_OUT … #define EEPROM_BASE … #define EEPROM_WRITE_SELECT … #define EEPROM_READ_SELECT … #define SRAM_BANK_512K … /* * udelay() values for when clocking the eeprom */ #define ACE_SHORT_DELAY … #define ACE_LONG_DELAY … /* * Misc Config bits */ #define SYNC_SRAM_TIMING … /* * CPU state bits. */ #define CPU_RESET … #define CPU_TRACE … #define CPU_PROM_FAILED … #define CPU_HALT … #define CPU_HALTED … /* * PCI State bits. */ #define DMA_READ_MAX_4 … #define DMA_READ_MAX_16 … #define DMA_READ_MAX_32 … #define DMA_READ_MAX_64 … #define DMA_READ_MAX_128 … #define DMA_READ_MAX_256 … #define DMA_READ_MAX_1K … #define DMA_WRITE_MAX_4 … #define DMA_WRITE_MAX_16 … #define DMA_WRITE_MAX_32 … #define DMA_WRITE_MAX_64 … #define DMA_WRITE_MAX_128 … #define DMA_WRITE_MAX_256 … #define DMA_WRITE_MAX_1K … #define DMA_READ_WRITE_MASK … #define MEM_READ_MULTIPLE … #define PCI_66MHZ … #define PCI_32BIT … #define DMA_WRITE_ALL_ALIGN … #define READ_CMD_MEM … #define WRITE_CMD_MEM … /* * Mode status */ #define ACE_BYTE_SWAP_BD … #define ACE_WORD_SWAP_BD … #define ACE_WARN … #define ACE_BYTE_SWAP_DMA … #define ACE_NO_JUMBO_FRAG … #define ACE_FATAL … /* * DMA config */ #define DMA_THRESH_1W … #define DMA_THRESH_2W … #define DMA_THRESH_4W … #define DMA_THRESH_8W … #define DMA_THRESH_16W … #define DMA_THRESH_32W … /* * Tuning parameters */ #define TICKS_PER_SEC … /* * Link bits */ #define LNK_PREF … #define LNK_10MB … #define LNK_100MB … #define LNK_1000MB … #define LNK_FULL_DUPLEX … #define LNK_HALF_DUPLEX … #define LNK_TX_FLOW_CTL_Y … #define LNK_NEG_ADVANCED … #define LNK_RX_FLOW_CTL_Y … #define LNK_NIC … #define LNK_JAM … #define LNK_JUMBO … #define LNK_ALTEON … #define LNK_NEG_FCTL … #define LNK_NEGOTIATE … #define LNK_ENABLE … #define LNK_UP … /* * Event definitions */ #define EVT_RING_ENTRIES … #define EVT_RING_SIZE … struct event { … }; /* * Events */ #define E_FW_RUNNING … #define E_STATS_UPDATED … #define E_STATS_UPDATE … #define E_LNK_STATE … #define E_C_LINK_UP … #define E_C_LINK_DOWN … #define E_C_LINK_10_100 … #define E_ERROR … #define E_C_ERR_INVAL_CMD … #define E_C_ERR_UNIMP_CMD … #define E_C_ERR_BAD_CFG … #define E_MCAST_LIST … #define E_C_MCAST_ADDR_ADD … #define E_C_MCAST_ADDR_DEL … #define E_RESET_JUMBO_RNG … /* * Commands */ #define CMD_RING_ENTRIES … struct cmd { … }; #define C_HOST_STATE … #define C_C_STACK_UP … #define C_C_STACK_DOWN … #define C_FDR_FILTERING … #define C_C_FDR_FILT_ENABLE … #define C_C_FDR_FILT_DISABLE … #define C_SET_RX_PRD_IDX … #define C_UPDATE_STATS … #define C_RESET_JUMBO_RNG … #define C_ADD_MULTICAST_ADDR … #define C_DEL_MULTICAST_ADDR … #define C_SET_PROMISC_MODE … #define C_C_PROMISC_ENABLE … #define C_C_PROMISC_DISABLE … #define C_LNK_NEGOTIATION … #define C_C_NEGOTIATE_BOTH … #define C_C_NEGOTIATE_GIG … #define C_C_NEGOTIATE_10_100 … #define C_SET_MAC_ADDR … #define C_CLEAR_PROFILE … #define C_SET_MULTICAST_MODE … #define C_C_MCAST_ENABLE … #define C_C_MCAST_DISABLE … #define C_CLEAR_STATS … #define C_SET_RX_JUMBO_PRD_IDX … #define C_REFRESH_STATS … /* * Descriptor flags */ #define BD_FLG_TCP_UDP_SUM … #define BD_FLG_IP_SUM … #define BD_FLG_END … #define BD_FLG_MORE … #define BD_FLG_JUMBO … #define BD_FLG_UCAST … #define BD_FLG_MCAST … #define BD_FLG_BCAST … #define BD_FLG_TYP_MASK … #define BD_FLG_IP_FRAG … #define BD_FLG_IP_FRAG_END … #define BD_FLG_VLAN_TAG … #define BD_FLG_FRAME_ERROR … #define BD_FLG_COAL_NOW … #define BD_FLG_MINI … /* * Ring Control block flags */ #define RCB_FLG_TCP_UDP_SUM … #define RCB_FLG_IP_SUM … #define RCB_FLG_NO_PSEUDO_HDR … #define RCB_FLG_VLAN_ASSIST … #define RCB_FLG_COAL_INT_ONLY … #define RCB_FLG_TX_HOST_RING … #define RCB_FLG_IEEE_SNAP_SUM … #define RCB_FLG_EXT_RX_BD … #define RCB_FLG_RNG_DISABLE … /* * TX ring - maximum TX ring entries for Tigon I's is 128 */ #define MAX_TX_RING_ENTRIES … #define TIGON_I_TX_RING_ENTRIES … #define TX_RING_SIZE … #define TX_RING_BASE … struct tx_desc{ … }; #define RX_STD_RING_ENTRIES … #define RX_STD_RING_SIZE … #define RX_JUMBO_RING_ENTRIES … #define RX_JUMBO_RING_SIZE … #define RX_MINI_RING_ENTRIES … #define RX_MINI_RING_SIZE … #define RX_RETURN_RING_ENTRIES … #define RX_RETURN_RING_SIZE … struct rx_desc{ … }; /* * This struct is shared with the NIC firmware. */ struct ring_ctrl { … }; struct ace_mac_stats { … }; struct ace_info { … }; struct ring_info { … }; /* * Funny... As soon as we add maplen on alpha, it starts to work * much slower. Hmm... is it because struct does not fit to one cacheline? * So, split tx_ring_info. */ struct tx_ring_info { … }; /* * struct ace_skb holding the rings of skb's. This is an awful lot of * pointers, but I don't see any other smart mode to do this in an * efficient manner ;-( */ struct ace_skb { … }; /* * Struct private for the AceNIC. * * Elements are grouped so variables used by the tx handling goes * together, and will go into the same cache lines etc. in order to * avoid cache line contention between the rx and tx handling on SMP. * * Frequently accessed variables are put at the beginning of the * struct to help the compiler generate better/shorter code. */ struct ace_private { … }; #define TX_RESERVED … static inline int tx_space (struct ace_private *ap, u32 csm, u32 prd) { … } #define tx_free(ap) … #define tx_ring_full(ap, csm, prd) … static inline void set_aceaddr(aceaddr *aa, dma_addr_t addr) { … } static inline void ace_set_txprd(struct ace_regs __iomem *regs, struct ace_private *ap, u32 value) { … } static inline void ace_mask_irq(struct net_device *dev) { … } static inline void ace_unmask_irq(struct net_device *dev) { … } /* * Prototypes */ static int ace_init(struct net_device *dev); static void ace_load_std_rx_ring(struct net_device *dev, int nr_bufs); static void ace_load_mini_rx_ring(struct net_device *dev, int nr_bufs); static void ace_load_jumbo_rx_ring(struct net_device *dev, int nr_bufs); static irqreturn_t ace_interrupt(int irq, void *dev_id); static int ace_load_firmware(struct net_device *dev); static int ace_open(struct net_device *dev); static netdev_tx_t ace_start_xmit(struct sk_buff *skb, struct net_device *dev); static int ace_close(struct net_device *dev); static void ace_tasklet(struct tasklet_struct *t); static void ace_dump_trace(struct ace_private *ap); static void ace_set_multicast_list(struct net_device *dev); static int ace_change_mtu(struct net_device *dev, int new_mtu); static int ace_set_mac_addr(struct net_device *dev, void *p); static void ace_set_rxtx_parms(struct net_device *dev, int jumbo); static int ace_allocate_descriptors(struct net_device *dev); static void ace_free_descriptors(struct net_device *dev); static void ace_init_cleanup(struct net_device *dev); static struct net_device_stats *ace_get_stats(struct net_device *dev); static int read_eeprom_byte(struct net_device *dev, unsigned long offset); #endif /* _ACENIC_H_ */
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