linux/drivers/net/ethernet/amazon/ena/ena_regs_defs.h

/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
/*
 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
 */
#ifndef _ENA_REGS_H_
#define _ENA_REGS_H_

enum ena_regs_reset_reason_types {};

/* ena_registers offsets */

/* 0 base */
#define ENA_REGS_VERSION_OFF
#define ENA_REGS_CONTROLLER_VERSION_OFF
#define ENA_REGS_CAPS_OFF
#define ENA_REGS_CAPS_EXT_OFF
#define ENA_REGS_AQ_BASE_LO_OFF
#define ENA_REGS_AQ_BASE_HI_OFF
#define ENA_REGS_AQ_CAPS_OFF
#define ENA_REGS_ACQ_BASE_LO_OFF
#define ENA_REGS_ACQ_BASE_HI_OFF
#define ENA_REGS_ACQ_CAPS_OFF
#define ENA_REGS_AQ_DB_OFF
#define ENA_REGS_ACQ_TAIL_OFF
#define ENA_REGS_AENQ_CAPS_OFF
#define ENA_REGS_AENQ_BASE_LO_OFF
#define ENA_REGS_AENQ_BASE_HI_OFF
#define ENA_REGS_AENQ_HEAD_DB_OFF
#define ENA_REGS_AENQ_TAIL_OFF
#define ENA_REGS_INTR_MASK_OFF
#define ENA_REGS_DEV_CTL_OFF
#define ENA_REGS_DEV_STS_OFF
#define ENA_REGS_MMIO_REG_READ_OFF
#define ENA_REGS_MMIO_RESP_LO_OFF
#define ENA_REGS_MMIO_RESP_HI_OFF
#define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF

/* version register */
#define ENA_REGS_VERSION_MINOR_VERSION_MASK
#define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT
#define ENA_REGS_VERSION_MAJOR_VERSION_MASK

/* controller_version register */
#define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK
#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT
#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK
#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT
#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK
#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT
#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK

/* caps register */
#define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK
#define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT
#define ENA_REGS_CAPS_RESET_TIMEOUT_MASK
#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT
#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK
#define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT
#define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK

/* aq_caps register */
#define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK
#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT
#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK

/* acq_caps register */
#define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK
#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT
#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK

/* aenq_caps register */
#define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK
#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT
#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK

/* dev_ctl register */
#define ENA_REGS_DEV_CTL_DEV_RESET_MASK
#define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT
#define ENA_REGS_DEV_CTL_AQ_RESTART_MASK
#define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT
#define ENA_REGS_DEV_CTL_QUIESCENT_MASK
#define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT
#define ENA_REGS_DEV_CTL_IO_RESUME_MASK
#define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT
#define ENA_REGS_DEV_CTL_RESET_REASON_MASK

/* dev_sts register */
#define ENA_REGS_DEV_STS_READY_MASK
#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT
#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK
#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT
#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK
#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT
#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK
#define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT
#define ENA_REGS_DEV_STS_RESET_FINISHED_MASK
#define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT
#define ENA_REGS_DEV_STS_FATAL_ERROR_MASK
#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT
#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK
#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT
#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK

/* mmio_reg_read register */
#define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK
#define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT
#define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK

/* rss_ind_entry_update register */
#define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK
#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT
#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK

#endif /* _ENA_REGS_H_ */