linux/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Applied Micro X-Gene SoC Ethernet Driver
 *
 * Copyright (c) 2014, Applied Micro Circuits Corporation
 * Authors: Iyappan Subramanian <[email protected]>
 *	    Keyur Chudgar <[email protected]>
 */

#ifndef __XGENE_ENET_XGMAC_H__
#define __XGENE_ENET_XGMAC_H__

#define X2_BLOCK_ETH_MAC_CSR_OFFSET …
#define BLOCK_AXG_MAC_OFFSET …
#define BLOCK_AXG_STATS_OFFSET …
#define BLOCK_AXG_MAC_CSR_OFFSET …
#define BLOCK_PCS_OFFSET …

#define XGENET_CONFIG_REG_ADDR …
#define XGENET_SRST_ADDR …
#define XGENET_CLKEN_ADDR …

#define CSR_CLK …
#define XGENET_CLK …
#define PCS_CLK …
#define AN_REF_CLK …
#define AN_CLK …
#define AD_CLK …

#define CSR_RST …
#define XGENET_RST …
#define PCS_RST …
#define AN_REF_RST …
#define AN_RST …
#define AD_RST …

#define AXGMAC_CONFIG_0 …
#define AXGMAC_CONFIG_1 …
#define HSTMACRST …
#define HSTTCTLEN …
#define HSTTFEN …
#define HSTRCTLEN …
#define HSTRFEN …
#define HSTPPEN …
#define HSTDRPLT64 …
#define HSTLENCHK …
#define HSTMACADR_LSW_ADDR …
#define HSTMACADR_MSW_ADDR …
#define HSTMAXFRAME_LENGTH_ADDR …

#define XG_MCX_RX_DV_GATE_REG_0_ADDR …
#define XG_MCX_ECM_CFG_0_ADDR …
#define XG_MCX_MULTI_DPF0_ADDR …
#define XG_MCX_MULTI_DPF1_ADDR …
#define XG_DEF_PAUSE_THRES …
#define XG_DEF_PAUSE_OFF_THRES …
#define XG_RSIF_CONFIG_REG_ADDR …
#define XG_RSIF_CLE_BUFF_THRESH …
#define RSIF_CLE_BUFF_THRESH_SET(dst, val) …
#define XG_RSIF_CONFIG1_REG_ADDR …
#define XG_RSIF_PLC_CLE_BUFF_THRESH …
#define RSIF_PLC_CLE_BUFF_THRESH_SET(dst, val) …
#define XG_MCX_ECM_CONFIG0_REG_0_ADDR …
#define XG_MCX_ICM_ECM_DROP_COUNT_REG0_ADDR …
#define XCLE_BYPASS_REG0_ADDR …
#define XCLE_BYPASS_REG1_ADDR …
#define XG_CFG_BYPASS_ADDR …
#define XG_CFG_LINK_AGGR_RESUME_0_ADDR …
#define XG_LINK_STATUS_ADDR …
#define XG_TSIF_MSS_REG0_ADDR …
#define XG_DEBUG_REG_ADDR …
#define XG_ENET_SPARE_CFG_REG_ADDR …
#define XG_ENET_SPARE_CFG_REG_1_ADDR …
#define XGENET_RX_DV_GATE_REG_0_ADDR …
#define XGENET_ECM_CONFIG0_REG_0 …
#define XGENET_ICM_ECM_DROP_COUNT_REG0 …
#define XGENET_CSR_ECM_CFG_0_ADDR …
#define XGENET_CSR_MULTI_DPF0_ADDR …
#define XGENET_CSR_MULTI_DPF1_ADDR …
#define XG_RXBUF_PAUSE_THRESH …
#define XG_MCX_ICM_CONFIG0_REG_0_ADDR …
#define XG_MCX_ICM_CONFIG2_REG_0_ADDR …

#define PCS_CONTROL_1 …
#define PCS_CTRL_PCS_RST …

extern const struct xgene_mac_ops xgene_xgmac_ops;
extern const struct xgene_port_ops xgene_xgport_ops;

#endif /* __XGENE_ENET_XGMAC_H__ */