// SPDX-License-Identifier: GPL-2.0-only /* * sl28cpld PWM driver * * Copyright (c) 2020 Michael Walle <[email protected]> * * There is no public datasheet available for this PWM core. But it is easy * enough to be briefly explained. It consists of one 8-bit counter. The PWM * supports four distinct frequencies by selecting when to reset the counter. * With the prescaler setting you can select which bit of the counter is used * to reset it. This implies that the higher the frequency the less remaining * bits are available for the actual counter. * * Let cnt[7:0] be the counter, clocked at 32kHz: * +-----------+--------+--------------+-----------+---------------+ * | prescaler | reset | counter bits | frequency | period length | * +-----------+--------+--------------+-----------+---------------+ * | 0 | cnt[7] | cnt[6:0] | 250 Hz | 4000000 ns | * | 1 | cnt[6] | cnt[5:0] | 500 Hz | 2000000 ns | * | 2 | cnt[5] | cnt[4:0] | 1 kHz | 1000000 ns | * | 3 | cnt[4] | cnt[3:0] | 2 kHz | 500000 ns | * +-----------+--------+--------------+-----------+---------------+ * * Limitations: * - The hardware cannot generate a 100% duty cycle if the prescaler is 0. * - The hardware cannot atomically set the prescaler and the counter value, * which might lead to glitches and inconsistent states if a write fails. * - The counter is not reset if you switch the prescaler which leads * to glitches, too. * - The duty cycle will switch immediately and not after a complete cycle. * - Depending on the actual implementation, disabling the PWM might have * side effects. For example, if the output pin is shared with a GPIO pin * it will automatically switch back to GPIO mode. */ #include <linux/bitfield.h> #include <linux/kernel.h> #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/pwm.h> #include <linux/regmap.h> /* * PWM timer block registers. */ #define SL28CPLD_PWM_CTRL … #define SL28CPLD_PWM_CTRL_ENABLE … #define SL28CPLD_PWM_CTRL_PRESCALER_MASK … #define SL28CPLD_PWM_CYCLE … #define SL28CPLD_PWM_CYCLE_MAX … #define SL28CPLD_PWM_CLK … #define SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler) … #define SL28CPLD_PWM_PERIOD(prescaler) … /* * We calculate the duty cycle like this: * duty_cycle_ns = pwm_cycle_reg * max_period_ns / max_duty_cycle * * With * max_period_ns = 1 << (7 - prescaler) / SL28CPLD_PWM_CLK * NSEC_PER_SEC * max_duty_cycle = 1 << (7 - prescaler) * this then simplifies to: * duty_cycle_ns = pwm_cycle_reg / SL28CPLD_PWM_CLK * NSEC_PER_SEC * = NSEC_PER_SEC / SL28CPLD_PWM_CLK * pwm_cycle_reg * * NSEC_PER_SEC is a multiple of SL28CPLD_PWM_CLK, therefore we're not losing * precision by doing the divison first. */ #define SL28CPLD_PWM_TO_DUTY_CYCLE(reg) … #define SL28CPLD_PWM_FROM_DUTY_CYCLE(duty_cycle) … #define sl28cpld_pwm_read(priv, reg, val) … #define sl28cpld_pwm_write(priv, reg, val) … struct sl28cpld_pwm { … }; static inline struct sl28cpld_pwm *sl28cpld_pwm_from_chip(struct pwm_chip *chip) { … } static int sl28cpld_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_state *state) { … } static int sl28cpld_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, const struct pwm_state *state) { … } static const struct pwm_ops sl28cpld_pwm_ops = …; static int sl28cpld_pwm_probe(struct platform_device *pdev) { … } static const struct of_device_id sl28cpld_pwm_of_match[] = …; MODULE_DEVICE_TABLE(of, sl28cpld_pwm_of_match); static struct platform_driver sl28cpld_pwm_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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