/* SPDX-License-Identifier: GPL-2.0-or-later */ /* atl2.h -- atl2 driver definitions * * Copyright(c) 2007 Atheros Corporation. All rights reserved. * Copyright(c) 2006 xiong huang <[email protected]> * Copyright(c) 2007 Chris Snook <[email protected]> * * Derived from Intel e1000 driver * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. */ #ifndef _ATL2_H_ #define _ATL2_H_ #include <linux/atomic.h> #include <linux/netdevice.h> #ifndef _ATL2_HW_H_ #define _ATL2_HW_H_ #ifndef _ATL2_OSDEP_H_ #define _ATL2_OSDEP_H_ #include <linux/pci.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/if_ether.h> #include "atlx.h" #ifdef ETHTOOL_OPS_COMPAT int ethtool_ioctl(struct ifreq *ifr); #endif #define PCI_COMMAND_REGISTER … #define CMD_MEM_WRT_INVALIDATE … #define ATL2_WRITE_REG(a, reg, value) … #define ATL2_WRITE_FLUSH(a) … #define ATL2_READ_REG(a, reg) … #define ATL2_WRITE_REGB(a, reg, value) … #define ATL2_READ_REGB(a, reg) … #define ATL2_WRITE_REGW(a, reg, value) … #define ATL2_READ_REGW(a, reg) … #define ATL2_WRITE_REG_ARRAY(a, reg, offset, value) … #define ATL2_READ_REG_ARRAY(a, reg, offset) … #endif /* _ATL2_OSDEP_H_ */ struct atl2_adapter; struct atl2_hw; /* function prototype */ static s32 atl2_reset_hw(struct atl2_hw *hw); static s32 atl2_read_mac_addr(struct atl2_hw *hw); static s32 atl2_init_hw(struct atl2_hw *hw); static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, u16 *duplex); static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr); static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value); static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data); static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data); static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value); static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value); static void atl2_set_mac_addr(struct atl2_hw *hw); static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue); static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value); static s32 atl2_phy_init(struct atl2_hw *hw); static int atl2_check_eeprom_exist(struct atl2_hw *hw); static void atl2_force_ps(struct atl2_hw *hw); /* register definition */ /* Block IDLE Status Register */ #define IDLE_STATUS_RXMAC … #define IDLE_STATUS_TXMAC … #define IDLE_STATUS_DMAR … #define IDLE_STATUS_DMAW … /* MDIO Control Register */ #define MDIO_WAIT_TIMES … /* MAC Control Register */ #define MAC_CTRL_DBG_TX_BKPRESURE … #define MAC_CTRL_MACLP_CLK_PHY … #define MAC_CTRL_HALF_LEFT_BUF_SHIFT … #define MAC_CTRL_HALF_LEFT_BUF_MASK … /* Internal SRAM Partition Register */ #define REG_SRAM_TXRAM_END … #define REG_SRAM_RXRAM_END … /* Descriptor Control register */ #define REG_TXD_BASE_ADDR_LO … #define REG_TXD_MEM_SIZE … #define REG_TXS_BASE_ADDR_LO … #define REG_TXS_MEM_SIZE … #define REG_RXD_BASE_ADDR_LO … #define REG_RXD_BUF_NUM … /* DMAR Control Register */ #define REG_DMAR … #define DMAR_EN … /* TX Cur-Through (early tx threshold) Control Register */ #define REG_TX_CUT_THRESH … /* DMAW Control Register */ #define REG_DMAW … #define DMAW_EN … /* Flow control register */ #define REG_PAUSE_ON_TH … #define REG_PAUSE_OFF_TH … /* Mailbox Register */ #define REG_MB_TXD_WR_IDX … #define REG_MB_RXD_RD_IDX … /* Interrupt Status Register */ #define ISR_TIMER … #define ISR_MANUAL … #define ISR_RXF_OV … #define ISR_TXF_UR … #define ISR_TXS_OV … #define ISR_RXS_OV … #define ISR_LINK_CHG … #define ISR_HOST_TXD_UR … #define ISR_HOST_RXD_OV … #define ISR_DMAR_TO_RST … #define ISR_DMAW_TO_RST … #define ISR_PHY … #define ISR_TS_UPDATE … #define ISR_RS_UPDATE … #define ISR_TX_EARLY … #define ISR_TX_EVENT … #define ISR_RX_EVENT … #define IMR_NORMAL_MASK … /* Receive MAC Statistics Registers */ #define REG_STS_RX_PAUSE … #define REG_STS_RXD_OV … #define REG_STS_RXS_OV … #define REG_STS_RX_FILTER … /* MII definitions */ /* PHY Common Register */ #define MII_SMARTSPEED … #define MII_DBG_ADDR … #define MII_DBG_DATA … /* PCI Command Register Bit Definitions */ #define PCI_REG_COMMAND … #define CMD_IO_SPACE … #define CMD_MEMORY_SPACE … #define CMD_BUS_MASTER … #define MEDIA_TYPE_100M_FULL … #define MEDIA_TYPE_100M_HALF … #define MEDIA_TYPE_10M_FULL … #define MEDIA_TYPE_10M_HALF … #define AUTONEG_ADVERTISE_SPEED_DEFAULT … /* The size (in bytes) of a ethernet packet */ #define MAXIMUM_ETHERNET_FRAME_SIZE … #define MINIMUM_ETHERNET_FRAME_SIZE … #define MAX_JUMBO_FRAME_SIZE … struct tx_pkt_header { … }; /* FIXME: replace above bitfields with MASK/SHIFT defines below */ #define TX_PKT_HEADER_SIZE_MASK … #define TX_PKT_HEADER_SIZE_SHIFT … #define TX_PKT_HEADER_INS_VLAN_MASK … #define TX_PKT_HEADER_INS_VLAN_SHIFT … #define TX_PKT_HEADER_VLAN_TAG_MASK … #define TX_PKT_HEADER_VLAN_TAG_SHIFT … struct tx_pkt_status { … }; /* FIXME: replace above bitfields with MASK/SHIFT defines below */ #define TX_PKT_STATUS_SIZE_MASK … #define TX_PKT_STATUS_SIZE_SHIFT … #define TX_PKT_STATUS_OK_MASK … #define TX_PKT_STATUS_OK_SHIFT … #define TX_PKT_STATUS_BCAST_MASK … #define TX_PKT_STATUS_BCAST_SHIFT … #define TX_PKT_STATUS_MCAST_MASK … #define TX_PKT_STATUS_MCAST_SHIFT … #define TX_PKT_STATUS_PAUSE_MASK … #define TX_PKT_STATUS_PAUSE_SHIFT … #define TX_PKT_STATUS_CTRL_MASK … #define TX_PKT_STATUS_CTRL_SHIFT … #define TX_PKT_STATUS_DEFER_MASK … #define TX_PKT_STATUS_DEFER_SHIFT … #define TX_PKT_STATUS_EXC_DEFER_MASK … #define TX_PKT_STATUS_EXC_DEFER_SHIFT … #define TX_PKT_STATUS_SINGLE_COL_MASK … #define TX_PKT_STATUS_SINGLE_COL_SHIFT … #define TX_PKT_STATUS_MULTI_COL_MASK … #define TX_PKT_STATUS_MULTI_COL_SHIFT … #define TX_PKT_STATUS_LATE_COL_MASK … #define TX_PKT_STATUS_LATE_COL_SHIFT … #define TX_PKT_STATUS_ABORT_COL_MASK … #define TX_PKT_STATUS_ABORT_COL_SHIFT … #define TX_PKT_STATUS_UNDERRUN_MASK … #define TX_PKT_STATUS_UNDERRUN_SHIFT … #define TX_PKT_STATUS_UPDATE_MASK … #define TX_PKT_STATUS_UPDATE_SHIFT … struct rx_pkt_status { … }; /* FIXME: replace above bitfields with MASK/SHIFT defines below */ #define RX_PKT_STATUS_SIZE_MASK … #define RX_PKT_STATUS_SIZE_SHIFT … #define RX_PKT_STATUS_OK_MASK … #define RX_PKT_STATUS_OK_SHIFT … #define RX_PKT_STATUS_BCAST_MASK … #define RX_PKT_STATUS_BCAST_SHIFT … #define RX_PKT_STATUS_MCAST_MASK … #define RX_PKT_STATUS_MCAST_SHIFT … #define RX_PKT_STATUS_PAUSE_MASK … #define RX_PKT_STATUS_PAUSE_SHIFT … #define RX_PKT_STATUS_CTRL_MASK … #define RX_PKT_STATUS_CTRL_SHIFT … #define RX_PKT_STATUS_CRC_MASK … #define RX_PKT_STATUS_CRC_SHIFT … #define RX_PKT_STATUS_CODE_MASK … #define RX_PKT_STATUS_CODE_SHIFT … #define RX_PKT_STATUS_RUNT_MASK … #define RX_PKT_STATUS_RUNT_SHIFT … #define RX_PKT_STATUS_FRAG_MASK … #define RX_PKT_STATUS_FRAG_SHIFT … #define RX_PKT_STATUS_TRUNK_MASK … #define RX_PKT_STATUS_TRUNK_SHIFT … #define RX_PKT_STATUS_ALIGN_MASK … #define RX_PKT_STATUS_ALIGN_SHIFT … #define RX_PKT_STATUS_VLAN_MASK … #define RX_PKT_STATUS_VLAN_SHIFT … #define RX_PKT_STATUS_UPDATE_MASK … #define RX_PKT_STATUS_UPDATE_SHIFT … #define RX_PKT_STATUS_VLAN_TAG_MASK … #define RX_PKT_STATUS_VLAN_TAG_SHIFT … struct rx_desc { … }; enum atl2_speed_duplex { … }; struct atl2_spi_flash_dev { … }; /* Structure containing variables used by the shared code (atl2_hw.c) */ struct atl2_hw { … }; #endif /* _ATL2_HW_H_ */ struct atl2_ring_header { … }; /* board specific private data structure */ struct atl2_adapter { … }; enum atl2_state_t { … }; #endif /* _ATL2_H_ */
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