/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved. * Copyright(c) 2006 - 2007 Chris Snook <[email protected]> * Copyright(c) 2006 - 2008 Jay Cliburn <[email protected]> * * Derived from Intel e1000 driver * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. */ #ifndef ATL1_H #define ATL1_H #include <linux/compiler.h> #include <linux/ethtool.h> #include <linux/if_vlan.h> #include <linux/mii.h> #include <linux/module.h> #include <linux/skbuff.h> #include <linux/spinlock.h> #include <linux/timer.h> #include <linux/types.h> #include <linux/workqueue.h> #include "atlx.h" #define ATLX_DRIVER_NAME … MODULE_DESCRIPTION(…) …; #define atlx_adapter … #define atlx_check_for_link … #define atlx_check_link … #define atlx_hash_mc_addr … #define atlx_hash_set … #define atlx_hw … #define atlx_mii_ioctl … #define atlx_read_phy_reg … #define atlx_set_mac … #define atlx_set_mac_addr … struct atl1_adapter; struct atl1_hw; /* function prototypes needed by multiple files */ static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr); static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value); static void atl1_set_mac_addr(struct atl1_hw *hw); static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); static u32 atl1_check_link(struct atl1_adapter *adapter); /* hardware definitions specific to L1 */ /* Block IDLE Status Register */ #define IDLE_STATUS_RXMAC … #define IDLE_STATUS_TXMAC … #define IDLE_STATUS_RXQ … #define IDLE_STATUS_TXQ … #define IDLE_STATUS_DMAR … #define IDLE_STATUS_DMAW … #define IDLE_STATUS_SMB … #define IDLE_STATUS_CMB … /* MDIO Control Register */ #define MDIO_WAIT_TIMES … /* MAC Control Register */ #define MAC_CTRL_TX_PAUSE … #define MAC_CTRL_SCNT … #define MAC_CTRL_SRST_TX … #define MAC_CTRL_TX_SIMURST … #define MAC_CTRL_SPEED_SHIFT … #define MAC_CTRL_SPEED_MASK … #define MAC_CTRL_SPEED_1000 … #define MAC_CTRL_SPEED_10_100 … #define MAC_CTRL_DBG_TX_BKPRESURE … #define MAC_CTRL_TX_HUGE … #define MAC_CTRL_RX_CHKSUM_EN … #define MAC_CTRL_DBG … /* Wake-On-Lan control register */ #define WOL_CLK_SWITCH_EN … #define WOL_PT5_EN … #define WOL_PT6_EN … #define WOL_PT5_MATCH … #define WOL_PT6_MATCH … /* WOL Length ( 2 DWORD ) */ #define REG_WOL_PATTERN_LEN … #define WOL_PT_LEN_MASK … #define WOL_PT0_LEN_SHIFT … #define WOL_PT1_LEN_SHIFT … #define WOL_PT2_LEN_SHIFT … #define WOL_PT3_LEN_SHIFT … #define WOL_PT4_LEN_SHIFT … #define WOL_PT5_LEN_SHIFT … #define WOL_PT6_LEN_SHIFT … /* Internal SRAM Partition Registers, low 32 bits */ #define REG_SRAM_RFD_LEN … #define REG_SRAM_RRD_ADDR … #define REG_SRAM_RRD_LEN … #define REG_SRAM_TPD_ADDR … #define REG_SRAM_TPD_LEN … #define REG_SRAM_TRD_ADDR … #define REG_SRAM_TRD_LEN … #define REG_SRAM_RXF_ADDR … #define REG_SRAM_RXF_LEN … #define REG_SRAM_TXF_ADDR … #define REG_SRAM_TXF_LEN … #define REG_SRAM_TCPH_PATH_ADDR … #define SRAM_TCPH_ADDR_MASK … #define SRAM_TCPH_ADDR_SHIFT … #define SRAM_PATH_ADDR_MASK … #define SRAM_PATH_ADDR_SHIFT … /* Load Ptr Register */ #define REG_LOAD_PTR … /* Descriptor Control registers, low 32 bits */ #define REG_DESC_RFD_ADDR_LO … #define REG_DESC_RRD_ADDR_LO … #define REG_DESC_TPD_ADDR_LO … #define REG_DESC_CMB_ADDR_LO … #define REG_DESC_SMB_ADDR_LO … #define REG_DESC_RFD_RRD_RING_SIZE … #define DESC_RFD_RING_SIZE_MASK … #define DESC_RFD_RING_SIZE_SHIFT … #define DESC_RRD_RING_SIZE_MASK … #define DESC_RRD_RING_SIZE_SHIFT … #define REG_DESC_TPD_RING_SIZE … #define DESC_TPD_RING_SIZE_MASK … #define DESC_TPD_RING_SIZE_SHIFT … /* TXQ Control Register */ #define REG_TXQ_CTRL … #define TXQ_CTRL_TPD_BURST_NUM_SHIFT … #define TXQ_CTRL_TPD_BURST_NUM_MASK … #define TXQ_CTRL_EN … #define TXQ_CTRL_ENH_MODE … #define TXQ_CTRL_TPD_FETCH_TH_SHIFT … #define TXQ_CTRL_TPD_FETCH_TH_MASK … #define TXQ_CTRL_TXF_BURST_NUM_SHIFT … #define TXQ_CTRL_TXF_BURST_NUM_MASK … /* Jumbo packet Threshold for task offload */ #define REG_TX_JUMBO_TASK_TH_TPD_IPG … #define TX_JUMBO_TASK_TH_MASK … #define TX_JUMBO_TASK_TH_SHIFT … #define TX_TPD_MIN_IPG_MASK … #define TX_TPD_MIN_IPG_SHIFT … /* RXQ Control Register */ #define REG_RXQ_CTRL … #define RXQ_CTRL_RFD_BURST_NUM_SHIFT … #define RXQ_CTRL_RFD_BURST_NUM_MASK … #define RXQ_CTRL_RRD_BURST_THRESH_SHIFT … #define RXQ_CTRL_RRD_BURST_THRESH_MASK … #define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT … #define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK … #define RXQ_CTRL_CUT_THRU_EN … #define RXQ_CTRL_EN … /* Rx jumbo packet threshold and rrd retirement timer */ #define REG_RXQ_JMBOSZ_RRDTIM … #define RXQ_JMBOSZ_TH_MASK … #define RXQ_JMBOSZ_TH_SHIFT … #define RXQ_JMBO_LKAH_MASK … #define RXQ_JMBO_LKAH_SHIFT … #define RXQ_RRD_TIMER_MASK … #define RXQ_RRD_TIMER_SHIFT … /* RFD flow control register */ #define REG_RXQ_RXF_PAUSE_THRESH … #define RXQ_RXF_PAUSE_TH_HI_SHIFT … #define RXQ_RXF_PAUSE_TH_HI_MASK … #define RXQ_RXF_PAUSE_TH_LO_SHIFT … #define RXQ_RXF_PAUSE_TH_LO_MASK … /* RRD flow control register */ #define REG_RXQ_RRD_PAUSE_THRESH … #define RXQ_RRD_PAUSE_TH_HI_SHIFT … #define RXQ_RRD_PAUSE_TH_HI_MASK … #define RXQ_RRD_PAUSE_TH_LO_SHIFT … #define RXQ_RRD_PAUSE_TH_LO_MASK … /* DMA Engine Control Register */ #define REG_DMA_CTRL … #define DMA_CTRL_DMAR_IN_ORDER … #define DMA_CTRL_DMAR_ENH_ORDER … #define DMA_CTRL_DMAR_OUT_ORDER … #define DMA_CTRL_RCB_VALUE … #define DMA_CTRL_DMAR_BURST_LEN_SHIFT … #define DMA_CTRL_DMAR_BURST_LEN_MASK … #define DMA_CTRL_DMAW_BURST_LEN_SHIFT … #define DMA_CTRL_DMAW_BURST_LEN_MASK … #define DMA_CTRL_DMAR_EN … #define DMA_CTRL_DMAW_EN … /* CMB/SMB Control Register */ #define REG_CSMB_CTRL … #define CSMB_CTRL_CMB_NOW … #define CSMB_CTRL_SMB_NOW … #define CSMB_CTRL_CMB_EN … #define CSMB_CTRL_SMB_EN … /* CMB DMA Write Threshold Register */ #define REG_CMB_WRITE_TH … #define CMB_RRD_TH_SHIFT … #define CMB_RRD_TH_MASK … #define CMB_TPD_TH_SHIFT … #define CMB_TPD_TH_MASK … /* RX/TX count-down timer to trigger CMB-write. 2us resolution. */ #define REG_CMB_WRITE_TIMER … #define CMB_RX_TM_SHIFT … #define CMB_RX_TM_MASK … #define CMB_TX_TM_SHIFT … #define CMB_TX_TM_MASK … /* Number of packet received since last CMB write */ #define REG_CMB_RX_PKT_CNT … /* Number of packet transmitted since last CMB write */ #define REG_CMB_TX_PKT_CNT … /* SMB auto DMA timer register */ #define REG_SMB_TIMER … /* Mailbox Register */ #define REG_MAILBOX … #define MB_RFD_PROD_INDX_SHIFT … #define MB_RFD_PROD_INDX_MASK … #define MB_RRD_CONS_INDX_SHIFT … #define MB_RRD_CONS_INDX_MASK … #define MB_TPD_PROD_INDX_SHIFT … #define MB_TPD_PROD_INDX_MASK … /* Interrupt Status Register */ #define ISR_SMB … #define ISR_TIMER … #define ISR_MANUAL … #define ISR_RXF_OV … #define ISR_RFD_UNRUN … #define ISR_RRD_OV … #define ISR_TXF_UNRUN … #define ISR_LINK … #define ISR_HOST_RFD_UNRUN … #define ISR_HOST_RRD_OV … #define ISR_DMAR_TO_RST … #define ISR_DMAW_TO_RST … #define ISR_GPHY … #define ISR_RX_PKT … #define ISR_TX_PKT … #define ISR_TX_DMA … #define ISR_RX_DMA … #define ISR_CMB_RX … #define ISR_CMB_TX … #define ISR_MAC_RX … #define ISR_MAC_TX … #define ISR_DIS_SMB … #define ISR_DIS_DMA … /* Normal Interrupt mask without RX/TX enabled */ #define IMR_NORXTX_MASK … /* Normal Interrupt mask */ #define IMR_NORMAL_MASK … /* Debug Interrupt Mask (enable all interrupt) */ #define IMR_DEBUG_MASK … #define MEDIA_TYPE_1000M_FULL … #define MEDIA_TYPE_100M_FULL … #define MEDIA_TYPE_100M_HALF … #define MEDIA_TYPE_10M_FULL … #define MEDIA_TYPE_10M_HALF … #define AUTONEG_ADVERTISE_SPEED_DEFAULT … #define MAX_JUMBO_FRAME_SIZE … #define ATL1_EEDUMP_LEN … /* Statistics counters collected by the MAC */ struct stats_msg_block { … }; /* Coalescing Message Block */ struct coals_msg_block { … }; /* RRD descriptor */ struct rx_return_desc { … }; #define PACKET_FLAG_ETH_TYPE … #define PACKET_FLAG_VLAN_INS … #define PACKET_FLAG_ERR … #define PACKET_FLAG_IPV4 … #define PACKET_FLAG_UDP … #define PACKET_FLAG_TCP … #define PACKET_FLAG_BCAST … #define PACKET_FLAG_MCAST … #define PACKET_FLAG_PAUSE … #define ERR_FLAG_CRC … #define ERR_FLAG_CODE … #define ERR_FLAG_DRIBBLE … #define ERR_FLAG_RUNT … #define ERR_FLAG_OV … #define ERR_FLAG_TRUNC … #define ERR_FLAG_IP_CHKSUM … #define ERR_FLAG_L4_CHKSUM … #define ERR_FLAG_LEN … #define ERR_FLAG_DES_ADDR … /* RFD descriptor */ struct rx_free_desc { … } __packed; /* * The L1 transmit packet descriptor is comprised of four 32-bit words. * * 31 0 * +---------------------------------------+ * | Word 0: Buffer addr lo | * +---------------------------------------+ * | Word 1: Buffer addr hi | * +---------------------------------------+ * | Word 2 | * +---------------------------------------+ * | Word 3 | * +---------------------------------------+ * * Words 0 and 1 combine to form a 64-bit buffer address. * * Word 2 is self explanatory in the #define block below. * * Word 3 has two forms, depending upon the state of bits 3 and 4. * If bits 3 and 4 are both zero, then bits 14:31 are unused by the * hardware. Otherwise, if either bit 3 or 4 is set, the definition * of bits 14:31 vary according to the following depiction. * * 0 End of packet 0 End of packet * 1 Coalesce 1 Coalesce * 2 Insert VLAN tag 2 Insert VLAN tag * 3 Custom csum enable = 0 3 Custom csum enable = 1 * 4 Segment enable = 1 4 Segment enable = 0 * 5 Generate IP checksum 5 Generate IP checksum * 6 Generate TCP checksum 6 Generate TCP checksum * 7 Generate UDP checksum 7 Generate UDP checksum * 8 VLAN tagged 8 VLAN tagged * 9 Ethernet frame type 9 Ethernet frame type * 10-+ 10-+ * 11 | IP hdr length (10:13) 11 | IP hdr length (10:13) * 12 | (num 32-bit words) 12 | (num 32-bit words) * 13-+ 13-+ * 14-+ 14 Unused * 15 | TCP hdr length (14:17) 15 Unused * 16 | (num 32-bit words) 16-+ * 17-+ 17 | * 18 Header TPD flag 18 | * 19-+ 19 | Payload offset * 20 | 20 | (16:23) * 21 | 21 | * 22 | 22 | * 23 | 23-+ * 24 | 24-+ * 25 | MSS (19:31) 25 | * 26 | 26 | * 27 | 27 | Custom csum offset * 28 | 28 | (24:31) * 29 | 29 | * 30 | 30 | * 31-+ 31-+ */ /* tpd word 2 */ #define TPD_BUFLEN_MASK … #define TPD_BUFLEN_SHIFT … #define TPD_DMAINT_MASK … #define TPD_DMAINT_SHIFT … #define TPD_PKTNT_MASK … #define TPD_PKTINT_SHIFT … #define TPD_VLANTAG_MASK … #define TPD_VLANTAG_SHIFT … /* tpd word 3 bits 0:13 */ #define TPD_EOP_MASK … #define TPD_EOP_SHIFT … #define TPD_COALESCE_MASK … #define TPD_COALESCE_SHIFT … #define TPD_INS_VL_TAG_MASK … #define TPD_INS_VL_TAG_SHIFT … #define TPD_CUST_CSUM_EN_MASK … #define TPD_CUST_CSUM_EN_SHIFT … #define TPD_SEGMENT_EN_MASK … #define TPD_SEGMENT_EN_SHIFT … #define TPD_IP_CSUM_MASK … #define TPD_IP_CSUM_SHIFT … #define TPD_TCP_CSUM_MASK … #define TPD_TCP_CSUM_SHIFT … #define TPD_UDP_CSUM_MASK … #define TPD_UDP_CSUM_SHIFT … #define TPD_VL_TAGGED_MASK … #define TPD_VL_TAGGED_SHIFT … #define TPD_ETHTYPE_MASK … #define TPD_ETHTYPE_SHIFT … #define TPD_IPHL_MASK … #define TPD_IPHL_SHIFT … /* tpd word 3 bits 14:31 if segment enabled */ #define TPD_TCPHDRLEN_MASK … #define TPD_TCPHDRLEN_SHIFT … #define TPD_HDRFLAG_MASK … #define TPD_HDRFLAG_SHIFT … #define TPD_MSS_MASK … #define TPD_MSS_SHIFT … /* tpd word 3 bits 16:31 if custom csum enabled */ #define TPD_PLOADOFFSET_MASK … #define TPD_PLOADOFFSET_SHIFT … #define TPD_CCSUMOFFSET_MASK … #define TPD_CCSUMOFFSET_SHIFT … struct tx_packet_desc { … }; /* DMA Order Settings */ enum atl1_dma_order { … }; enum atl1_dma_rcb { … }; enum atl1_dma_req_block { … }; #define ATL1_MAX_INTR … #define ATL1_MAX_TX_BUF_LEN … #define ATL1_DEFAULT_TPD … #define ATL1_MAX_TPD … #define ATL1_MIN_TPD … #define ATL1_DEFAULT_RFD … #define ATL1_MIN_RFD … #define ATL1_MAX_RFD … #define ATL1_REG_COUNT … #define ATL1_GET_DESC(R, i, type) … #define ATL1_RFD_DESC(R, i) … #define ATL1_TPD_DESC(R, i) … #define ATL1_RRD_DESC(R, i) … /* * atl1_ring_header represents a single, contiguous block of DMA space * mapped for the three descriptor rings (tpd, rfd, rrd) and the two * message blocks (cmb, smb) described below */ struct atl1_ring_header { … }; /* * atl1_buffer is wrapper around a pointer to a socket buffer * so a DMA handle can be stored along with the skb */ struct atl1_buffer { … }; /* transmit packet descriptor (tpd) ring */ struct atl1_tpd_ring { … }; /* receive free descriptor (rfd) ring */ struct atl1_rfd_ring { … }; /* receive return descriptor (rrd) ring */ struct atl1_rrd_ring { … }; /* coalescing message block (cmb) */ struct atl1_cmb { … }; /* statistics message block (smb) */ struct atl1_smb { … }; /* Statistics counters */ struct atl1_sft_stats { … }; /* hardware structure */ struct atl1_hw { … }; struct atl1_adapter { … }; #endif /* ATL1_H */
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