/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright(c) 2007 Atheros Corporation. All rights reserved. * * Derived from Intel e1000 driver * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. */ #ifndef _ATHL1E_HW_H_ #define _ATHL1E_HW_H_ #include <linux/types.h> #include <linux/mii.h> struct atl1e_adapter; struct atl1e_hw; /* function prototype */ s32 atl1e_reset_hw(struct atl1e_hw *hw); s32 atl1e_read_mac_addr(struct atl1e_hw *hw); s32 atl1e_init_hw(struct atl1e_hw *hw); s32 atl1e_phy_commit(struct atl1e_hw *hw); s32 atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex); u32 atl1e_auto_get_fc(struct atl1e_adapter *adapter, u16 duplex); u32 atl1e_hash_mc_addr(struct atl1e_hw *hw, u8 *mc_addr); void atl1e_hash_set(struct atl1e_hw *hw, u32 hash_value); s32 atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data); s32 atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data); s32 atl1e_validate_mdi_setting(struct atl1e_hw *hw); void atl1e_hw_set_mac_addr(struct atl1e_hw *hw); bool atl1e_read_eeprom(struct atl1e_hw *hw, u32 offset, u32 *p_value); bool atl1e_write_eeprom(struct atl1e_hw *hw, u32 offset, u32 value); s32 atl1e_phy_enter_power_saving(struct atl1e_hw *hw); s32 atl1e_phy_leave_power_saving(struct atl1e_hw *hw); s32 atl1e_phy_init(struct atl1e_hw *hw); int atl1e_check_eeprom_exist(struct atl1e_hw *hw); void atl1e_force_ps(struct atl1e_hw *hw); s32 atl1e_restart_autoneg(struct atl1e_hw *hw); /* register definition */ #define REG_PM_CTRLSTAT … #define REG_PCIE_CAP_LIST … #define REG_DEVICE_CAP … #define DEVICE_CAP_MAX_PAYLOAD_MASK … #define DEVICE_CAP_MAX_PAYLOAD_SHIFT … #define REG_DEVICE_CTRL … #define DEVICE_CTRL_MAX_PAYLOAD_MASK … #define DEVICE_CTRL_MAX_PAYLOAD_SHIFT … #define DEVICE_CTRL_MAX_RREQ_SZ_MASK … #define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT … #define REG_VPD_CAP … #define VPD_CAP_ID_MASK … #define VPD_CAP_ID_SHIFT … #define VPD_CAP_NEXT_PTR_MASK … #define VPD_CAP_NEXT_PTR_SHIFT … #define VPD_CAP_VPD_ADDR_MASK … #define VPD_CAP_VPD_ADDR_SHIFT … #define VPD_CAP_VPD_FLAG … #define REG_VPD_DATA … #define REG_SPI_FLASH_CTRL … #define SPI_FLASH_CTRL_STS_NON_RDY … #define SPI_FLASH_CTRL_STS_WEN … #define SPI_FLASH_CTRL_STS_WPEN … #define SPI_FLASH_CTRL_DEV_STS_MASK … #define SPI_FLASH_CTRL_DEV_STS_SHIFT … #define SPI_FLASH_CTRL_INS_MASK … #define SPI_FLASH_CTRL_INS_SHIFT … #define SPI_FLASH_CTRL_START … #define SPI_FLASH_CTRL_EN_VPD … #define SPI_FLASH_CTRL_LDSTART … #define SPI_FLASH_CTRL_CS_HI_MASK … #define SPI_FLASH_CTRL_CS_HI_SHIFT … #define SPI_FLASH_CTRL_CS_HOLD_MASK … #define SPI_FLASH_CTRL_CS_HOLD_SHIFT … #define SPI_FLASH_CTRL_CLK_LO_MASK … #define SPI_FLASH_CTRL_CLK_LO_SHIFT … #define SPI_FLASH_CTRL_CLK_HI_MASK … #define SPI_FLASH_CTRL_CLK_HI_SHIFT … #define SPI_FLASH_CTRL_CS_SETUP_MASK … #define SPI_FLASH_CTRL_CS_SETUP_SHIFT … #define SPI_FLASH_CTRL_EROM_PGSZ_MASK … #define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT … #define SPI_FLASH_CTRL_WAIT_READY … #define REG_SPI_ADDR … #define REG_SPI_DATA … #define REG_SPI_FLASH_CONFIG … #define SPI_FLASH_CONFIG_LD_ADDR_MASK … #define SPI_FLASH_CONFIG_LD_ADDR_SHIFT … #define SPI_FLASH_CONFIG_VPD_ADDR_MASK … #define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT … #define SPI_FLASH_CONFIG_LD_EXIST … #define REG_SPI_FLASH_OP_PROGRAM … #define REG_SPI_FLASH_OP_SC_ERASE … #define REG_SPI_FLASH_OP_CHIP_ERASE … #define REG_SPI_FLASH_OP_RDID … #define REG_SPI_FLASH_OP_WREN … #define REG_SPI_FLASH_OP_RDSR … #define REG_SPI_FLASH_OP_WRSR … #define REG_SPI_FLASH_OP_READ … #define REG_TWSI_CTRL … #define TWSI_CTRL_LD_OFFSET_MASK … #define TWSI_CTRL_LD_OFFSET_SHIFT … #define TWSI_CTRL_LD_SLV_ADDR_MASK … #define TWSI_CTRL_LD_SLV_ADDR_SHIFT … #define TWSI_CTRL_SW_LDSTART … #define TWSI_CTRL_HW_LDSTART … #define TWSI_CTRL_SMB_SLV_ADDR_MASK … #define TWSI_CTRL_SMB_SLV_ADDR_SHIFT … #define TWSI_CTRL_LD_EXIST … #define TWSI_CTRL_READ_FREQ_SEL_MASK … #define TWSI_CTRL_READ_FREQ_SEL_SHIFT … #define TWSI_CTRL_FREQ_SEL_100K … #define TWSI_CTRL_FREQ_SEL_200K … #define TWSI_CTRL_FREQ_SEL_300K … #define TWSI_CTRL_FREQ_SEL_400K … #define TWSI_CTRL_SMB_SLV_ADDR #define TWSI_CTRL_WRITE_FREQ_SEL_MASK … #define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT … #define REG_PCIE_DEV_MISC_CTRL … #define PCIE_DEV_MISC_CTRL_EXT_PIPE … #define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS … #define PCIE_DEV_MISC_CTRL_SPIROM_EXIST … #define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN … #define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN … #define REG_PCIE_PHYMISC … #define PCIE_PHYMISC_FORCE_RCV_DET … #define REG_LTSSM_TEST_MODE … #define LTSSM_TEST_MODE_DEF … /* Selene Master Control Register */ #define REG_MASTER_CTRL … #define MASTER_CTRL_SOFT_RST … #define MASTER_CTRL_MTIMER_EN … #define MASTER_CTRL_ITIMER_EN … #define MASTER_CTRL_MANUAL_INT … #define MASTER_CTRL_ITIMER2_EN … #define MASTER_CTRL_INT_RDCLR … #define MASTER_CTRL_LED_MODE … #define MASTER_CTRL_REV_NUM_SHIFT … #define MASTER_CTRL_REV_NUM_MASK … #define MASTER_CTRL_DEV_ID_SHIFT … #define MASTER_CTRL_DEV_ID_MASK … /* Timer Initial Value Register */ #define REG_MANUAL_TIMER_INIT … /* IRQ ModeratorTimer Initial Value Register */ #define REG_IRQ_MODU_TIMER_INIT … #define REG_IRQ_MODU_TIMER2_INIT … #define REG_GPHY_CTRL … #define GPHY_CTRL_EXT_RESET … #define GPHY_CTRL_PIPE_MOD … #define GPHY_CTRL_TEST_MODE_MASK … #define GPHY_CTRL_TEST_MODE_SHIFT … #define GPHY_CTRL_BERT_START … #define GPHY_CTRL_GATE_25M_EN … #define GPHY_CTRL_LPW_EXIT … #define GPHY_CTRL_PHY_IDDQ … #define GPHY_CTRL_PHY_IDDQ_DIS … #define GPHY_CTRL_PCLK_SEL_DIS … #define GPHY_CTRL_HIB_EN … #define GPHY_CTRL_HIB_PULSE … #define GPHY_CTRL_SEL_ANA_RST … #define GPHY_CTRL_PHY_PLL_ON … #define GPHY_CTRL_PWDOWN_HW … #define GPHY_CTRL_DEFAULT … #define GPHY_CTRL_PW_WOL_DIS … /* IRQ Anti-Lost Timer Initial Value Register */ #define REG_CMBDISDMA_TIMER … /* Block IDLE Status Register */ #define REG_IDLE_STATUS … #define IDLE_STATUS_RXMAC … #define IDLE_STATUS_TXMAC … #define IDLE_STATUS_RXQ … #define IDLE_STATUS_TXQ … #define IDLE_STATUS_DMAR … #define IDLE_STATUS_DMAW … #define IDLE_STATUS_SMB … #define IDLE_STATUS_CMB … /* MDIO Control Register */ #define REG_MDIO_CTRL … #define MDIO_DATA_MASK … #define MDIO_DATA_SHIFT … #define MDIO_REG_ADDR_MASK … #define MDIO_REG_ADDR_SHIFT … #define MDIO_RW … #define MDIO_SUP_PREAMBLE … #define MDIO_START … #define MDIO_CLK_SEL_SHIFT … #define MDIO_CLK_25_4 … #define MDIO_CLK_25_6 … #define MDIO_CLK_25_8 … #define MDIO_CLK_25_10 … #define MDIO_CLK_25_14 … #define MDIO_CLK_25_20 … #define MDIO_CLK_25_28 … #define MDIO_BUSY … #define MDIO_AP_EN … #define MDIO_WAIT_TIMES … /* MII PHY Status Register */ #define REG_PHY_STATUS … #define PHY_STATUS_100M … #define PHY_STATUS_EMI_CA … /* BIST Control and Status Register0 (for the Packet Memory) */ #define REG_BIST0_CTRL … #define BIST0_NOW … /* BIST process and reset to zero when BIST is done */ #define BIST0_SRAM_FAIL … /* decoder failure or more than 1 cell stuck-to-x failure */ #define BIST0_FUSE_FLAG … /* BIST Control and Status Register1(for the retry buffer of PCI Express) */ #define REG_BIST1_CTRL … #define BIST1_NOW … /* BIST process and reset to zero when BIST is done */ #define BIST1_SRAM_FAIL … /* decoder failure or more than 1 cell stuck-to-x failure.*/ #define BIST1_FUSE_FLAG … /* SerDes Lock Detect Control and Status Register */ #define REG_SERDES_LOCK … #define SERDES_LOCK_DETECT … #define SERDES_LOCK_DETECT_EN … /* MAC Control Register */ #define REG_MAC_CTRL … #define MAC_CTRL_TX_EN … #define MAC_CTRL_RX_EN … #define MAC_CTRL_TX_FLOW … #define MAC_CTRL_RX_FLOW … #define MAC_CTRL_LOOPBACK … #define MAC_CTRL_DUPLX … #define MAC_CTRL_ADD_CRC … #define MAC_CTRL_PAD … #define MAC_CTRL_LENCHK … #define MAC_CTRL_HUGE_EN … #define MAC_CTRL_PRMLEN_SHIFT … #define MAC_CTRL_PRMLEN_MASK … #define MAC_CTRL_RMV_VLAN … #define MAC_CTRL_PROMIS_EN … #define MAC_CTRL_TX_PAUSE … #define MAC_CTRL_SCNT … #define MAC_CTRL_SRST_TX … #define MAC_CTRL_TX_SIMURST … #define MAC_CTRL_SPEED_SHIFT … #define MAC_CTRL_SPEED_MASK … #define MAC_CTRL_SPEED_1000 … #define MAC_CTRL_SPEED_10_100 … #define MAC_CTRL_DBG_TX_BKPRESURE … #define MAC_CTRL_TX_HUGE … #define MAC_CTRL_RX_CHKSUM_EN … #define MAC_CTRL_MC_ALL_EN … #define MAC_CTRL_BC_EN … #define MAC_CTRL_DBG … /* MAC IPG/IFG Control Register */ #define REG_MAC_IPG_IFG … #define MAC_IPG_IFG_IPGT_SHIFT … #define MAC_IPG_IFG_IPGT_MASK … #define MAC_IPG_IFG_MIFG_SHIFT … #define MAC_IPG_IFG_MIFG_MASK … #define MAC_IPG_IFG_IPGR1_SHIFT … #define MAC_IPG_IFG_IPGR1_MASK … #define MAC_IPG_IFG_IPGR2_SHIFT … #define MAC_IPG_IFG_IPGR2_MASK … /* MAC STATION ADDRESS */ #define REG_MAC_STA_ADDR … /* Hash table for multicast address */ #define REG_RX_HASH_TABLE … /* MAC Half-Duplex Control Register */ #define REG_MAC_HALF_DUPLX_CTRL … #define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT … #define MAC_HALF_DUPLX_CTRL_LCOL_MASK … #define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT … #define MAC_HALF_DUPLX_CTRL_RETRY_MASK … #define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN … #define MAC_HALF_DUPLX_CTRL_NO_BACK_C … #define MAC_HALF_DUPLX_CTRL_NO_BACK_P … #define MAC_HALF_DUPLX_CTRL_ABEBE … #define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT … #define MAC_HALF_DUPLX_CTRL_ABEBT_MASK … #define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT … #define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK … /* Maximum Frame Length Control Register */ #define REG_MTU … /* Wake-On-Lan control register */ #define REG_WOL_CTRL … #define WOL_PATTERN_EN … #define WOL_PATTERN_PME_EN … #define WOL_MAGIC_EN … #define WOL_MAGIC_PME_EN … #define WOL_LINK_CHG_EN … #define WOL_LINK_CHG_PME_EN … #define WOL_PATTERN_ST … #define WOL_MAGIC_ST … #define WOL_LINKCHG_ST … #define WOL_CLK_SWITCH_EN … #define WOL_PT0_EN … #define WOL_PT1_EN … #define WOL_PT2_EN … #define WOL_PT3_EN … #define WOL_PT4_EN … #define WOL_PT5_EN … #define WOL_PT6_EN … /* WOL Length ( 2 DWORD ) */ #define REG_WOL_PATTERN_LEN … #define WOL_PT_LEN_MASK … #define WOL_PT0_LEN_SHIFT … #define WOL_PT1_LEN_SHIFT … #define WOL_PT2_LEN_SHIFT … #define WOL_PT3_LEN_SHIFT … #define WOL_PT4_LEN_SHIFT … #define WOL_PT5_LEN_SHIFT … #define WOL_PT6_LEN_SHIFT … /* Internal SRAM Partition Register */ #define REG_SRAM_TRD_ADDR … #define REG_SRAM_TRD_LEN … #define REG_SRAM_RXF_ADDR … #define REG_SRAM_RXF_LEN … #define REG_SRAM_TXF_ADDR … #define REG_SRAM_TXF_LEN … #define REG_SRAM_TCPH_ADDR … #define REG_SRAM_PKTH_ADDR … /* Load Ptr Register */ #define REG_LOAD_PTR … /* * addresses of all descriptors, as well as the following descriptor * control register, which triggers each function block to load the head * pointer to prepare for the operation. This bit is then self-cleared * after one cycle. */ /* Descriptor Control register */ #define REG_RXF3_BASE_ADDR_HI … #define REG_DESC_BASE_ADDR_HI … #define REG_RXF0_BASE_ADDR_HI … #define REG_HOST_RXF0_PAGE0_LO … #define REG_HOST_RXF0_PAGE1_LO … #define REG_TPD_BASE_ADDR_LO … #define REG_RXF1_BASE_ADDR_HI … #define REG_RXF2_BASE_ADDR_HI … #define REG_HOST_RXFPAGE_SIZE … #define REG_TPD_RING_SIZE … /* RSS about */ #define REG_RSS_KEY0 … #define REG_RSS_KEY1 … #define REG_RSS_KEY2 … #define REG_RSS_KEY3 … #define REG_RSS_KEY4 … #define REG_RSS_KEY5 … #define REG_RSS_KEY6 … #define REG_RSS_KEY7 … #define REG_RSS_KEY8 … #define REG_RSS_KEY9 … #define REG_IDT_TABLE4 … #define REG_IDT_TABLE5 … #define REG_IDT_TABLE6 … #define REG_IDT_TABLE7 … #define REG_IDT_TABLE0 … #define REG_IDT_TABLE1 … #define REG_IDT_TABLE2 … #define REG_IDT_TABLE3 … #define REG_IDT_TABLE … #define REG_RSS_HASH_VALUE … #define REG_RSS_HASH_FLAG … #define REG_BASE_CPU_NUMBER … /* TXQ Control Register */ #define REG_TXQ_CTRL … #define TXQ_CTRL_NUM_TPD_BURST_MASK … #define TXQ_CTRL_NUM_TPD_BURST_SHIFT … #define TXQ_CTRL_EN … #define TXQ_CTRL_ENH_MODE … #define TXQ_CTRL_TXF_BURST_NUM_SHIFT … #define TXQ_CTRL_TXF_BURST_NUM_MASK … /* Jumbo packet Threshold for task offload */ #define REG_TX_EARLY_TH … /* JUMBO_TASK_OFFLOAD_THRESHOLD will not be task offloaded. */ #define TX_TX_EARLY_TH_MASK … #define TX_TX_EARLY_TH_SHIFT … /* RXQ Control Register */ #define REG_RXQ_CTRL … #define RXQ_CTRL_PBA_ALIGN_32 … #define RXQ_CTRL_PBA_ALIGN_64 … #define RXQ_CTRL_PBA_ALIGN_128 … #define RXQ_CTRL_PBA_ALIGN_256 … #define RXQ_CTRL_Q1_EN … #define RXQ_CTRL_Q2_EN … #define RXQ_CTRL_Q3_EN … #define RXQ_CTRL_IPV6_XSUM_VERIFY_EN … #define RXQ_CTRL_HASH_TLEN_SHIFT … #define RXQ_CTRL_HASH_TLEN_MASK … #define RXQ_CTRL_HASH_TYPE_IPV4 … #define RXQ_CTRL_HASH_TYPE_IPV4_TCP … #define RXQ_CTRL_HASH_TYPE_IPV6 … #define RXQ_CTRL_HASH_TYPE_IPV6_TCP … #define RXQ_CTRL_RSS_MODE_DISABLE … #define RXQ_CTRL_RSS_MODE_SQSINT … #define RXQ_CTRL_RSS_MODE_MQUESINT … #define RXQ_CTRL_RSS_MODE_MQUEMINT … #define RXQ_CTRL_NIP_QUEUE_SEL_TBL … #define RXQ_CTRL_HASH_ENABLE … #define RXQ_CTRL_CUT_THRU_EN … #define RXQ_CTRL_EN … /* Rx jumbo packet threshold and rrd retirement timer */ #define REG_RXQ_JMBOSZ_RRDTIM … /* * Jumbo packet threshold for non-VLAN packet, in QWORD (64-bit) unit. * When the packet length greater than or equal to this value, RXQ * shall start cut-through forwarding of the received packet. */ #define RXQ_JMBOSZ_TH_MASK … #define RXQ_JMBOSZ_TH_SHIFT … #define RXQ_JMBO_LKAH_MASK … #define RXQ_JMBO_LKAH_SHIFT … /* RXF flow control register */ #define REG_RXQ_RXF_PAUSE_THRESH … #define RXQ_RXF_PAUSE_TH_HI_SHIFT … #define RXQ_RXF_PAUSE_TH_HI_MASK … #define RXQ_RXF_PAUSE_TH_LO_SHIFT … #define RXQ_RXF_PAUSE_TH_LO_MASK … /* DMA Engine Control Register */ #define REG_DMA_CTRL … #define DMA_CTRL_DMAR_IN_ORDER … #define DMA_CTRL_DMAR_ENH_ORDER … #define DMA_CTRL_DMAR_OUT_ORDER … #define DMA_CTRL_RCB_VALUE … #define DMA_CTRL_DMAR_BURST_LEN_SHIFT … #define DMA_CTRL_DMAR_BURST_LEN_MASK … #define DMA_CTRL_DMAW_BURST_LEN_SHIFT … #define DMA_CTRL_DMAW_BURST_LEN_MASK … #define DMA_CTRL_DMAR_REQ_PRI … #define DMA_CTRL_DMAR_DLY_CNT_MASK … #define DMA_CTRL_DMAR_DLY_CNT_SHIFT … #define DMA_CTRL_DMAW_DLY_CNT_MASK … #define DMA_CTRL_DMAW_DLY_CNT_SHIFT … #define DMA_CTRL_TXCMB_EN … #define DMA_CTRL_RXCMB_EN … /* CMB/SMB Control Register */ #define REG_SMB_STAT_TIMER … #define REG_TRIG_RRD_THRESH … #define REG_TRIG_TPD_THRESH … #define REG_TRIG_TXTIMER … #define REG_TRIG_RXTIMER … /* HOST RXF Page 1,2,3 address */ #define REG_HOST_RXF1_PAGE0_LO … #define REG_HOST_RXF1_PAGE1_LO … #define REG_HOST_RXF2_PAGE0_LO … #define REG_HOST_RXF2_PAGE1_LO … #define REG_HOST_RXF3_PAGE0_LO … #define REG_HOST_RXF3_PAGE1_LO … /* Mail box */ #define REG_MB_RXF1_RADDR … #define REG_MB_RXF2_RADDR … #define REG_MB_RXF3_RADDR … #define REG_MB_TPD_PROD_IDX … /* RXF-Page 0-3 PageNo & Valid bit */ #define REG_HOST_RXF0_PAGE0_VLD … #define HOST_RXF_VALID … #define HOST_RXF_PAGENO_SHIFT … #define HOST_RXF_PAGENO_MASK … #define REG_HOST_RXF0_PAGE1_VLD … #define REG_HOST_RXF1_PAGE0_VLD … #define REG_HOST_RXF1_PAGE1_VLD … #define REG_HOST_RXF2_PAGE0_VLD … #define REG_HOST_RXF2_PAGE1_VLD … #define REG_HOST_RXF3_PAGE0_VLD … #define REG_HOST_RXF3_PAGE1_VLD … /* Interrupt Status Register */ #define REG_ISR … #define ISR_SMB … #define ISR_TIMER … /* * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set * in Table 51 Selene Master Control Register (Offset 0x1400). */ #define ISR_MANUAL … #define ISR_HW_RXF_OV … #define ISR_HOST_RXF0_OV … #define ISR_HOST_RXF1_OV … #define ISR_HOST_RXF2_OV … #define ISR_HOST_RXF3_OV … #define ISR_TXF_UN … #define ISR_RX0_PAGE_FULL … #define ISR_DMAR_TO_RST … #define ISR_DMAW_TO_RST … #define ISR_GPHY … #define ISR_TX_CREDIT … #define ISR_GPHY_LPW … #define ISR_RX_PKT … #define ISR_TX_PKT … #define ISR_TX_DMA … #define ISR_RX_PKT_1 … #define ISR_RX_PKT_2 … #define ISR_RX_PKT_3 … #define ISR_MAC_RX … #define ISR_MAC_TX … #define ISR_UR_DETECTED … #define ISR_FERR_DETECTED … #define ISR_NFERR_DETECTED … #define ISR_CERR_DETECTED … #define ISR_PHY_LINKDOWN … #define ISR_DIS_INT … /* Interrupt Mask Register */ #define REG_IMR … #define IMR_NORMAL_MASK … #define ISR_TX_EVENT … #define ISR_RX_EVENT … #define REG_MAC_RX_STATUS_BIN … #define REG_MAC_RX_STATUS_END … #define REG_MAC_TX_STATUS_BIN … #define REG_MAC_TX_STATUS_END … /* Hardware Offset Register */ #define REG_HOST_RXF0_PAGEOFF … #define REG_TPD_CONS_IDX … #define REG_HOST_RXF1_PAGEOFF … #define REG_HOST_RXF2_PAGEOFF … #define REG_HOST_RXF3_PAGEOFF … /* RXF-Page 0-3 Offset DMA Address */ #define REG_HOST_RXF0_MB0_LO … #define REG_HOST_RXF0_MB1_LO … #define REG_HOST_RXF1_MB0_LO … #define REG_HOST_RXF1_MB1_LO … #define REG_HOST_RXF2_MB0_LO … #define REG_HOST_RXF2_MB1_LO … #define REG_HOST_RXF3_MB0_LO … #define REG_HOST_RXF3_MB1_LO … /* Tpd CMB DMA Address */ #define REG_HOST_TX_CMB_LO … #define REG_HOST_SMB_ADDR_LO … /* DEBUG ADDR */ #define REG_DEBUG_DATA0 … #define REG_DEBUG_DATA1 … /***************************** MII definition ***************************************/ /* PHY Common Register */ #define MII_AT001_PSCR … #define MII_AT001_PSSR … #define MII_INT_CTRL … #define MII_INT_STATUS … #define MII_SMARTSPEED … #define MII_LBRERROR … #define MII_RESV2 … #define MII_DBG_ADDR … #define MII_DBG_DATA … /* Autoneg Advertisement Register */ #define MII_AR_DEFAULT_CAP_MASK … /* 1000BASE-T Control Register */ #define MII_AT001_CR_1000T_SPEED_MASK … #define MII_AT001_CR_1000T_DEFAULT_CAP_MASK … /* AT001 PHY Specific Control Register */ #define MII_AT001_PSCR_JABBER_DISABLE … #define MII_AT001_PSCR_POLARITY_REVERSAL … #define MII_AT001_PSCR_SQE_TEST … #define MII_AT001_PSCR_MAC_POWERDOWN … #define MII_AT001_PSCR_CLK125_DISABLE … #define MII_AT001_PSCR_MDI_MANUAL_MODE … /* Manual MDI configuration */ #define MII_AT001_PSCR_MDIX_MANUAL_MODE … #define MII_AT001_PSCR_AUTO_X_1000T … #define MII_AT001_PSCR_AUTO_X_MODE … #define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE … /* 1=Enable Extended 10BASE-T distance * (Lower 10BASE-T RX Threshold) * 0=Normal 10BASE-T RX Threshold */ #define MII_AT001_PSCR_MII_5BIT_ENABLE … /* 1=5-Bit interface in 100BASE-TX * 0=MII interface in 100BASE-TX */ #define MII_AT001_PSCR_SCRAMBLER_DISABLE … #define MII_AT001_PSCR_FORCE_LINK_GOOD … #define MII_AT001_PSCR_ASSERT_CRS_ON_TX … #define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT … #define MII_AT001_PSCR_AUTO_X_MODE_SHIFT … #define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT … /* AT001 PHY Specific Status Register */ #define MII_AT001_PSSR_SPD_DPLX_RESOLVED … #define MII_AT001_PSSR_DPLX … #define MII_AT001_PSSR_SPEED … #define MII_AT001_PSSR_10MBS … #define MII_AT001_PSSR_100MBS … #define MII_AT001_PSSR_1000MBS … #endif /*_ATHL1E_HW_H_*/
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