/* * Copyright (c) 2013 Johannes Berg <[email protected]> * * This file is free software: you may copy, redistribute and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation, either version 2 of the License, or (at your * option) any later version. * * This file is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. * * This file incorporates work covered by the following copyright and * permission notice: * * Copyright (c) 2012 Qualcomm Atheros, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef ALX_REG_H #define ALX_REG_H #define ALX_DEV_ID_AR8161 … #define ALX_DEV_ID_E2200 … #define ALX_DEV_ID_E2400 … #define ALX_DEV_ID_E2500 … #define ALX_DEV_ID_AR8162 … #define ALX_DEV_ID_AR8171 … #define ALX_DEV_ID_AR8172 … /* rev definition, * bit(0): with xD support * bit(1): with Card Reader function * bit(7:2): real revision */ #define ALX_PCI_REVID_SHIFT … #define ALX_REV_A0 … #define ALX_REV_A1 … #define ALX_REV_B0 … #define ALX_REV_C0 … #define ALX_DEV_CTRL … #define ALX_DEV_CTRL_MAXRRS_MIN … #define ALX_MSIX_MASK … #define ALX_UE_SVRT … #define ALX_UE_SVRT_FCPROTERR … #define ALX_UE_SVRT_DLPROTERR … /* eeprom & flash load register */ #define ALX_EFLD … #define ALX_EFLD_F_EXIST … #define ALX_EFLD_E_EXIST … #define ALX_EFLD_STAT … #define ALX_EFLD_START … /* eFuse load register */ #define ALX_SLD … #define ALX_SLD_STAT … #define ALX_SLD_START … #define ALX_SLD_MAX_TO … #define ALX_PDLL_TRNS1 … #define ALX_PDLL_TRNS1_D3PLLOFF_EN … #define ALX_PMCTRL … #define ALX_PMCTRL_HOTRST_WTEN … /* bit30: L0s/L1 controlled by MAC based on throughput(setting in 15A0) */ #define ALX_PMCTRL_ASPM_FCEN … #define ALX_PMCTRL_SADLY_EN … #define ALX_PMCTRL_LCKDET_TIMER_MASK … #define ALX_PMCTRL_LCKDET_TIMER_SHIFT … #define ALX_PMCTRL_LCKDET_TIMER_DEF … /* bit[23:20] if pm_request_l1 time > @, then enter L0s not L1 */ #define ALX_PMCTRL_L1REQ_TO_MASK … #define ALX_PMCTRL_L1REQ_TO_SHIFT … #define ALX_PMCTRL_L1REG_TO_DEF … #define ALX_PMCTRL_TXL1_AFTER_L0S … #define ALX_PMCTRL_L1_TIMER_MASK … #define ALX_PMCTRL_L1_TIMER_SHIFT … #define ALX_PMCTRL_L1_TIMER_16US … #define ALX_PMCTRL_RCVR_WT_1US … /* bit13: enable pcie clk switch in L1 state */ #define ALX_PMCTRL_L1_CLKSW_EN … #define ALX_PMCTRL_L0S_EN … #define ALX_PMCTRL_RXL1_AFTER_L0S … #define ALX_PMCTRL_L1_BUFSRX_EN … /* bit6: power down serdes RX */ #define ALX_PMCTRL_L1_SRDSRX_PWD … #define ALX_PMCTRL_L1_SRDSPLL_EN … #define ALX_PMCTRL_L1_SRDS_EN … #define ALX_PMCTRL_L1_EN … /*******************************************************/ /* following registers are mapped only to memory space */ /*******************************************************/ #define ALX_MASTER … /* bit12: 1:alwys select pclk from serdes, not sw to 25M */ #define ALX_MASTER_PCLKSEL_SRDS … /* bit11: irq moduration for rx */ #define ALX_MASTER_IRQMOD2_EN … /* bit10: irq moduration for tx/rx */ #define ALX_MASTER_IRQMOD1_EN … #define ALX_MASTER_SYSALVTIMER_EN … #define ALX_MASTER_OOB_DIS … /* bit5: wakeup without pcie clk */ #define ALX_MASTER_WAKEN_25M … /* bit0: MAC & DMA reset */ #define ALX_MASTER_DMA_MAC_RST … #define ALX_DMA_MAC_RST_TO … #define ALX_IRQ_MODU_TIMER … #define ALX_IRQ_MODU_TIMER1_MASK … #define ALX_IRQ_MODU_TIMER1_SHIFT … #define ALX_PHY_CTRL … #define ALX_PHY_CTRL_100AB_EN … /* bit14: affect MAC & PHY, go to low power sts */ #define ALX_PHY_CTRL_POWER_DOWN … /* bit13: 1:pll always ON, 0:can switch in lpw */ #define ALX_PHY_CTRL_PLL_ON … #define ALX_PHY_CTRL_RST_ANALOG … #define ALX_PHY_CTRL_HIB_PULSE … #define ALX_PHY_CTRL_HIB_EN … #define ALX_PHY_CTRL_IDDQ … #define ALX_PHY_CTRL_GATE_25M … #define ALX_PHY_CTRL_LED_MODE … /* bit0: out of dsp RST state */ #define ALX_PHY_CTRL_DSPRST_OUT … #define ALX_PHY_CTRL_DSPRST_TO … #define ALX_PHY_CTRL_CLS … #define ALX_MAC_STS … #define ALX_MAC_STS_TXQ_BUSY … #define ALX_MAC_STS_RXQ_BUSY … #define ALX_MAC_STS_TXMAC_BUSY … #define ALX_MAC_STS_RXMAC_BUSY … #define ALX_MAC_STS_IDLE … #define ALX_MDIO … #define ALX_MDIO_MODE_EXT … #define ALX_MDIO_BUSY … #define ALX_MDIO_CLK_SEL_MASK … #define ALX_MDIO_CLK_SEL_SHIFT … #define ALX_MDIO_CLK_SEL_25MD4 … #define ALX_MDIO_CLK_SEL_25MD128 … #define ALX_MDIO_START … #define ALX_MDIO_SPRES_PRMBL … /* bit21: 1:read,0:write */ #define ALX_MDIO_OP_READ … #define ALX_MDIO_REG_MASK … #define ALX_MDIO_REG_SHIFT … #define ALX_MDIO_DATA_MASK … #define ALX_MDIO_DATA_SHIFT … #define ALX_MDIO_MAX_AC_TO … #define ALX_MDIO_EXTN … #define ALX_MDIO_EXTN_DEVAD_MASK … #define ALX_MDIO_EXTN_DEVAD_SHIFT … #define ALX_MDIO_EXTN_REG_MASK … #define ALX_MDIO_EXTN_REG_SHIFT … #define ALX_SERDES … #define ALX_SERDES_PHYCLK_SLWDWN … #define ALX_SERDES_MACCLK_SLWDWN … #define ALX_LPI_CTRL … #define ALX_LPI_CTRL_EN … /* for B0+, bit[13..] for C0+ */ #define ALX_HRTBT_EXT_CTRL … #define L1F_HRTBT_EXT_CTRL_PERIOD_HIGH_MASK … #define L1F_HRTBT_EXT_CTRL_PERIOD_HIGH_SHIFT … #define L1F_HRTBT_EXT_CTRL_SWOI_STARTUP_PKT_EN … #define L1F_HRTBT_EXT_CTRL_IOAC_2_FRAGMENTED … #define L1F_HRTBT_EXT_CTRL_IOAC_1_FRAGMENTED … #define L1F_HRTBT_EXT_CTRL_IOAC_1_KEEPALIVE_EN … #define L1F_HRTBT_EXT_CTRL_IOAC_1_HAS_VLAN … #define L1F_HRTBT_EXT_CTRL_IOAC_1_IS_8023 … #define L1F_HRTBT_EXT_CTRL_IOAC_1_IS_IPV6 … #define L1F_HRTBT_EXT_CTRL_IOAC_2_KEEPALIVE_EN … #define L1F_HRTBT_EXT_CTRL_IOAC_2_HAS_VLAN … #define L1F_HRTBT_EXT_CTRL_IOAC_2_IS_8023 … #define L1F_HRTBT_EXT_CTRL_IOAC_2_IS_IPV6 … #define ALX_HRTBT_EXT_CTRL_NS_EN … #define ALX_HRTBT_EXT_CTRL_FRAG_LEN_MASK … #define ALX_HRTBT_EXT_CTRL_FRAG_LEN_SHIFT … #define ALX_HRTBT_EXT_CTRL_IS_8023 … #define ALX_HRTBT_EXT_CTRL_IS_IPV6 … #define ALX_HRTBT_EXT_CTRL_WAKEUP_EN … #define ALX_HRTBT_EXT_CTRL_ARP_EN … #define ALX_HRTBT_REM_IPV4_ADDR … #define ALX_HRTBT_HOST_IPV4_ADDR … #define ALX_HRTBT_REM_IPV6_ADDR3 … #define ALX_HRTBT_REM_IPV6_ADDR2 … #define ALX_HRTBT_REM_IPV6_ADDR1 … #define ALX_HRTBT_REM_IPV6_ADDR0 … /* 1B8C ~ 1B94 for C0+ */ #define ALX_SWOI_ACER_CTRL … #define ALX_SWOI_ORIG_ACK_NAK_EN … #define ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_MASK … #define ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_SHIFT … #define ALX_SWOI_ORIG_ACK_ADDR_MASK … #define ALX_SWOI_ORIG_ACK_ADDR_SHIFT … #define ALX_SWOI_IOAC_CTRL_2 … #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_MASK … #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_SHIFT … #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_MASK … #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_SHIFT … #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_MASK … #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_SHIFT … #define ALX_SWOI_IOAC_CTRL_3 … #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_MASK … #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_SHIFT … #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_MASK … #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_SHIFT … #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_MASK … #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_SHIFT … /* for B0 */ #define ALX_IDLE_DECISN_TIMER … /* 1ms */ #define ALX_IDLE_DECISN_TIMER_DEF … #define ALX_MAC_CTRL … #define ALX_MAC_CTRL_FAST_PAUSE … #define ALX_MAC_CTRL_WOLSPED_SWEN … /* bit29: 1:legacy(hi5b), 0:marvl(lo5b)*/ #define ALX_MAC_CTRL_MHASH_ALG_HI5B … #define ALX_MAC_CTRL_BRD_EN … #define ALX_MAC_CTRL_MULTIALL_EN … #define ALX_MAC_CTRL_SPEED_MASK … #define ALX_MAC_CTRL_SPEED_SHIFT … #define ALX_MAC_CTRL_SPEED_10_100 … #define ALX_MAC_CTRL_SPEED_1000 … #define ALX_MAC_CTRL_PROMISC_EN … #define ALX_MAC_CTRL_VLANSTRIP … #define ALX_MAC_CTRL_PRMBLEN_MASK … #define ALX_MAC_CTRL_PRMBLEN_SHIFT … #define ALX_MAC_CTRL_PCRCE … #define ALX_MAC_CTRL_CRCE … #define ALX_MAC_CTRL_FULLD … #define ALX_MAC_CTRL_RXFC_EN … #define ALX_MAC_CTRL_TXFC_EN … #define ALX_MAC_CTRL_RX_EN … #define ALX_MAC_CTRL_TX_EN … #define ALX_STAD0 … #define ALX_STAD1 … #define ALX_HASH_TBL0 … #define ALX_HASH_TBL1 … #define ALX_MTU … #define ALX_MTU_JUMBO_TH … #define ALX_MTU_STD_ALGN … #define ALX_SRAM5 … #define ALX_SRAM_RXF_LEN_MASK … #define ALX_SRAM_RXF_LEN_SHIFT … #define ALX_SRAM_RXF_LEN_8K … #define ALX_SRAM9 … #define ALX_SRAM_LOAD_PTR … #define ALX_RX_BASE_ADDR_HI … #define ALX_TX_BASE_ADDR_HI … #define ALX_RFD_ADDR_LO … #define ALX_RFD_RING_SZ … #define ALX_RFD_BUF_SZ … #define ALX_RRD_ADDR_LO … #define ALX_RRD_RING_SZ … /* pri3: highest, pri0: lowest */ #define ALX_TPD_PRI3_ADDR_LO … #define ALX_TPD_PRI2_ADDR_LO … #define ALX_TPD_PRI1_ADDR_LO … #define ALX_TPD_PRI0_ADDR_LO … /* producer index is 16bit */ #define ALX_TPD_PRI3_PIDX … #define ALX_TPD_PRI2_PIDX … #define ALX_TPD_PRI1_PIDX … #define ALX_TPD_PRI0_PIDX … /* consumer index is 16bit */ #define ALX_TPD_PRI3_CIDX … #define ALX_TPD_PRI2_CIDX … #define ALX_TPD_PRI1_CIDX … #define ALX_TPD_PRI0_CIDX … #define ALX_TPD_RING_SZ … #define ALX_TXQ0 … #define ALX_TXQ0_TXF_BURST_PREF_MASK … #define ALX_TXQ0_TXF_BURST_PREF_SHIFT … #define ALX_TXQ_TXF_BURST_PREF_DEF … #define ALX_TXQ0_LSO_8023_EN … #define ALX_TXQ0_MODE_ENHANCE … #define ALX_TXQ0_EN … #define ALX_TXQ0_SUPT_IPOPT … #define ALX_TXQ0_TPD_BURSTPREF_MASK … #define ALX_TXQ0_TPD_BURSTPREF_SHIFT … #define ALX_TXQ_TPD_BURSTPREF_DEF … #define ALX_TXQ1 … /* bit11: drop large packet, len > (rfd buf) */ #define ALX_TXQ1_ERRLGPKT_DROP_EN … #define ALX_TXQ1_JUMBO_TSO_TH … #define ALX_RXQ0 … #define ALX_RXQ0_EN … #define ALX_RXQ0_RSS_HASH_EN … #define ALX_RXQ0_RSS_MODE_MASK … #define ALX_RXQ0_RSS_MODE_SHIFT … #define ALX_RXQ0_RSS_MODE_DIS … #define ALX_RXQ0_RSS_MODE_MQMI … #define ALX_RXQ0_NUM_RFD_PREF_MASK … #define ALX_RXQ0_NUM_RFD_PREF_SHIFT … #define ALX_RXQ0_NUM_RFD_PREF_DEF … #define ALX_RXQ0_IDT_TBL_SIZE_MASK … #define ALX_RXQ0_IDT_TBL_SIZE_SHIFT … #define ALX_RXQ0_IDT_TBL_SIZE_DEF … #define ALX_RXQ0_IDT_TBL_SIZE_NORMAL … #define ALX_RXQ0_IPV6_PARSE_EN … #define ALX_RXQ0_RSS_HSTYP_MASK … #define ALX_RXQ0_RSS_HSTYP_SHIFT … #define ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN … #define ALX_RXQ0_RSS_HSTYP_IPV6_EN … #define ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN … #define ALX_RXQ0_RSS_HSTYP_IPV4_EN … #define ALX_RXQ0_RSS_HSTYP_ALL … #define ALX_RXQ0_ASPM_THRESH_MASK … #define ALX_RXQ0_ASPM_THRESH_SHIFT … #define ALX_RXQ0_ASPM_THRESH_100M … #define ALX_RXQ2 … #define ALX_RXQ2_RXF_XOFF_THRESH_MASK … #define ALX_RXQ2_RXF_XOFF_THRESH_SHIFT … #define ALX_RXQ2_RXF_XON_THRESH_MASK … #define ALX_RXQ2_RXF_XON_THRESH_SHIFT … /* Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) + * rx-packet(1522) + delay-of-link(64) * = 3212. */ #define ALX_RXQ2_RXF_FLOW_CTRL_RSVD … #define ALX_DMA … #define ALX_DMA_RCHNL_SEL_MASK … #define ALX_DMA_RCHNL_SEL_SHIFT … #define ALX_DMA_WDLY_CNT_MASK … #define ALX_DMA_WDLY_CNT_SHIFT … #define ALX_DMA_WDLY_CNT_DEF … #define ALX_DMA_RDLY_CNT_MASK … #define ALX_DMA_RDLY_CNT_SHIFT … #define ALX_DMA_RDLY_CNT_DEF … /* bit10: 0:tpd with pri, 1: data */ #define ALX_DMA_RREQ_PRI_DATA … #define ALX_DMA_RREQ_BLEN_MASK … #define ALX_DMA_RREQ_BLEN_SHIFT … #define ALX_DMA_RORDER_MODE_MASK … #define ALX_DMA_RORDER_MODE_SHIFT … #define ALX_DMA_RORDER_MODE_OUT … #define ALX_WOL0 … #define ALX_WOL0_PME_LINK … #define ALX_WOL0_LINK_EN … #define ALX_WOL0_PME_MAGIC_EN … #define ALX_WOL0_MAGIC_EN … #define ALX_RFD_PIDX … #define ALX_RFD_CIDX … /* MIB */ #define ALX_MIB_BASE … #define ALX_MIB_RX_OK … #define ALX_MIB_RX_BCAST … #define ALX_MIB_RX_MCAST … #define ALX_MIB_RX_PAUSE … #define ALX_MIB_RX_CTRL … #define ALX_MIB_RX_FCS_ERR … #define ALX_MIB_RX_LEN_ERR … #define ALX_MIB_RX_BYTE_CNT … #define ALX_MIB_RX_RUNT … #define ALX_MIB_RX_FRAG … #define ALX_MIB_RX_SZ_64B … #define ALX_MIB_RX_SZ_127B … #define ALX_MIB_RX_SZ_255B … #define ALX_MIB_RX_SZ_511B … #define ALX_MIB_RX_SZ_1023B … #define ALX_MIB_RX_SZ_1518B … #define ALX_MIB_RX_SZ_MAX … #define ALX_MIB_RX_OV_SZ … #define ALX_MIB_RX_OV_RXF … #define ALX_MIB_RX_OV_RRD … #define ALX_MIB_RX_ALIGN_ERR … #define ALX_MIB_RX_BCCNT … #define ALX_MIB_RX_MCCNT … #define ALX_MIB_RX_ERRADDR … #define ALX_MIB_TX_OK … #define ALX_MIB_TX_BCAST … #define ALX_MIB_TX_MCAST … #define ALX_MIB_TX_PAUSE … #define ALX_MIB_TX_EXC_DEFER … #define ALX_MIB_TX_CTRL … #define ALX_MIB_TX_DEFER … #define ALX_MIB_TX_BYTE_CNT … #define ALX_MIB_TX_SZ_64B … #define ALX_MIB_TX_SZ_127B … #define ALX_MIB_TX_SZ_255B … #define ALX_MIB_TX_SZ_511B … #define ALX_MIB_TX_SZ_1023B … #define ALX_MIB_TX_SZ_1518B … #define ALX_MIB_TX_SZ_MAX … #define ALX_MIB_TX_SINGLE_COL … #define ALX_MIB_TX_MULTI_COL … #define ALX_MIB_TX_LATE_COL … #define ALX_MIB_TX_ABORT_COL … #define ALX_MIB_TX_UNDERRUN … #define ALX_MIB_TX_TRD_EOP … #define ALX_MIB_TX_LEN_ERR … #define ALX_MIB_TX_TRUNC … #define ALX_MIB_TX_BCCNT … #define ALX_MIB_TX_MCCNT … #define ALX_MIB_UPDATE … #define ALX_ISR … #define ALX_ISR_DIS … #define ALX_ISR_RX_Q7 … #define ALX_ISR_RX_Q6 … #define ALX_ISR_RX_Q5 … #define ALX_ISR_RX_Q4 … #define ALX_ISR_PCIE_LNKDOWN … #define ALX_ISR_RX_Q3 … #define ALX_ISR_RX_Q2 … #define ALX_ISR_RX_Q1 … #define ALX_ISR_RX_Q0 … #define ALX_ISR_TX_Q0 … #define ALX_ISR_PHY … #define ALX_ISR_DMAW … #define ALX_ISR_DMAR … #define ALX_ISR_TXF_UR … #define ALX_ISR_TX_Q3 … #define ALX_ISR_TX_Q2 … #define ALX_ISR_TX_Q1 … #define ALX_ISR_RFD_UR … #define ALX_ISR_RXF_OV … #define ALX_ISR_MANU … #define ALX_ISR_TIMER … #define ALX_ISR_SMB … #define ALX_IMR … /* re-send assert msg if SW no response */ #define ALX_INT_RETRIG … /* 40ms */ #define ALX_INT_RETRIG_TO … #define ALX_SMB_TIMER … #define ALX_TINT_TPD_THRSHLD … #define ALX_TINT_TIMER … #define ALX_CLK_GATE … #define ALX_CLK_GATE_RXMAC … #define ALX_CLK_GATE_TXMAC … #define ALX_CLK_GATE_RXQ … #define ALX_CLK_GATE_TXQ … #define ALX_CLK_GATE_DMAR … #define ALX_CLK_GATE_DMAW … #define ALX_CLK_GATE_ALL … /* interop between drivers */ #define ALX_DRV … #define ALX_DRV_PHY_AUTO … #define ALX_DRV_PHY_1000 … #define ALX_DRV_PHY_100 … #define ALX_DRV_PHY_10 … #define ALX_DRV_PHY_DUPLEX … /* bit23: adv Pause */ #define ALX_DRV_PHY_PAUSE … /* bit22: adv Asym Pause */ #define ALX_DRV_PHY_MASK … #define ALX_DRV_PHY_SHIFT … #define ALX_DRV_PHY_UNKNOWN … /* flag of phy inited */ #define ALX_PHY_INITED … /* reg 1830 ~ 186C for C0+, 16 bit map patterns and wake packet detection */ #define ALX_WOL_CTRL2 … #define ALX_WOL_CTRL2_DATA_STORE … #define ALX_WOL_CTRL2_PTRN_EVT … #define ALX_WOL_CTRL2_PME_PTRN_EN … #define ALX_WOL_CTRL2_PTRN_EN … #define ALX_WOL_CTRL3 … #define ALX_WOL_CTRL3_PTRN_ADDR_MASK … #define ALX_WOL_CTRL3_PTRN_ADDR_SHIFT … #define ALX_WOL_CTRL4 … #define ALX_WOL_CTRL4_PT15_MATCH … #define ALX_WOL_CTRL4_PT14_MATCH … #define ALX_WOL_CTRL4_PT13_MATCH … #define ALX_WOL_CTRL4_PT12_MATCH … #define ALX_WOL_CTRL4_PT11_MATCH … #define ALX_WOL_CTRL4_PT10_MATCH … #define ALX_WOL_CTRL4_PT9_MATCH … #define ALX_WOL_CTRL4_PT8_MATCH … #define ALX_WOL_CTRL4_PT7_MATCH … #define ALX_WOL_CTRL4_PT6_MATCH … #define ALX_WOL_CTRL4_PT5_MATCH … #define ALX_WOL_CTRL4_PT4_MATCH … #define ALX_WOL_CTRL4_PT3_MATCH … #define ALX_WOL_CTRL4_PT2_MATCH … #define ALX_WOL_CTRL4_PT1_MATCH … #define ALX_WOL_CTRL4_PT0_MATCH … #define ALX_WOL_CTRL4_PT15_EN … #define ALX_WOL_CTRL4_PT14_EN … #define ALX_WOL_CTRL4_PT13_EN … #define ALX_WOL_CTRL4_PT12_EN … #define ALX_WOL_CTRL4_PT11_EN … #define ALX_WOL_CTRL4_PT10_EN … #define ALX_WOL_CTRL4_PT9_EN … #define ALX_WOL_CTRL4_PT8_EN … #define ALX_WOL_CTRL4_PT7_EN … #define ALX_WOL_CTRL4_PT6_EN … #define ALX_WOL_CTRL4_PT5_EN … #define ALX_WOL_CTRL4_PT4_EN … #define ALX_WOL_CTRL4_PT3_EN … #define ALX_WOL_CTRL4_PT2_EN … #define ALX_WOL_CTRL4_PT1_EN … #define ALX_WOL_CTRL4_PT0_EN … #define ALX_WOL_CTRL5 … #define ALX_WOL_CTRL5_PT3_LEN_MASK … #define ALX_WOL_CTRL5_PT3_LEN_SHIFT … #define ALX_WOL_CTRL5_PT2_LEN_MASK … #define ALX_WOL_CTRL5_PT2_LEN_SHIFT … #define ALX_WOL_CTRL5_PT1_LEN_MASK … #define ALX_WOL_CTRL5_PT1_LEN_SHIFT … #define ALX_WOL_CTRL5_PT0_LEN_MASK … #define ALX_WOL_CTRL5_PT0_LEN_SHIFT … #define ALX_WOL_CTRL6 … #define ALX_WOL_CTRL5_PT7_LEN_MASK … #define ALX_WOL_CTRL5_PT7_LEN_SHIFT … #define ALX_WOL_CTRL5_PT6_LEN_MASK … #define ALX_WOL_CTRL5_PT6_LEN_SHIFT … #define ALX_WOL_CTRL5_PT5_LEN_MASK … #define ALX_WOL_CTRL5_PT5_LEN_SHIFT … #define ALX_WOL_CTRL5_PT4_LEN_MASK … #define ALX_WOL_CTRL5_PT4_LEN_SHIFT … #define ALX_WOL_CTRL7 … #define ALX_WOL_CTRL5_PT11_LEN_MASK … #define ALX_WOL_CTRL5_PT11_LEN_SHIFT … #define ALX_WOL_CTRL5_PT10_LEN_MASK … #define ALX_WOL_CTRL5_PT10_LEN_SHIFT … #define ALX_WOL_CTRL5_PT9_LEN_MASK … #define ALX_WOL_CTRL5_PT9_LEN_SHIFT … #define ALX_WOL_CTRL5_PT8_LEN_MASK … #define ALX_WOL_CTRL5_PT8_LEN_SHIFT … #define ALX_WOL_CTRL8 … #define ALX_WOL_CTRL5_PT15_LEN_MASK … #define ALX_WOL_CTRL5_PT15_LEN_SHIFT … #define ALX_WOL_CTRL5_PT14_LEN_MASK … #define ALX_WOL_CTRL5_PT14_LEN_SHIFT … #define ALX_WOL_CTRL5_PT13_LEN_MASK … #define ALX_WOL_CTRL5_PT13_LEN_SHIFT … #define ALX_WOL_CTRL5_PT12_LEN_MASK … #define ALX_WOL_CTRL5_PT12_LEN_SHIFT … #define ALX_ACER_FIXED_PTN0 … #define ALX_ACER_FIXED_PTN0_MASK … #define ALX_ACER_FIXED_PTN0_SHIFT … #define ALX_ACER_FIXED_PTN1 … #define ALX_ACER_FIXED_PTN1_MASK … #define ALX_ACER_FIXED_PTN1_SHIFT … #define ALX_ACER_RANDOM_NUM0 … #define ALX_ACER_RANDOM_NUM0_MASK … #define ALX_ACER_RANDOM_NUM0_SHIFT … #define ALX_ACER_RANDOM_NUM1 … #define ALX_ACER_RANDOM_NUM1_MASK … #define ALX_ACER_RANDOM_NUM1_SHIFT … #define ALX_ACER_RANDOM_NUM2 … #define ALX_ACER_RANDOM_NUM2_MASK … #define ALX_ACER_RANDOM_NUM2_SHIFT … #define ALX_ACER_RANDOM_NUM3 … #define ALX_ACER_RANDOM_NUM3_MASK … #define ALX_ACER_RANDOM_NUM3_SHIFT … #define ALX_ACER_MAGIC … #define ALX_ACER_MAGIC_EN … #define ALX_ACER_MAGIC_PME_EN … #define ALX_ACER_MAGIC_MATCH … #define ALX_ACER_MAGIC_FF_CHECK … #define ALX_ACER_MAGIC_RAN_LEN_MASK … #define ALX_ACER_MAGIC_RAN_LEN_SHIFT … #define ALX_ACER_MAGIC_FIX_LEN_MASK … #define ALX_ACER_MAGIC_FIX_LEN_SHIFT … #define ALX_ACER_TIMER … #define ALX_ACER_TIMER_EN … #define ALX_ACER_TIMER_PME_EN … #define ALX_ACER_TIMER_MATCH … #define ALX_ACER_TIMER_THRES_MASK … #define ALX_ACER_TIMER_THRES_SHIFT … #define ALX_ACER_TIMER_THRES_DEF … /* RSS definitions */ #define ALX_RSS_KEY0 … #define ALX_RSS_KEY1 … #define ALX_RSS_KEY2 … #define ALX_RSS_KEY3 … #define ALX_RSS_KEY4 … #define ALX_RSS_KEY5 … #define ALX_RSS_KEY6 … #define ALX_RSS_KEY7 … #define ALX_RSS_KEY8 … #define ALX_RSS_KEY9 … #define ALX_RSS_IDT_TBL0 … #define ALX_MSI_MAP_TBL1 … #define ALX_MSI_MAP_TBL1_TXQ1_SHIFT … #define ALX_MSI_MAP_TBL1_TXQ0_SHIFT … #define ALX_MSI_MAP_TBL1_RXQ3_SHIFT … #define ALX_MSI_MAP_TBL1_RXQ2_SHIFT … #define ALX_MSI_MAP_TBL1_RXQ1_SHIFT … #define ALX_MSI_MAP_TBL1_RXQ0_SHIFT … #define ALX_MSI_MAP_TBL2 … #define ALX_MSI_MAP_TBL2_TXQ3_SHIFT … #define ALX_MSI_MAP_TBL2_TXQ2_SHIFT … #define ALX_MSI_MAP_TBL2_RXQ7_SHIFT … #define ALX_MSI_MAP_TBL2_RXQ6_SHIFT … #define ALX_MSI_MAP_TBL2_RXQ5_SHIFT … #define ALX_MSI_MAP_TBL2_RXQ4_SHIFT … #define ALX_MSI_ID_MAP … #define ALX_MSI_RETRANS_TIMER … /* bit16: 1:line,0:standard */ #define ALX_MSI_MASK_SEL_LINE … #define ALX_MSI_RETRANS_TM_MASK … #define ALX_MSI_RETRANS_TM_SHIFT … /* CR DMA ctrl */ /* TX QoS */ #define ALX_WRR … #define ALX_WRR_PRI_MASK … #define ALX_WRR_PRI_SHIFT … #define ALX_WRR_PRI_RESTRICT_NONE … #define ALX_WRR_PRI3_MASK … #define ALX_WRR_PRI3_SHIFT … #define ALX_WRR_PRI2_MASK … #define ALX_WRR_PRI2_SHIFT … #define ALX_WRR_PRI1_MASK … #define ALX_WRR_PRI1_SHIFT … #define ALX_WRR_PRI0_MASK … #define ALX_WRR_PRI0_SHIFT … #define ALX_HQTPD … #define ALX_HQTPD_BURST_EN … #define ALX_HQTPD_Q3_NUMPREF_MASK … #define ALX_HQTPD_Q3_NUMPREF_SHIFT … #define ALX_HQTPD_Q2_NUMPREF_MASK … #define ALX_HQTPD_Q2_NUMPREF_SHIFT … #define ALX_HQTPD_Q1_NUMPREF_MASK … #define ALX_HQTPD_Q1_NUMPREF_SHIFT … #define ALX_MISC … #define ALX_MISC_PSW_OCP_MASK … #define ALX_MISC_PSW_OCP_SHIFT … #define ALX_MISC_PSW_OCP_DEF … #define ALX_MISC_ISO_EN … #define ALX_MISC_INTNLOSC_OPEN … #define ALX_MSIC2 … #define ALX_MSIC2_CALB_START … #define ALX_MISC3 … /* bit1: 1:Software control 25M */ #define ALX_MISC3_25M_BY_SW … /* bit0: 25M switch to intnl OSC */ #define ALX_MISC3_25M_NOTO_INTNL … /* MSIX tbl in memory space */ #define ALX_MSIX_ENTRY_BASE … /********************* PHY regs definition ***************************/ /* PHY Specific Status Register */ #define ALX_MII_GIGA_PSSR … #define ALX_GIGA_PSSR_SPD_DPLX_RESOLVED … #define ALX_GIGA_PSSR_DPLX … #define ALX_GIGA_PSSR_SPEED … #define ALX_GIGA_PSSR_10MBS … #define ALX_GIGA_PSSR_100MBS … #define ALX_GIGA_PSSR_1000MBS … /* PHY Interrupt Enable Register */ #define ALX_MII_IER … #define ALX_IER_LINK_UP … #define ALX_IER_LINK_DOWN … /* PHY Interrupt Status Register */ #define ALX_MII_ISR … #define ALX_MII_DBG_ADDR … #define ALX_MII_DBG_DATA … /***************************** debug port *************************************/ #define ALX_MIIDBG_ANACTRL … #define ALX_ANACTRL_DEF … #define ALX_MIIDBG_SYSMODCTRL … /* en half bias */ #define ALX_SYSMODCTRL_IECHOADJ_DEF … #define ALX_MIIDBG_SRDSYSMOD … #define ALX_SRDSYSMOD_DEEMP_EN … #define ALX_SRDSYSMOD_DEF … #define ALX_MIIDBG_HIBNEG … #define ALX_HIBNEG_PSHIB_EN … #define ALX_HIBNEG_HIB_PSE … #define ALX_HIBNEG_DEF … #define ALX_HIBNEG_NOHIB … #define ALX_MIIDBG_TST10BTCFG … #define ALX_TST10BTCFG_DEF … #define ALX_MIIDBG_AZ_ANADECT … #define ALX_AZ_ANADECT_DEF … #define ALX_AZ_ANADECT_LONG … #define ALX_MIIDBG_MSE16DB … #define ALX_MSE16DB_UP … #define ALX_MSE16DB_DOWN … #define ALX_MIIDBG_MSE20DB … #define ALX_MSE20DB_TH_MASK … #define ALX_MSE20DB_TH_SHIFT … #define ALX_MSE20DB_TH_DEF … #define ALX_MSE20DB_TH_HI … #define ALX_MIIDBG_AGC … #define ALX_AGC_2_VGA_MASK … #define ALX_AGC_2_VGA_SHIFT … #define ALX_AGC_LONG1G_LIMT … #define ALX_AGC_LONG100M_LIMT … #define ALX_MIIDBG_LEGCYPS … #define ALX_LEGCYPS_EN … #define ALX_LEGCYPS_DEF … #define ALX_MIIDBG_TST100BTCFG … #define ALX_TST100BTCFG_DEF … #define ALX_MIIDBG_GREENCFG … #define ALX_GREENCFG_DEF … #define ALX_MIIDBG_GREENCFG2 … #define ALX_GREENCFG2_BP_GREEN … #define ALX_GREENCFG2_GATE_DFSE_EN … /******* dev 3 *********/ #define ALX_MIIEXT_PCS … #define ALX_MIIEXT_CLDCTRL3 … #define ALX_CLDCTRL3_BP_CABLE1TH_DET_GT … #define ALX_MIIEXT_CLDCTRL5 … #define ALX_CLDCTRL5_BP_VD_HLFBIAS … #define ALX_MIIEXT_CLDCTRL6 … #define ALX_CLDCTRL6_CAB_LEN_MASK … #define ALX_CLDCTRL6_CAB_LEN_SHIFT … #define ALX_CLDCTRL6_CAB_LEN_SHORT1G … #define ALX_CLDCTRL6_CAB_LEN_SHORT100M … #define ALX_MIIEXT_VDRVBIAS … #define ALX_VDRVBIAS_DEF … /********* dev 7 **********/ #define ALX_MIIEXT_ANEG … #define ALX_MIIEXT_LOCAL_EEEADV … #define ALX_LOCAL_EEEADV_1000BT … #define ALX_LOCAL_EEEADV_100BT … #define ALX_MIIEXT_AFE … #define ALX_AFE_10BT_100M_TH … #define ALX_MIIEXT_S3DIG10 … /* bit0: 1:bypass 10BT rx fifo, 0:original 10BT rx */ #define ALX_MIIEXT_S3DIG10_SL … #define ALX_MIIEXT_S3DIG10_DEF … #define ALX_MIIEXT_NLP78 … #define ALX_MIIEXT_NLP78_120M_DEF … #endif
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