/* bnx2x_reg.h: Qlogic Everest network driver. * * Copyright (c) 2007-2013 Broadcom Corporation * Copyright (c) 2014 QLogic Corporation * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation. * * The registers description starts with the register Access type followed * by size in bits. For example [RW 32]. The access types are: * R - Read only * RC - Clear on read * RW - Read/Write * ST - Statistics register (clear on read) * W - Write only * WB - Wide bus register - the size is over 32 bits and it should be * read/write in consecutive 32 bits accesses * WR - Write Clear (write 1 to clear the bit) * */ #ifndef BNX2X_REG_H #define BNX2X_REG_H #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR … #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS … #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU … #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT … #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR … #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND … /* [RW 1] Initiate the ATC array - reset all the valid bits */ #define ATC_REG_ATC_INIT_ARRAY … /* [R 1] ATC initialization done */ #define ATC_REG_ATC_INIT_DONE … /* [RC 6] Interrupt register #0 read clear */ #define ATC_REG_ATC_INT_STS_CLR … /* [RW 5] Parity mask register #0 read/write */ #define ATC_REG_ATC_PRTY_MASK … /* [R 5] Parity register #0 read */ #define ATC_REG_ATC_PRTY_STS … /* [RC 5] Parity register #0 read clear */ #define ATC_REG_ATC_PRTY_STS_CLR … /* [RW 19] Interrupt mask register #0 read/write */ #define BRB1_REG_BRB1_INT_MASK … /* [R 19] Interrupt register #0 read */ #define BRB1_REG_BRB1_INT_STS … /* [RW 4] Parity mask register #0 read/write */ #define BRB1_REG_BRB1_PRTY_MASK … /* [R 4] Parity register #0 read */ #define BRB1_REG_BRB1_PRTY_STS … /* [RC 4] Parity register #0 read clear */ #define BRB1_REG_BRB1_PRTY_STS_CLR … /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning - * following reset the first rbc access to this reg must be write; there can * be no more rbc writes after the first one; there can be any number of rbc * read following the first write; rbc access not following these rules will * result in hang condition. */ #define BRB1_REG_FREE_LIST_PRS_CRDT … /* [RW 10] The number of free blocks below which the full signal to class 0 * is asserted */ #define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 … #define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 … /* [RW 11] The number of free blocks above which the full signal to class 0 * is de-asserted */ #define BRB1_REG_FULL_0_XON_THRESHOLD_0 … #define BRB1_REG_FULL_0_XON_THRESHOLD_1 … /* [RW 11] The number of free blocks below which the full signal to class 1 * is asserted */ #define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 … #define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 … /* [RW 11] The number of free blocks above which the full signal to class 1 * is de-asserted */ #define BRB1_REG_FULL_1_XON_THRESHOLD_0 … #define BRB1_REG_FULL_1_XON_THRESHOLD_1 … /* [RW 11] The number of free blocks below which the full signal to the LB * port is asserted */ #define BRB1_REG_FULL_LB_XOFF_THRESHOLD … /* [RW 10] The number of free blocks above which the full signal to the LB * port is de-asserted */ #define BRB1_REG_FULL_LB_XON_THRESHOLD … /* [RW 10] The number of free blocks above which the High_llfc signal to interface #n is de-asserted. */ #define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 … /* [RW 10] The number of free blocks below which the High_llfc signal to interface #n is asserted. */ #define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 … /* [RW 11] The number of blocks guarantied for the LB port */ #define BRB1_REG_LB_GUARANTIED … /* [RW 11] The hysteresis on the guarantied buffer space for the Lb port * before signaling XON. */ #define BRB1_REG_LB_GUARANTIED_HYST … /* [RW 24] LL RAM data. */ #define BRB1_REG_LL_RAM … /* [RW 10] The number of free blocks above which the Low_llfc signal to interface #n is de-asserted. */ #define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 … /* [RW 10] The number of free blocks below which the Low_llfc signal to interface #n is asserted. */ #define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 … /* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The * register is applicable only when per_class_guaranty_mode is set. */ #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED … /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC * 1 before signaling XON. The register is applicable only when * per_class_guaranty_mode is set. */ #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST … /* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The * register is applicable only when per_class_guaranty_mode is set. */ #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED … /* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0 * before signaling XON. The register is applicable only when * per_class_guaranty_mode is set. */ #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST … /* [RW 11] The number of blocks guarantied for class 0in MAC1.The register * is applicable only when per_class_guaranty_mode is set. */ #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED … /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC * 1 before signaling XON. The register is applicable only when * per_class_guaranty_mode is set. */ #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST … /* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The * register is applicable only when per_class_guaranty_mode is set. */ #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED … /* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC * 1 before signaling XON. The register is applicable only when * per_class_guaranty_mode is set. */ #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST … /* [RW 11] The number of blocks guarantied for the MAC port. The register is * applicable only when per_class_guaranty_mode is reset. */ #define BRB1_REG_MAC_GUARANTIED_0 … #define BRB1_REG_MAC_GUARANTIED_1 … /* [R 24] The number of full blocks. */ #define BRB1_REG_NUM_OF_FULL_BLOCKS … /* [ST 32] The number of cycles that the write_full signal towards MAC #0 was asserted. */ #define BRB1_REG_NUM_OF_FULL_CYCLES_0 … #define BRB1_REG_NUM_OF_FULL_CYCLES_1 … #define BRB1_REG_NUM_OF_FULL_CYCLES_4 … /* [ST 32] The number of cycles that the pause signal towards MAC #0 was asserted. */ #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 … #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 … /* [RW 10] The number of free blocks below which the pause signal to class 0 * is asserted */ #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 … #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 … /* [RW 11] The number of free blocks above which the pause signal to class 0 * is de-asserted */ #define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 … #define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 … /* [RW 11] The number of free blocks below which the pause signal to class 1 * is asserted */ #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 … #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 … /* [RW 11] The number of free blocks above which the pause signal to class 1 * is de-asserted */ #define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 … #define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 … /* [RW 10] Write client 0: De-assert pause threshold. Not Functional */ #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 … #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 … /* [RW 10] Write client 0: Assert pause threshold. */ #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 … /* [RW 1] Indicates if to use per-class guaranty mode (new mode) or per-MAC * guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC * mode). 1=per-class guaranty mode (new mode). */ #define BRB1_REG_PER_CLASS_GUARANTY_MODE … /* [R 24] The number of full blocks occpied by port. */ #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 … /* [RW 1] Reset the design by software. */ #define BRB1_REG_SOFT_RESET … /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */ #define CCM_REG_CAM_OCCUP … /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define CCM_REG_CCM_CFC_IFEN … /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define CCM_REG_CCM_CQM_IFEN … /* [RW 1] If set the Q index; received from the QM is inserted to event ID. Otherwise 0 is inserted. */ #define CCM_REG_CCM_CQM_USE_Q … /* [RW 11] Interrupt mask register #0 read/write */ #define CCM_REG_CCM_INT_MASK … /* [R 11] Interrupt register #0 read */ #define CCM_REG_CCM_INT_STS … /* [RW 27] Parity mask register #0 read/write */ #define CCM_REG_CCM_PRTY_MASK … /* [R 27] Parity register #0 read */ #define CCM_REG_CCM_PRTY_STS … /* [RC 27] Parity register #0 read clear */ #define CCM_REG_CCM_PRTY_STS_CLR … /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). Is used to determine the number of the AG context REG-pairs written back; when the input message Reg1WbFlg isn't set. */ #define CCM_REG_CCM_REG0_SZ … /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define CCM_REG_CCM_STORM0_IFEN … /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define CCM_REG_CCM_STORM1_IFEN … /* [RW 1] CDU AG read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define CCM_REG_CDU_AG_RD_IFEN … /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input are disregarded; all other signals are treated as usual; if 1 - normal activity. */ #define CCM_REG_CDU_AG_WR_IFEN … /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define CCM_REG_CDU_SM_RD_IFEN … /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid input is disregarded; all other signals are treated as usual; if 1 - normal activity. */ #define CCM_REG_CDU_SM_WR_IFEN … /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 1 at start-up. */ #define CCM_REG_CFC_INIT_CRD … /* [RW 2] Auxiliary counter flag Q number 1. */ #define CCM_REG_CNT_AUX1_Q … /* [RW 2] Auxiliary counter flag Q number 2. */ #define CCM_REG_CNT_AUX2_Q … /* [RW 28] The CM header value for QM request (primary). */ #define CCM_REG_CQM_CCM_HDR_P … /* [RW 28] The CM header value for QM request (secondary). */ #define CCM_REG_CQM_CCM_HDR_S … /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define CCM_REG_CQM_CCM_IFEN … /* [RW 6] QM output initial credit. Max credit available - 32. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 32 at start-up. */ #define CCM_REG_CQM_INIT_CRD … /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define CCM_REG_CQM_P_WEIGHT … /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define CCM_REG_CQM_S_WEIGHT … /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define CCM_REG_CSDM_IFEN … /* [RC 1] Set when the message length mismatch (relative to last indication) at the SDM interface is detected. */ #define CCM_REG_CSDM_LENGTH_MIS … /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define CCM_REG_CSDM_WEIGHT … /* [RW 28] The CM header for QM formatting in case of an error in the QM inputs. */ #define CCM_REG_ERR_CCM_HDR … /* [RW 8] The Event ID in case the input message ErrorFlg is set. */ #define CCM_REG_ERR_EVNT_ID … /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 64 at start-up. */ #define CCM_REG_FIC0_INIT_CRD … /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 64 at start-up. */ #define CCM_REG_FIC1_INIT_CRD … /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr; ~ccm_registers_gr_ld0_pr.gr_ld0_pr and ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and outputs to STORM: aggregation; load FIC0; load FIC1 and store. */ #define CCM_REG_GR_ARB_TYPE … /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed; that the Store channel priority is the complement to 4 of the rest priorities - Aggregation channel; Load (FIC0) channel and Load (FIC1). */ #define CCM_REG_GR_LD0_PR … /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed; that the Store channel priority is the complement to 4 of the rest priorities - Aggregation channel; Load (FIC0) channel and Load (FIC1). */ #define CCM_REG_GR_LD1_PR … /* [RW 2] General flags index. */ #define CCM_REG_INV_DONE_Q … /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _(0..15) stands for the connection type (one of 16). */ #define CCM_REG_N_SM_CTX_LD_0 … #define CCM_REG_N_SM_CTX_LD_1 … #define CCM_REG_N_SM_CTX_LD_2 … #define CCM_REG_N_SM_CTX_LD_3 … #define CCM_REG_N_SM_CTX_LD_4 … /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define CCM_REG_PBF_IFEN … /* [RC 1] Set when the message length mismatch (relative to last indication) at the pbf interface is detected. */ #define CCM_REG_PBF_LENGTH_MIS … /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define CCM_REG_PBF_WEIGHT … #define CCM_REG_PHYS_QNUM1_0 … #define CCM_REG_PHYS_QNUM1_1 … #define CCM_REG_PHYS_QNUM2_0 … #define CCM_REG_PHYS_QNUM2_1 … #define CCM_REG_PHYS_QNUM3_0 … #define CCM_REG_PHYS_QNUM3_1 … #define CCM_REG_QOS_PHYS_QNUM0_0 … #define CCM_REG_QOS_PHYS_QNUM0_1 … #define CCM_REG_QOS_PHYS_QNUM1_0 … #define CCM_REG_QOS_PHYS_QNUM1_1 … #define CCM_REG_QOS_PHYS_QNUM2_0 … #define CCM_REG_QOS_PHYS_QNUM2_1 … #define CCM_REG_QOS_PHYS_QNUM3_0 … #define CCM_REG_QOS_PHYS_QNUM3_1 … /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define CCM_REG_STORM_CCM_IFEN … /* [RC 1] Set when the message length mismatch (relative to last indication) at the STORM interface is detected. */ #define CCM_REG_STORM_LENGTH_MIS … /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin) mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2 (more prioritised); tc. */ #define CCM_REG_STORM_WEIGHT … /* [RW 1] Input tsem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define CCM_REG_TSEM_IFEN … /* [RC 1] Set when the message length mismatch (relative to last indication) at the tsem interface is detected. */ #define CCM_REG_TSEM_LENGTH_MIS … /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define CCM_REG_TSEM_WEIGHT … /* [RW 1] Input usem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define CCM_REG_USEM_IFEN … /* [RC 1] Set when message length mismatch (relative to last indication) at the usem interface is detected. */ #define CCM_REG_USEM_LENGTH_MIS … /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define CCM_REG_USEM_WEIGHT … /* [RW 1] Input xsem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define CCM_REG_XSEM_IFEN … /* [RC 1] Set when the message length mismatch (relative to last indication) at the xsem interface is detected. */ #define CCM_REG_XSEM_LENGTH_MIS … /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define CCM_REG_XSEM_WEIGHT … /* [RW 19] Indirect access to the descriptor table of the XX protection mechanism. The fields are: [5:0] - message length; [12:6] - message pointer; 18:13] - next pointer. */ #define CCM_REG_XX_DESCR_TABLE … #define CCM_REG_XX_DESCR_TABLE_SIZE … /* [R 7] Used to read the value of XX protection Free counter. */ #define CCM_REG_XX_FREE … /* [RW 6] Initial value for the credit counter; responsible for fulfilling of the Input Stage XX protection buffer by the XX protection pending messages. Max credit available - 127. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to maximum XX protected message size - 2 at start-up. */ #define CCM_REG_XX_INIT_CRD … /* [RW 7] The maximum number of pending messages; which may be stored in XX protection. At read the ~ccm_registers_xx_free.xx_free counter is read. At write comprises the start value of the ~ccm_registers_xx_free.xx_free counter. */ #define CCM_REG_XX_MSG_NUM … /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ #define CCM_REG_XX_OVFL_EVNT_ID … /* [RW 18] Indirect access to the XX table of the XX protection mechanism. The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] - header pointer. */ #define CCM_REG_XX_TABLE … #define CDU_REG_CDU_CHK_MASK0 … #define CDU_REG_CDU_CHK_MASK1 … #define CDU_REG_CDU_CONTROL0 … #define CDU_REG_CDU_DEBUG … #define CDU_REG_CDU_GLOBAL_PARAMS … /* [RW 7] Interrupt mask register #0 read/write */ #define CDU_REG_CDU_INT_MASK … /* [R 7] Interrupt register #0 read */ #define CDU_REG_CDU_INT_STS … /* [RW 5] Parity mask register #0 read/write */ #define CDU_REG_CDU_PRTY_MASK … /* [R 5] Parity register #0 read */ #define CDU_REG_CDU_PRTY_STS … /* [RC 5] Parity register #0 read clear */ #define CDU_REG_CDU_PRTY_STS_CLR … /* [RC 32] logging of error data in case of a CDU load error: {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error; ype_error; ctual_active; ctual_compressed_context}; */ #define CDU_REG_ERROR_DATA … /* [WB 216] L1TT ram access. each entry has the following format : {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0]; ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */ #define CDU_REG_L1TT … /* [WB 24] MATT ram access. each entry has the following format:{RegionLength[11:0]; egionOffset[11:0]} */ #define CDU_REG_MATT … /* [RW 1] when this bit is set the CDU operates in e1hmf mode */ #define CDU_REG_MF_MODE … /* [R 1] indication the initializing the activity counter by the hardware was done. */ #define CFC_REG_AC_INIT_DONE … /* [RW 13] activity counter ram access */ #define CFC_REG_ACTIVITY_COUNTER … #define CFC_REG_ACTIVITY_COUNTER_SIZE … /* [R 1] indication the initializing the cams by the hardware was done. */ #define CFC_REG_CAM_INIT_DONE … /* [RW 2] Interrupt mask register #0 read/write */ #define CFC_REG_CFC_INT_MASK … /* [R 2] Interrupt register #0 read */ #define CFC_REG_CFC_INT_STS … /* [RC 2] Interrupt register #0 read clear */ #define CFC_REG_CFC_INT_STS_CLR … /* [RW 4] Parity mask register #0 read/write */ #define CFC_REG_CFC_PRTY_MASK … /* [R 4] Parity register #0 read */ #define CFC_REG_CFC_PRTY_STS … /* [RC 4] Parity register #0 read clear */ #define CFC_REG_CFC_PRTY_STS_CLR … /* [RW 21] CID cam access (21:1 - Data; alid - 0) */ #define CFC_REG_CID_CAM … #define CFC_REG_CONTROL0 … #define CFC_REG_DEBUG0 … /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error vector) whether the cfc should be disabled upon it */ #define CFC_REG_DISABLE_ON_ERROR … /* [RC 14] CFC error vector. when the CFC detects an internal error it will set one of these bits. the bit description can be found in CFC specifications */ #define CFC_REG_ERROR_VECTOR … /* [WB 93] LCID info ram access */ #define CFC_REG_INFO_RAM … #define CFC_REG_INFO_RAM_SIZE … #define CFC_REG_INIT_REG … #define CFC_REG_INTERFACES … /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this field allows changing the priorities of the weighted-round-robin arbiter which selects which CFC load client should be served next */ #define CFC_REG_LCREQ_WEIGHTS … /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */ #define CFC_REG_LINK_LIST … #define CFC_REG_LINK_LIST_SIZE … /* [R 1] indication the initializing the link list by the hardware was done. */ #define CFC_REG_LL_INIT_DONE … /* [R 9] Number of allocated LCIDs which are at empty state */ #define CFC_REG_NUM_LCIDS_ALLOC … /* [R 9] Number of Arriving LCIDs in Link List Block */ #define CFC_REG_NUM_LCIDS_ARRIVING … #define CFC_REG_NUM_LCIDS_INSIDE_PF … /* [R 9] Number of Leaving LCIDs in Link List Block */ #define CFC_REG_NUM_LCIDS_LEAVING … #define CFC_REG_WEAK_ENABLE_PF … /* [RW 8] The event id for aggregated interrupt 0 */ #define CSDM_REG_AGG_INT_EVENT_0 … #define CSDM_REG_AGG_INT_EVENT_10 … #define CSDM_REG_AGG_INT_EVENT_11 … #define CSDM_REG_AGG_INT_EVENT_12 … #define CSDM_REG_AGG_INT_EVENT_13 … #define CSDM_REG_AGG_INT_EVENT_14 … #define CSDM_REG_AGG_INT_EVENT_15 … #define CSDM_REG_AGG_INT_EVENT_16 … #define CSDM_REG_AGG_INT_EVENT_2 … #define CSDM_REG_AGG_INT_EVENT_3 … #define CSDM_REG_AGG_INT_EVENT_4 … #define CSDM_REG_AGG_INT_EVENT_5 … #define CSDM_REG_AGG_INT_EVENT_6 … #define CSDM_REG_AGG_INT_EVENT_7 … #define CSDM_REG_AGG_INT_EVENT_8 … #define CSDM_REG_AGG_INT_EVENT_9 … /* [RW 1] For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1) */ #define CSDM_REG_AGG_INT_MODE_10 … #define CSDM_REG_AGG_INT_MODE_11 … #define CSDM_REG_AGG_INT_MODE_12 … #define CSDM_REG_AGG_INT_MODE_13 … #define CSDM_REG_AGG_INT_MODE_14 … #define CSDM_REG_AGG_INT_MODE_15 … #define CSDM_REG_AGG_INT_MODE_16 … #define CSDM_REG_AGG_INT_MODE_6 … #define CSDM_REG_AGG_INT_MODE_7 … #define CSDM_REG_AGG_INT_MODE_8 … #define CSDM_REG_AGG_INT_MODE_9 … /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ #define CSDM_REG_CFC_RSP_START_ADDR … /* [RW 16] The maximum value of the completion counter #0 */ #define CSDM_REG_CMP_COUNTER_MAX0 … /* [RW 16] The maximum value of the completion counter #1 */ #define CSDM_REG_CMP_COUNTER_MAX1 … /* [RW 16] The maximum value of the completion counter #2 */ #define CSDM_REG_CMP_COUNTER_MAX2 … /* [RW 16] The maximum value of the completion counter #3 */ #define CSDM_REG_CMP_COUNTER_MAX3 … /* [RW 13] The start address in the internal RAM for the completion counters. */ #define CSDM_REG_CMP_COUNTER_START_ADDR … /* [RW 32] Interrupt mask register #0 read/write */ #define CSDM_REG_CSDM_INT_MASK_0 … #define CSDM_REG_CSDM_INT_MASK_1 … /* [R 32] Interrupt register #0 read */ #define CSDM_REG_CSDM_INT_STS_0 … #define CSDM_REG_CSDM_INT_STS_1 … /* [RW 11] Parity mask register #0 read/write */ #define CSDM_REG_CSDM_PRTY_MASK … /* [R 11] Parity register #0 read */ #define CSDM_REG_CSDM_PRTY_STS … /* [RC 11] Parity register #0 read clear */ #define CSDM_REG_CSDM_PRTY_STS_CLR … #define CSDM_REG_ENABLE_IN1 … #define CSDM_REG_ENABLE_IN2 … #define CSDM_REG_ENABLE_OUT1 … #define CSDM_REG_ENABLE_OUT2 … /* [RW 4] The initial number of messages that can be sent to the pxp control interface without receiving any ACK. */ #define CSDM_REG_INIT_CREDIT_PXP_CTRL … /* [ST 32] The number of ACK after placement messages received */ #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE … /* [ST 32] The number of packet end messages received from the parser */ #define CSDM_REG_NUM_OF_PKT_END_MSG … /* [ST 32] The number of requests received from the pxp async if */ #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ … /* [ST 32] The number of commands received in queue 0 */ #define CSDM_REG_NUM_OF_Q0_CMD … /* [ST 32] The number of commands received in queue 10 */ #define CSDM_REG_NUM_OF_Q10_CMD … /* [ST 32] The number of commands received in queue 11 */ #define CSDM_REG_NUM_OF_Q11_CMD … /* [ST 32] The number of commands received in queue 1 */ #define CSDM_REG_NUM_OF_Q1_CMD … /* [ST 32] The number of commands received in queue 3 */ #define CSDM_REG_NUM_OF_Q3_CMD … /* [ST 32] The number of commands received in queue 4 */ #define CSDM_REG_NUM_OF_Q4_CMD … /* [ST 32] The number of commands received in queue 5 */ #define CSDM_REG_NUM_OF_Q5_CMD … /* [ST 32] The number of commands received in queue 6 */ #define CSDM_REG_NUM_OF_Q6_CMD … /* [ST 32] The number of commands received in queue 7 */ #define CSDM_REG_NUM_OF_Q7_CMD … /* [ST 32] The number of commands received in queue 8 */ #define CSDM_REG_NUM_OF_Q8_CMD … /* [ST 32] The number of commands received in queue 9 */ #define CSDM_REG_NUM_OF_Q9_CMD … /* [RW 13] The start address in the internal RAM for queue counters */ #define CSDM_REG_Q_COUNTER_START_ADDR … /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY … /* [R 1] parser fifo empty in sdm_sync block */ #define CSDM_REG_SYNC_PARSER_EMPTY … /* [R 1] parser serial fifo empty in sdm_sync block */ #define CSDM_REG_SYNC_SYNC_EMPTY … /* [RW 32] Tick for timer counter. Applicable only when ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */ #define CSDM_REG_TIMER_TICK … /* [RW 5] The number of time_slots in the arbitration cycle */ #define CSEM_REG_ARB_CYCLE_SIZE … /* [RW 3] The source that is associated with arbitration element 0. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2 */ #define CSEM_REG_ARB_ELEMENT0 … /* [RW 3] The source that is associated with arbitration element 1. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~csem_registers_arb_element0.arb_element0 */ #define CSEM_REG_ARB_ELEMENT1 … /* [RW 3] The source that is associated with arbitration element 2. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~csem_registers_arb_element0.arb_element0 and ~csem_registers_arb_element1.arb_element1 */ #define CSEM_REG_ARB_ELEMENT2 … /* [RW 3] The source that is associated with arbitration element 3. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2.Could not be equal to register ~csem_registers_arb_element0.arb_element0 and ~csem_registers_arb_element1.arb_element1 and ~csem_registers_arb_element2.arb_element2 */ #define CSEM_REG_ARB_ELEMENT3 … /* [RW 3] The source that is associated with arbitration element 4. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~csem_registers_arb_element0.arb_element0 and ~csem_registers_arb_element1.arb_element1 and ~csem_registers_arb_element2.arb_element2 and ~csem_registers_arb_element3.arb_element3 */ #define CSEM_REG_ARB_ELEMENT4 … /* [RW 32] Interrupt mask register #0 read/write */ #define CSEM_REG_CSEM_INT_MASK_0 … #define CSEM_REG_CSEM_INT_MASK_1 … /* [R 32] Interrupt register #0 read */ #define CSEM_REG_CSEM_INT_STS_0 … #define CSEM_REG_CSEM_INT_STS_1 … /* [RW 32] Parity mask register #0 read/write */ #define CSEM_REG_CSEM_PRTY_MASK_0 … #define CSEM_REG_CSEM_PRTY_MASK_1 … /* [R 32] Parity register #0 read */ #define CSEM_REG_CSEM_PRTY_STS_0 … #define CSEM_REG_CSEM_PRTY_STS_1 … /* [RC 32] Parity register #0 read clear */ #define CSEM_REG_CSEM_PRTY_STS_CLR_0 … #define CSEM_REG_CSEM_PRTY_STS_CLR_1 … #define CSEM_REG_ENABLE_IN … #define CSEM_REG_ENABLE_OUT … /* [RW 32] This address space contains all registers and memories that are placed in SEM_FAST block. The SEM_FAST registers are described in appendix B. In order to access the sem_fast registers the base address ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ #define CSEM_REG_FAST_MEMORY … /* [RW 1] Disables input messages from FIC0 May be updated during run_time by the microcode */ #define CSEM_REG_FIC0_DISABLE … /* [RW 1] Disables input messages from FIC1 May be updated during run_time by the microcode */ #define CSEM_REG_FIC1_DISABLE … /* [RW 15] Interrupt table Read and write access to it is not possible in the middle of the work */ #define CSEM_REG_INT_TABLE … /* [ST 24] Statistics register. The number of messages that entered through FIC0 */ #define CSEM_REG_MSG_NUM_FIC0 … /* [ST 24] Statistics register. The number of messages that entered through FIC1 */ #define CSEM_REG_MSG_NUM_FIC1 … /* [ST 24] Statistics register. The number of messages that were sent to FOC0 */ #define CSEM_REG_MSG_NUM_FOC0 … /* [ST 24] Statistics register. The number of messages that were sent to FOC1 */ #define CSEM_REG_MSG_NUM_FOC1 … /* [ST 24] Statistics register. The number of messages that were sent to FOC2 */ #define CSEM_REG_MSG_NUM_FOC2 … /* [ST 24] Statistics register. The number of messages that were sent to FOC3 */ #define CSEM_REG_MSG_NUM_FOC3 … /* [RW 1] Disables input messages from the passive buffer May be updated during run_time by the microcode */ #define CSEM_REG_PAS_DISABLE … /* [WB 128] Debug only. Passive buffer memory */ #define CSEM_REG_PASSIVE_BUFFER … /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ #define CSEM_REG_PRAM … /* [R 16] Valid sleeping threads indication have bit per thread */ #define CSEM_REG_SLEEP_THREADS_VALID … /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ #define CSEM_REG_SLOW_EXT_STORE_EMPTY … /* [RW 16] List of free threads . There is a bit per thread. */ #define CSEM_REG_THREADS_LIST … /* [RW 3] The arbitration scheme of time_slot 0 */ #define CSEM_REG_TS_0_AS … /* [RW 3] The arbitration scheme of time_slot 10 */ #define CSEM_REG_TS_10_AS … /* [RW 3] The arbitration scheme of time_slot 11 */ #define CSEM_REG_TS_11_AS … /* [RW 3] The arbitration scheme of time_slot 12 */ #define CSEM_REG_TS_12_AS … /* [RW 3] The arbitration scheme of time_slot 13 */ #define CSEM_REG_TS_13_AS … /* [RW 3] The arbitration scheme of time_slot 14 */ #define CSEM_REG_TS_14_AS … /* [RW 3] The arbitration scheme of time_slot 15 */ #define CSEM_REG_TS_15_AS … /* [RW 3] The arbitration scheme of time_slot 16 */ #define CSEM_REG_TS_16_AS … /* [RW 3] The arbitration scheme of time_slot 17 */ #define CSEM_REG_TS_17_AS … /* [RW 3] The arbitration scheme of time_slot 18 */ #define CSEM_REG_TS_18_AS … /* [RW 3] The arbitration scheme of time_slot 1 */ #define CSEM_REG_TS_1_AS … /* [RW 3] The arbitration scheme of time_slot 2 */ #define CSEM_REG_TS_2_AS … /* [RW 3] The arbitration scheme of time_slot 3 */ #define CSEM_REG_TS_3_AS … /* [RW 3] The arbitration scheme of time_slot 4 */ #define CSEM_REG_TS_4_AS … /* [RW 3] The arbitration scheme of time_slot 5 */ #define CSEM_REG_TS_5_AS … /* [RW 3] The arbitration scheme of time_slot 6 */ #define CSEM_REG_TS_6_AS … /* [RW 3] The arbitration scheme of time_slot 7 */ #define CSEM_REG_TS_7_AS … /* [RW 3] The arbitration scheme of time_slot 8 */ #define CSEM_REG_TS_8_AS … /* [RW 3] The arbitration scheme of time_slot 9 */ #define CSEM_REG_TS_9_AS … /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ #define CSEM_REG_VFPF_ERR_NUM … /* [RW 1] Parity mask register #0 read/write */ #define DBG_REG_DBG_PRTY_MASK … /* [R 1] Parity register #0 read */ #define DBG_REG_DBG_PRTY_STS … /* [RC 1] Parity register #0 read clear */ #define DBG_REG_DBG_PRTY_STS_CLR … /* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0; * 4.Completion function=0; 5.Error handling=0 */ #define DMAE_REG_BACKWARD_COMP_EN … /* [RW 32] Commands memory. The address to command X; row Y is to calculated as 14*X+Y. */ #define DMAE_REG_CMD_MEM … #define DMAE_REG_CMD_MEM_SIZE … /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c initial value is all ones. */ #define DMAE_REG_CRC16C_INIT … /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the CRC-16 T10 initial value is all ones. */ #define DMAE_REG_CRC16T10_INIT … /* [RW 2] Interrupt mask register #0 read/write */ #define DMAE_REG_DMAE_INT_MASK … /* [RW 4] Parity mask register #0 read/write */ #define DMAE_REG_DMAE_PRTY_MASK … /* [R 4] Parity register #0 read */ #define DMAE_REG_DMAE_PRTY_STS … /* [RC 4] Parity register #0 read clear */ #define DMAE_REG_DMAE_PRTY_STS_CLR … /* [RW 1] Command 0 go. */ #define DMAE_REG_GO_C0 … /* [RW 1] Command 1 go. */ #define DMAE_REG_GO_C1 … /* [RW 1] Command 10 go. */ #define DMAE_REG_GO_C10 … /* [RW 1] Command 11 go. */ #define DMAE_REG_GO_C11 … /* [RW 1] Command 12 go. */ #define DMAE_REG_GO_C12 … /* [RW 1] Command 13 go. */ #define DMAE_REG_GO_C13 … /* [RW 1] Command 14 go. */ #define DMAE_REG_GO_C14 … /* [RW 1] Command 15 go. */ #define DMAE_REG_GO_C15 … /* [RW 1] Command 2 go. */ #define DMAE_REG_GO_C2 … /* [RW 1] Command 3 go. */ #define DMAE_REG_GO_C3 … /* [RW 1] Command 4 go. */ #define DMAE_REG_GO_C4 … /* [RW 1] Command 5 go. */ #define DMAE_REG_GO_C5 … /* [RW 1] Command 6 go. */ #define DMAE_REG_GO_C6 … /* [RW 1] Command 7 go. */ #define DMAE_REG_GO_C7 … /* [RW 1] Command 8 go. */ #define DMAE_REG_GO_C8 … /* [RW 1] Command 9 go. */ #define DMAE_REG_GO_C9 … /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define DMAE_REG_GRC_IFEN … /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; full is asserted; all other signals are treated as usual; if 1 - normal activity. */ #define DMAE_REG_PCI_IFEN … /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the initial value to the credit counter; related to the address. Read returns the current value of the counter. */ #define DMAE_REG_PXP_REQ_INIT_CRD … /* [RW 8] Aggregation command. */ #define DORQ_REG_AGG_CMD0 … /* [RW 8] Aggregation command. */ #define DORQ_REG_AGG_CMD1 … /* [RW 8] Aggregation command. */ #define DORQ_REG_AGG_CMD2 … /* [RW 8] Aggregation command. */ #define DORQ_REG_AGG_CMD3 … /* [RW 28] UCM Header. */ #define DORQ_REG_CMHEAD_RX … /* [RW 32] Doorbell address for RBC doorbells (function 0). */ #define DORQ_REG_DB_ADDR0 … /* [RW 5] Interrupt mask register #0 read/write */ #define DORQ_REG_DORQ_INT_MASK … /* [R 5] Interrupt register #0 read */ #define DORQ_REG_DORQ_INT_STS … /* [RC 5] Interrupt register #0 read clear */ #define DORQ_REG_DORQ_INT_STS_CLR … /* [RW 2] Parity mask register #0 read/write */ #define DORQ_REG_DORQ_PRTY_MASK … /* [R 2] Parity register #0 read */ #define DORQ_REG_DORQ_PRTY_STS … /* [RC 2] Parity register #0 read clear */ #define DORQ_REG_DORQ_PRTY_STS_CLR … /* [RW 8] The address to write the DPM CID to STORM. */ #define DORQ_REG_DPM_CID_ADDR … /* [RW 5] The DPM mode CID extraction offset. */ #define DORQ_REG_DPM_CID_OFST … /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */ #define DORQ_REG_DQ_FIFO_AFULL_TH … /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */ #define DORQ_REG_DQ_FIFO_FULL_TH … /* [R 13] Current value of the DQ FIFO fill level according to following pointer. The range is 0 - 256 FIFO rows; where each row stands for the doorbell. */ #define DORQ_REG_DQ_FILL_LVLF … /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or equal to full threshold; reset on full clear. */ #define DORQ_REG_DQ_FULL_ST … /* [RW 28] The value sent to CM header in the case of CFC load error. */ #define DORQ_REG_ERR_CMHEAD … #define DORQ_REG_IF_EN … #define DORQ_REG_MAX_RVFID_SIZE … #define DORQ_REG_MODE_ACT … /* [RW 5] The normal mode CID extraction offset. */ #define DORQ_REG_NORM_CID_OFST … /* [RW 28] TCM Header when only TCP context is loaded. */ #define DORQ_REG_NORM_CMHEAD_TX … /* [RW 3] The number of simultaneous outstanding requests to Context Fetch Interface. */ #define DORQ_REG_OUTST_REQ … #define DORQ_REG_PF_USAGE_CNT … #define DORQ_REG_REGN … /* [R 4] Current value of response A counter credit. Initial credit is configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd register. */ #define DORQ_REG_RSPA_CRD_CNT … /* [R 4] Current value of response B counter credit. Initial credit is configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd register. */ #define DORQ_REG_RSPB_CRD_CNT … /* [RW 4] The initial credit at the Doorbell Response Interface. The write writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The read reads this written value. */ #define DORQ_REG_RSP_INIT_CRD … #define DORQ_REG_RSPB_CRD_CNT … #define DORQ_REG_VF_NORM_CID_BASE … #define DORQ_REG_VF_NORM_CID_OFST … #define DORQ_REG_VF_NORM_CID_WND_SIZE … #define DORQ_REG_VF_NORM_MAX_CID_COUNT … #define DORQ_REG_VF_NORM_VF_BASE … /* [RW 10] VF type validation mask value */ #define DORQ_REG_VF_TYPE_MASK_0 … /* [RW 17] VF type validation Min MCID value */ #define DORQ_REG_VF_TYPE_MAX_MCID_0 … /* [RW 17] VF type validation Max MCID value */ #define DORQ_REG_VF_TYPE_MIN_MCID_0 … /* [RW 10] VF type validation comp value */ #define DORQ_REG_VF_TYPE_VALUE_0 … #define DORQ_REG_VF_USAGE_CT_LIMIT … /* [RW 4] Initial activity counter value on the load request; when the shortcut is done. */ #define DORQ_REG_SHRT_ACT_CNT … /* [RW 28] TCM Header when both ULP and TCP context is loaded. */ #define DORQ_REG_SHRT_CMHEAD … #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 … #define HC_CONFIG_0_REG_BLOCK_DISABLE_0 … #define HC_CONFIG_0_REG_INT_LINE_EN_0 … #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 … #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 … #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 … #define HC_CONFIG_1_REG_BLOCK_DISABLE_1 … #define DORQ_REG_VF_USAGE_CNT … #define HC_REG_AGG_INT_0 … #define HC_REG_AGG_INT_1 … #define HC_REG_ATTN_BIT … #define HC_REG_ATTN_IDX … #define HC_REG_ATTN_MSG0_ADDR_L … #define HC_REG_ATTN_MSG1_ADDR_L … #define HC_REG_ATTN_NUM_P0 … #define HC_REG_ATTN_NUM_P1 … #define HC_REG_COMMAND_REG … #define HC_REG_CONFIG_0 … #define HC_REG_CONFIG_1 … #define HC_REG_FUNC_NUM_P0 … #define HC_REG_FUNC_NUM_P1 … /* [RW 3] Parity mask register #0 read/write */ #define HC_REG_HC_PRTY_MASK … /* [R 3] Parity register #0 read */ #define HC_REG_HC_PRTY_STS … /* [RC 3] Parity register #0 read clear */ #define HC_REG_HC_PRTY_STS_CLR … #define HC_REG_INT_MASK … #define HC_REG_LEADING_EDGE_0 … #define HC_REG_LEADING_EDGE_1 … #define HC_REG_MAIN_MEMORY … #define HC_REG_MAIN_MEMORY_SIZE … #define HC_REG_P0_PROD_CONS … #define HC_REG_P1_PROD_CONS … #define HC_REG_PBA_COMMAND … #define HC_REG_PCI_CONFIG_0 … #define HC_REG_PCI_CONFIG_1 … #define HC_REG_STATISTIC_COUNTERS … #define HC_REG_TRAILING_EDGE_0 … #define HC_REG_TRAILING_EDGE_1 … #define HC_REG_UC_RAM_ADDR_0 … #define HC_REG_UC_RAM_ADDR_1 … #define HC_REG_USTORM_ADDR_FOR_COALESCE … #define HC_REG_VQID_0 … #define HC_REG_VQID_1 … #define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN … #define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE … #define IGU_REG_ATTENTION_ACK_BITS … /* [R 4] Debug: attn_fsm */ #define IGU_REG_ATTN_FSM … #define IGU_REG_ATTN_MSG_ADDR_H … #define IGU_REG_ATTN_MSG_ADDR_L … /* [R 4] Debug: [3] - attention write done message is pending (0-no pending; * 1-pending). [2:0] = PFID. Pending means attention message was sent; but * write done didn't receive. */ #define IGU_REG_ATTN_WRITE_DONE_PENDING … #define IGU_REG_BLOCK_CONFIGURATION … #define IGU_REG_COMMAND_REG_32LSB_DATA … #define IGU_REG_COMMAND_REG_CTRL … /* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit * is clear. The bits in this registers are set and clear via the producer * command. Data valid only in addresses 0-4. all the rest are zero. */ #define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP … /* [R 5] Debug: ctrl_fsm */ #define IGU_REG_CTRL_FSM … /* [R 1] data available for error memory. If this bit is clear do not red * from error_handling_memory. */ #define IGU_REG_ERROR_HANDLING_DATA_VALID … /* [RW 11] Parity mask register #0 read/write */ #define IGU_REG_IGU_PRTY_MASK … /* [R 11] Parity register #0 read */ #define IGU_REG_IGU_PRTY_STS … /* [RC 11] Parity register #0 read clear */ #define IGU_REG_IGU_PRTY_STS_CLR … /* [R 4] Debug: int_handle_fsm */ #define IGU_REG_INT_HANDLE_FSM … #define IGU_REG_LEADING_EDGE_LATCH … /* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid. * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */ #define IGU_REG_MAPPING_MEMORY … #define IGU_REG_MAPPING_MEMORY_SIZE … #define IGU_REG_PBA_STATUS_LSB … #define IGU_REG_PBA_STATUS_MSB … #define IGU_REG_PCI_PF_MSI_EN … #define IGU_REG_PCI_PF_MSIX_EN … #define IGU_REG_PCI_PF_MSIX_FUNC_MASK … /* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no * pending; 1 = pending. Pendings means interrupt was asserted; and write * done was not received. Data valid only in addresses 0-4. all the rest are * zero. */ #define IGU_REG_PENDING_BITS_STATUS … #define IGU_REG_PF_CONFIGURATION … /* [RW 20] producers only. E2 mode: address 0-135 match to the mapping * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod; * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode * - In backward compatible mode; for non default SB; each even line in the * memory holds the U producer and each odd line hold the C producer. The * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The * last 20 producers are for the DSB for each PF. each PF has five segments * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods; * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */ #define IGU_REG_PROD_CONS_MEMORY … /* [R 3] Debug: pxp_arb_fsm */ #define IGU_REG_PXP_ARB_FSM … /* [RW 6] Write one for each bit will reset the appropriate memory. When the * memory reset finished the appropriate bit will be clear. Bit 0 - mapping * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */ #define IGU_REG_RESET_MEMORIES … /* [R 4] Debug: sb_ctrl_fsm */ #define IGU_REG_SB_CTRL_FSM … #define IGU_REG_SB_INT_BEFORE_MASK_LSB … #define IGU_REG_SB_INT_BEFORE_MASK_MSB … #define IGU_REG_SB_MASK_LSB … #define IGU_REG_SB_MASK_MSB … /* [RW 16] Number of command that were dropped without causing an interrupt * due to: read access for WO BAR address; or write access for RO BAR * address or any access for reserved address or PCI function error is set * and address is not MSIX; PBA or cleanup */ #define IGU_REG_SILENT_DROP … /* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 - * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per * PF; 68-71 number of ATTN messages per PF */ #define IGU_REG_STATISTIC_NUM_MESSAGE_SENT … /* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a * timer mask command arrives. Value must be bigger than 100. */ #define IGU_REG_TIMER_MASKING_VALUE … #define IGU_REG_TRAILING_EDGE_LATCH … #define IGU_REG_VF_CONFIGURATION … /* [WB_R 32] Each bit represent write done pending bits status for that SB * (MSI/MSIX message was sent and write done was not received yet). 0 = * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */ #define IGU_REG_WRITE_DONE_PENDING … #define MCP_A_REG_MCPR_SCRATCH … #define MCP_REG_MCPR_ACCESS_LOCK … #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER … #define MCP_REG_MCPR_GP_INPUTS … #define MCP_REG_MCPR_GP_OENABLE … #define MCP_REG_MCPR_GP_OUTPUTS … #define MCP_REG_MCPR_IMC_COMMAND … #define MCP_REG_MCPR_IMC_DATAREG0 … #define MCP_REG_MCPR_IMC_SLAVE_CONTROL … #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER … #define MCP_REG_MCPR_NVM_ACCESS_ENABLE … #define MCP_REG_MCPR_NVM_ADDR … #define MCP_REG_MCPR_NVM_CFG4 … #define MCP_REG_MCPR_NVM_COMMAND … #define MCP_REG_MCPR_NVM_READ … #define MCP_REG_MCPR_NVM_SW_ARB … #define MCP_REG_MCPR_NVM_WRITE … #define MCP_REG_MCPR_SCRATCH … #define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK … #define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK … /* [R 32] read first 32 bit after inversion of function 0. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 … #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 … /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ #define MISC_REG_AEU_AFTER_INVERT_1_MCP … /* [R 32] read second 32 bit after inversion of function 0. mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 … #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 … /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ #define MISC_REG_AEU_AFTER_INVERT_2_MCP … /* [R 32] read third 32 bit after inversion of function 0. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1; */ #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 … #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 … /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1; */ #define MISC_REG_AEU_AFTER_INVERT_3_MCP … /* [R 32] read fourth 32 bit after inversion of function 0. mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 … #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 … /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ #define MISC_REG_AEU_AFTER_INVERT_4_MCP … /* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */ #define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 … /* [W 14] write to this register results with the clear of the latched signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP latch; one in d5 clears GRC Latched timeout attention; one in d6 clears GRC Latched reserved access attention; one in d7 clears Latched rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read from this register return zero */ #define MISC_REG_AEU_CLR_LATCH_SIGNAL … /* [RW 32] first 32b for enabling the output for function 0 output0. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 … #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 … #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 … #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 … #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 … #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 … #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 … /* [RW 32] first 32b for enabling the output for function 1 output0. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 … #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 … #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 … #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 … #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 … #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 … #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 … /* [RW 32] first 32b for enabling the output for close the gate nig. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ #define MISC_REG_AEU_ENABLE1_NIG_0 … #define MISC_REG_AEU_ENABLE1_NIG_1 … /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ #define MISC_REG_AEU_ENABLE1_PXP_0 … #define MISC_REG_AEU_ENABLE1_PXP_1 … /* [RW 32] second 32b for enabling the output for function 0 output0. mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 … #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 … /* [RW 32] second 32b for enabling the output for function 1 output0. mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 … #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 … /* [RW 32] second 32b for enabling the output for close the gate nig. mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ #define MISC_REG_AEU_ENABLE2_NIG_0 … #define MISC_REG_AEU_ENABLE2_NIG_1 … /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ #define MISC_REG_AEU_ENABLE2_PXP_0 … #define MISC_REG_AEU_ENABLE2_PXP_1 … /* [RW 32] third 32b for enabling the output for function 0 output0. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1; */ #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 … #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 … /* [RW 32] third 32b for enabling the output for function 1 output0. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1; */ #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 … #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 … /* [RW 32] third 32b for enabling the output for close the gate nig. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1; */ #define MISC_REG_AEU_ENABLE3_NIG_0 … #define MISC_REG_AEU_ENABLE3_NIG_1 … /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General attn1; */ #define MISC_REG_AEU_ENABLE3_PXP_0 … #define MISC_REG_AEU_ENABLE3_PXP_1 … /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 … #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 … #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 … #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 … #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 … #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 … /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 … #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 … #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 … #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 … #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 … #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 … /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ #define MISC_REG_AEU_ENABLE4_NIG_0 … #define MISC_REG_AEU_ENABLE4_NIG_1 … /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] General attn8; [7] General attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] General attn13; [12] General attn14; [13] General attn15; [14] General attn16; [15] General attn17; [16] General attn18; [17] General attn19; [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved access attention; [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ #define MISC_REG_AEU_ENABLE4_PXP_0 … #define MISC_REG_AEU_ENABLE4_PXP_1 … /* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 * parity; [31-10] Reserved; */ #define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 … /* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 * parity; [31-10] Reserved; */ #define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 … /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu 128 bit vector */ #define MISC_REG_AEU_GENERAL_ATTN_0 … #define MISC_REG_AEU_GENERAL_ATTN_1 … #define MISC_REG_AEU_GENERAL_ATTN_10 … #define MISC_REG_AEU_GENERAL_ATTN_11 … #define MISC_REG_AEU_GENERAL_ATTN_12 … #define MISC_REG_AEU_GENERAL_ATTN_2 … #define MISC_REG_AEU_GENERAL_ATTN_3 … #define MISC_REG_AEU_GENERAL_ATTN_4 … #define MISC_REG_AEU_GENERAL_ATTN_5 … #define MISC_REG_AEU_GENERAL_ATTN_6 … #define MISC_REG_AEU_GENERAL_ATTN_7 … #define MISC_REG_AEU_GENERAL_ATTN_8 … #define MISC_REG_AEU_GENERAL_ATTN_9 … #define MISC_REG_AEU_GENERAL_MASK … /* [RW 32] first 32b for inverting the input for function 0; for each bit: 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ #define MISC_REG_AEU_INVERTER_1_FUNC_0 … #define MISC_REG_AEU_INVERTER_1_FUNC_1 … /* [RW 32] second 32b for inverting the input for function 0; for each bit: 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ #define MISC_REG_AEU_INVERTER_2_FUNC_0 … #define MISC_REG_AEU_INVERTER_2_FUNC_1 … /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0; [9:8] = raserved. Zero = mask; one = unmask */ #define MISC_REG_AEU_MASK_ATTN_FUNC_0 … #define MISC_REG_AEU_MASK_ATTN_FUNC_1 … /* [RW 1] If set a system kill occurred */ #define MISC_REG_AEU_SYS_KILL_OCCURRED … /* [RW 32] Represent the status of the input vector to the AEU when a system kill occurred. The register is reset in por reset. Mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ #define MISC_REG_AEU_SYS_KILL_STATUS_0 … #define MISC_REG_AEU_SYS_KILL_STATUS_1 … #define MISC_REG_AEU_SYS_KILL_STATUS_2 … #define MISC_REG_AEU_SYS_KILL_STATUS_3 … /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1 Port. */ #define MISC_REG_BOND_ID … /* [R 16] These bits indicate the part number for the chip. */ #define MISC_REG_CHIP_NUM … /* [R 4] These bits indicate the base revision of the chip. This value starts at 0x0 for the A0 tape-out and increments by one for each all-layer tape-out. */ #define MISC_REG_CHIP_REV … /* [R 14] otp_misc_do[100:0] spare bits collection: 13:11- * otp_misc_do[100:98]; 10:7 - otp_misc_do[87:84]; 6:3 - otp_misc_do[75:72]; * 2:1 - otp_misc_do[51:50]; 0 - otp_misc_do[1]. */ #define MISC_REG_CHIP_TYPE … #define MISC_REG_CHIP_TYPE_57811_MASK … #define MISC_REG_CPMU_LP_DR_ENABLE … /* [RW 1] FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled * by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk * 25MHz. Reset on hard reset. */ #define MISC_REG_CPMU_LP_FW_ENABLE_P0 … /* [RW 32] EEE LPI Idle Threshold. The threshold value for the idle EEE LPI * counter. Timer tick is 1 us. Clock 25MHz. Reset on hard reset. */ #define MISC_REG_CPMU_LP_IDLE_THR_P0 … /* [RW 18] LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that * the Vmain SM end state is disabled. When 0 indicates that the Vmain SM * end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that * the FW command that all Queues are empty is disabled. When 0 indicates * that the FW command that all Queues are empty is enabled. [2] - FW Early * Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early * Exit command is disabled. When 0 indicates that the FW Early Exit command * is enabled. This bit applicable only in the EXIT Events Mask registers. * [3] - PBF Request Mask. When 1 indicates that the PBF Request indication * is disabled. When 0 indicates that the PBF Request indication is enabled. * [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF * Request indication is disabled. When 0 indicates that the Tx Other Than * PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1 * indicates that the RX EEE LPI Status indication is disabled. When 0 * indicates that the RX EEE LPI Status indication is enabled. In the EXIT * Events Masks registers; this bit masks the falling edge detect of the LPI * Status (Rx LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that * the Tx Pause indication is disabled. When 0 indicates that the Tx Pause * indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the * BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY * indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM * IDLE indication is disabled. When 0 indicates that the QM IDLE indication * is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When * 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0 * indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1 * Status Mask. When 1 indicates that the L1 Status indication from the PCIE * CORE is disabled. When 0 indicates that the RX EEE LPI Status indication * from the PCIE CORE is enabled. In the EXIT Events Masks registers; this * bit masks the falling edge detect of the L1 status (L1 is on - off). [11] * - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE * LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI * REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1 * indicates that the P0 EEE LPI REQ indication is disabled. When =0 * indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE * LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is * disabled. When =0 indicates that the P0 EEE LPI REQ indication is * enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ * indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1 * REQ indication is disabled. When =0 indicates that the L1 indication is * enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates * that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx * EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status * Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This * bit is applicable only in the EXIT Events Masks registers. [17] - L1 * Status Edge Detect Mask. When =1 indicates that the L1 Status Falling * Edge Detect indication from the PCIE CORE is disabled (L1 is on - off). * When =0 indicates that the L1 Status Falling Edge Detect indication from * the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in * the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset. */ #define MISC_REG_CPMU_LP_MASK_ENT_P0 … /* [RW 18] EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates * that the Vmain SM end state is disabled. When 0 indicates that the Vmain * SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates * that the FW command that all Queues are empty is disabled. When 0 * indicates that the FW command that all Queues are empty is enabled. [2] - * FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW * Early Exit command is disabled. When 0 indicates that the FW Early Exit * command is enabled. This bit applicable only in the EXIT Events Mask * registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request * indication is disabled. When 0 indicates that the PBF Request indication * is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other * Than PBF Request indication is disabled. When 0 indicates that the Tx * Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status * Mask. When 1 indicates that the RX EEE LPI Status indication is disabled. * When 0 indicates that the RX LPI Status indication is enabled. In the * EXIT Events Masks registers; this bit masks the falling edge detect of * the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1 * indicates that the Tx Pause indication is disabled. When 0 indicates that * the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1 * indicates that the BRB1 EMPTY indication is disabled. When 0 indicates * that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1 * indicates that the QM IDLE indication is disabled. When 0 indicates that * the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9] * - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for * LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for * LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1 * Status indication from the PCIE CORE is disabled. When 0 indicates that * the RX EEE LPI Status indication from the PCIE CORE is enabled. In the * EXIT Events Masks registers; this bit masks the falling edge detect of * the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When * =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When * =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1 * E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication * is disabled. When =0 indicates that the P0 EEE LPI REQ indication is * enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ * indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates * that the P0 EEE LPI REQ indication is disabled. When =0 indicates that * the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1 * indicates that the L1 REQ indication is disabled. When =0 indicates that * the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask. * When =1 indicates that the RX EEE LPI Status Falling Edge Detect * indication is disabled (Rx EEE LPI is on - off). When =0 indicates that * the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE * LPI is on - off). This bit is applicable only in the EXIT Events Masks * registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the * L1 Status Falling Edge Detect indication from the PCIE CORE is disabled * (L1 is on - off). When =0 indicates that the L1 Status Falling Edge * Detect indication from the PCIE CORE is enabled (L1 is on - off). This * bit is applicable only in the EXIT Events Masks registers.Clock 25MHz. * Reset on hard reset. */ #define MISC_REG_CPMU_LP_MASK_EXT_P0 … /* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only * register. Reset on hard reset. */ #define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 … /* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only * register. Reset on hard reset. */ #define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 … /* [RW 32] The following driver registers(1...16) represent 16 drivers and 32 clients. Each client can be controlled by one driver only. One in each bit represent that this driver control the appropriate client (Ex: bit 5 is set means this driver control client number 5). addr1 = set; addr0 = clear; read from both addresses will give the same result = status. write to address 1 will set a request to control all the clients that their appropriate bit (in the write command) is set. if the client is free (the appropriate bit in all the other drivers is clear) one will be written to that driver register; if the client isn't free the bit will remain zero. if the appropriate bit is set (the driver request to gain control on a client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). write to address 0 will set a request to free all the clients that their appropriate bit (in the write command) is set. if the appropriate bit is clear (the driver request to free a client it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted). */ #define MISC_REG_DRIVER_CONTROL_1 … #define MISC_REG_DRIVER_CONTROL_7 … /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0 only. */ #define MISC_REG_E1HMF_MODE … /* [R 1] Status of four port mode path swap input pin. */ #define MISC_REG_FOUR_PORT_PATH_SWAP … /* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 - the path_swap output is equal to 4 port mode path swap input pin; if it is 1 - the path_swap output is equal to bit[1] of this register; [1] - Overwrite value. If bit[0] of this register is 1 this is the value that receives the path_swap output. Reset on Hard reset. */ #define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR … /* [R 1] Status of 4 port mode port swap input pin. */ #define MISC_REG_FOUR_PORT_PORT_SWAP … /* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 - the port_swap output is equal to 4 port mode port swap input pin; if it is 1 - the port_swap output is equal to bit[1] of this register; [1] - Overwrite value. If bit[0] of this register is 1 this is the value that receives the port_swap output. Reset on Hard reset. */ #define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR … /* [RW 32] Debug only: spare RW register reset by core reset */ #define MISC_REG_GENERIC_CR_0 … #define MISC_REG_GENERIC_CR_1 … /* [RW 32] Debug only: spare RW register reset by por reset */ #define MISC_REG_GENERIC_POR_1 … /* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO can not be configured as an output. Each output has its output enable in the MCP register space; but this bit needs to be set to make use of that. Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON. When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change the i/o to an output and will drive the TimeSync output. Bit[31:7]: spare. Global register. Reset by hard reset. */ #define MISC_REG_GEN_PURP_HWG … /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of these bits is written as a '1'; the corresponding SPIO bit will turn off it's drivers and become an input. This is the reset state of all GPIO pins. The read value of these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff). [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written as a '1'; the corresponding GPIO bit will drive low. The read value of these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0; SET When any of these bits is written as a '1'; the corresponding GPIO bit will drive high (if it has that capability). The read value of these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0; RO; These bits indicate the read value of each of the eight GPIO pins. This is the result value of the pin; not the drive value. Writing these bits will have not effect. */ #define MISC_REG_GPIO … /* [RW 8] These bits enable the GPIO_INTs to signals event to the IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2] p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2; [7] p1_gpio_3; */ #define MISC_REG_GPIO_EVENT_EN … /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a '1' to these bit clears the corresponding bit in the #OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0; Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1; OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input value. When the ~INT_STATE bit is set; this bit indicates the OLD value of the pin such that if ~INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in #OLD_VALUE (reset value 0). */ #define MISC_REG_GPIO_INT … /* [R 28] this field hold the last information that caused reserved attention. bits [19:0] - address; [22:20] function; [23] reserved; [27:24] the master that caused the attention - according to the following encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = dbu; 8 = dmae */ #define MISC_REG_GRC_RSV_ATTN … /* [R 28] this field hold the last information that caused timeout attention. bits [19:0] - address; [22:20] function; [23] reserved; [27:24] the master that caused the attention - according to the following encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = dbu; 8 = dmae */ #define MISC_REG_GRC_TIMEOUT_ATTN … /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any access that does not finish within ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is cleared; this timeout is disabled. If this timeout occurs; the GRC shall assert it attention output. */ #define MISC_REG_GRC_TIMEOUT_EN … /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of the bits is: [2:0] OAC reset value 001) CML output buffer bias control; 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl (reset value 001) Charge pump current control; 111 for 720u; 011 for 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00) Global bias control; When bit 7 is high bias current will be 10 0gh; When bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8] Pll_observe (reset value 010) Bits to control observability. bit 10 is for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted internally). [14] reserved (reset value 0) Reset for VCO sequencer is connected to RESET input directly. [15] capRetry_en (reset value 0) enable retry on cap search failure (inverted). [16] freqMonitor_e (reset value 0) bit to continuously monitor vco freq (inverted). [17] freqDetRestart_en (reset value 0) bit to enable restart when not freq locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable retry on freq det failure(inverted). [19] pllForceFdone_en (reset value 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20] pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0) bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force capPass. [26] capRestart (reset value 0) bit to force cap sequencer to restart. [27] capSelectM_en (reset value 0) bit to enable cap select register bits. */ #define MISC_REG_LCPLL_CTRL_1 … #define MISC_REG_LCPLL_CTRL_REG_2 … /* [RW 1] LCPLL power down. Global register. Active High. Reset on POR * reset. */ #define MISC_REG_LCPLL_E40_PWRDWN … /* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */ #define MISC_REG_LCPLL_E40_RESETB_ANA … /* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR * reset. */ #define MISC_REG_LCPLL_E40_RESETB_DIG … /* [RW 4] Interrupt mask register #0 read/write */ #define MISC_REG_MISC_INT_MASK … /* [RW 1] Parity mask register #0 read/write */ #define MISC_REG_MISC_PRTY_MASK … /* [R 1] Parity register #0 read */ #define MISC_REG_MISC_PRTY_STS … /* [RC 1] Parity register #0 read clear */ #define MISC_REG_MISC_PRTY_STS_CLR … #define MISC_REG_NIG_WOL_P0 … #define MISC_REG_NIG_WOL_P1 … /* [R 1] If set indicate that the pcie_rst_b was asserted without perst assertion */ #define MISC_REG_PCIE_HOT_RESET … /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911. inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9] freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1] (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16] Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0); [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25] Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27] testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29] testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31] testa_en (reset value 0); */ #define MISC_REG_PLL_STORM_CTRL_1 … #define MISC_REG_PLL_STORM_CTRL_2 … #define MISC_REG_PLL_STORM_CTRL_3 … #define MISC_REG_PLL_STORM_CTRL_4 … /* [R 1] Status of 4 port mode enable input pin. */ #define MISC_REG_PORT4MODE_EN … /* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 - * the port4mode_en output is equal to 4 port mode input pin; if it is 1 - * the port4mode_en output is equal to bit[1] of this register; [1] - * Overwrite value. If bit[0] of this register is 1 this is the value that * receives the port4mode_en output . */ #define MISC_REG_PORT4MODE_EN_OVWR … /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset; write/read zero = the specific block is in reset; addr 0-wr- the write value will be written to the register; addr 1-set - one will be written to all the bits that have the value of one in the data written (bits that have the value of zero will not be change) ; addr 2-clear - zero will be written to all the bits that have the value of one in the data written (bits that have the value of zero will not be change); addr 3-ignore; read ignore from all addr except addr 00; inside order of the bits is: [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc; [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7] rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn; [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13] Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16] rst_pxp_rq_rd_wr; 31:17] reserved */ #define MISC_REG_RESET_REG_1 … #define MISC_REG_RESET_REG_2 … /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is shared with the driver resides */ #define MISC_REG_SHARED_MEM_ADDR … /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1'; the corresponding SPIO bit will turn off it's drivers and become an input. This is the reset state of all SPIO pins. The read value of these bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits is written as a '1'; the corresponding SPIO bit will drive low. The read value of these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of these bits is written as a '1'; the corresponding SPIO bit will drive high (if it has that capability). The read value of these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET. (reset value 0). [7-0] VALUE RO; These bits indicate the read value of each of the eight SPIO pins. This is the result value of the pin; not the drive value. Writing these bits will have not effect. Each 8 bits field is divided as follows: [0] VAUX Enable; when pulsed low; enables supply from VAUX. (This is an output pin only; the FLOAT field is not applicable for this pin); [1] VAUX Disable; when pulsed low; disables supply form VAUX. (This is an output pin only; FLOAT field is not applicable for this pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to select VAUX supply. (This is an output pin only; it is not controlled by the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT field is not applicable for this pin; only the VALUE fields is relevant - it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6] Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP device ID select; read by UMP firmware. */ #define MISC_REG_SPIO … /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC. according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5; [7:0] reserved */ #define MISC_REG_SPIO_EVENT_EN … /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the corresponding bit in the #OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding SPIO input (reset value 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE RO; These bits indicate the old value of the SPIO input value. When the ~INT_STATE bit is set; this bit indicates the OLD value of the pin such that if ~INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE RO; These bits indicate the current SPIO interrupt state for each SPIO pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is set when the SPIO input does not match the current value in #OLD_VALUE (reset value 0). */ #define MISC_REG_SPIO_INT … /* [RW 32] reload value for counter 4 if reload; the value will be reload if the counter reached zero and the reload bit (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */ #define MISC_REG_SW_TIMER_RELOAD_VAL_4 … /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 - timer 8 */ #define MISC_REG_SW_TIMER_VAL … /* [R 1] Status of two port mode path swap input pin. */ #define MISC_REG_TWO_PORT_PATH_SWAP … /* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the path_swap output is equal to 2 port mode path swap input pin; if it is 1 - the path_swap output is equal to bit[1] of this register; [1] - Overwrite value. If bit[0] of this register is 1 this is the value that receives the path_swap output. Reset on Hard reset. */ #define MISC_REG_TWO_PORT_PATH_SWAP_OVWR … /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare; -unprepare */ #define MISC_REG_UNPREPARED … #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST … #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST … #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN … #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST … #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN … /* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or * not it is the recipient of the message on the MDIO interface. The value * is compared to the value on ctrl_md_devad. Drives output * misc_xgxs0_phy_addr. Global register. */ #define MISC_REG_WC0_CTRL_PHY_ADDR … #define MISC_REG_WC0_RESET … /* [RW 2] XMAC Core port mode. Indicates the number of ports on the system side. This should be less than or equal to phy_port_mode; if some of the ports are not used. This enables reduction of frequency on the core side. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap input for the XMAC_MP core; and should be changed only while reset is held low. Reset on Hard reset. */ #define MISC_REG_XMAC_CORE_PORT_MODE … /* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the XMAC_MP core; and should be changed only while reset is held low. Reset on Hard reset. */ #define MISC_REG_XMAC_PHY_PORT_MODE … /* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0. * Reads from this register will clear bits 31:0. */ #define MSTAT_REG_RX_STAT_GR64_LO … /* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits * 31:0. Reads from this register will clear bits 31:0. */ #define MSTAT_REG_TX_STAT_GTXPOK_LO … #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST … #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST … #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN … #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST … #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN … #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN … #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN … #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT … #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS … #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G … #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS … /* [RW 1] Input enable for RX_BMAC0 IF */ #define NIG_REG_BMAC0_IN_EN … /* [RW 1] output enable for TX_BMAC0 IF */ #define NIG_REG_BMAC0_OUT_EN … /* [RW 1] output enable for TX BMAC pause port 0 IF */ #define NIG_REG_BMAC0_PAUSE_OUT_EN … /* [RW 1] output enable for RX_BMAC0_REGS IF */ #define NIG_REG_BMAC0_REGS_OUT_EN … /* [RW 1] output enable for RX BRB1 port0 IF */ #define NIG_REG_BRB0_OUT_EN … /* [RW 1] Input enable for TX BRB1 pause port 0 IF */ #define NIG_REG_BRB0_PAUSE_IN_EN … /* [RW 1] output enable for RX BRB1 port1 IF */ #define NIG_REG_BRB1_OUT_EN … /* [RW 1] Input enable for TX BRB1 pause port 1 IF */ #define NIG_REG_BRB1_PAUSE_IN_EN … /* [RW 1] output enable for RX BRB1 LP IF */ #define NIG_REG_BRB_LB_OUT_EN … /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64] error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush; 72:73]-vnic_num; 81:74]-sideband_info */ #define NIG_REG_DEBUG_PACKET_LB … /* [RW 1] Input enable for TX Debug packet */ #define NIG_REG_EGRESS_DEBUG_IN_EN … /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all packets from PBFare not forwarded to the MAC and just deleted from FIFO. First packet may be deleted from the middle. And last packet will be always deleted till the end. */ #define NIG_REG_EGRESS_DRAIN0_MODE … /* [RW 1] Output enable to EMAC0 */ #define NIG_REG_EGRESS_EMAC0_OUT_EN … /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs to emac for port0; other way to bmac for port0 */ #define NIG_REG_EGRESS_EMAC0_PORT … /* [RW 1] Input enable for TX PBF user packet port0 IF */ #define NIG_REG_EGRESS_PBF0_IN_EN … /* [RW 1] Input enable for TX PBF user packet port1 IF */ #define NIG_REG_EGRESS_PBF1_IN_EN … /* [RW 1] Input enable for TX UMP management packet port0 IF */ #define NIG_REG_EGRESS_UMP0_IN_EN … /* [RW 1] Input enable for RX_EMAC0 IF */ #define NIG_REG_EMAC0_IN_EN … /* [RW 1] output enable for TX EMAC pause port 0 IF */ #define NIG_REG_EMAC0_PAUSE_OUT_EN … /* [R 1] status from emac0. This bit is set when MDINT from either the EXT_MDINT pin or from the Copper PHY is driven low. This condition must be cleared in the attached PHY device that is driving the MINT pin. */ #define NIG_REG_EMAC0_STATUS_MISC_MI_INT … /* [WB 48] This address space contains BMAC0 registers. The BMAC registers are described in appendix A. In order to access the BMAC0 registers; the base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be added to each BMAC register offset */ #define NIG_REG_INGRESS_BMAC0_MEM … /* [WB 48] This address space contains BMAC1 registers. The BMAC registers are described in appendix A. In order to access the BMAC0 registers; the base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be added to each BMAC register offset */ #define NIG_REG_INGRESS_BMAC1_MEM … /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */ #define NIG_REG_INGRESS_EOP_LB_EMPTY … /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */ #define NIG_REG_INGRESS_EOP_LB_FIFO … /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch logic for interrupts must be used. Enable per bit of interrupt of ~latch_status.latch_status */ #define NIG_REG_LATCH_BC_0 … /* [RW 27] Latch for each interrupt from Unicore.b[0] status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete; b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status; b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn; b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete; b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status; b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete; b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet; b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g; b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact; b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx; b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx; b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */ #define NIG_REG_LATCH_STATUS_0 … /* [RW 1] led 10g for port 0 */ #define NIG_REG_LED_10G_P0 … /* [RW 1] led 10g for port 1 */ #define NIG_REG_LED_10G_P1 … /* [RW 1] Port0: This bit is set to enable the use of the ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field defined below. If this bit is cleared; then the blink rate will be about 8Hz. */ #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 … /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field is reset to 0x080; giving a default blink period of approximately 8Hz. */ #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 … /* [RW 1] Port0: If set along with the ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED bit; the Traffic LED will blink with the blink rate specified in ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 fields. */ #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 … /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The Traffic LED will then be controlled via bit ~nig_registers_ led_control_traffic_p0.led_control_traffic_p0 and bit ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */ #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 … /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit; turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also set; the LED will blink with blink rate specified in ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 fields. */ #define NIG_REG_LED_CONTROL_TRAFFIC_P0 … /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3; 9-11PHY7; 12 MAC4; 13-15 PHY10; */ #define NIG_REG_LED_MODE_P0 … /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1- tsdm enable; b2- usdm enable */ #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 … #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 … /* [RW 1] SAFC enable for port0. This register may get 1 only when ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same port */ #define NIG_REG_LLFC_ENABLE_0 … #define NIG_REG_LLFC_ENABLE_1 … /* [RW 16] classes are high-priority for port0 */ #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 … #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 … /* [RW 16] classes are low-priority for port0 */ #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 … #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 … /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */ #define NIG_REG_LLFC_OUT_EN_0 … #define NIG_REG_LLFC_OUT_EN_1 … #define NIG_REG_LLH0_ACPI_PAT_0_CRC … #define NIG_REG_LLH0_ACPI_PAT_6_LEN … #define NIG_REG_LLH0_BRB1_DRV_MASK … #define NIG_REG_LLH0_BRB1_DRV_MASK_MF … /* [RW 1] send to BRB1 if no match on any of RMP rules. */ #define NIG_REG_LLH0_BRB1_NOT_MCP … /* [RW 2] Determine the classification participants. 0: no classification.1: classification upon VLAN id. 2: classification upon MAC address. 3: classification upon both VLAN id & MAC addr. */ #define NIG_REG_LLH0_CLS_TYPE … /* [RW 32] cm header for llh0 */ #define NIG_REG_LLH0_CM_HEADER … #define NIG_REG_LLH0_DEST_IP_0_1 … #define NIG_REG_LLH0_DEST_MAC_0_0 … /* [RW 16] destination TCP address 1. The LLH will look for this address in all incoming packets. */ #define NIG_REG_LLH0_DEST_TCP_0 … /* [RW 16] destination UDP address 1 The LLH will look for this address in all incoming packets. */ #define NIG_REG_LLH0_DEST_UDP_0 … #define NIG_REG_LLH0_ERROR_MASK … /* [RW 8] event id for llh0 */ #define NIG_REG_LLH0_EVENT_ID … #define NIG_REG_LLH0_FUNC_EN … #define NIG_REG_LLH0_FUNC_MEM … #define NIG_REG_LLH0_FUNC_MEM_ENABLE … #define NIG_REG_LLH0_FUNC_VLAN_ID … /* [RW 1] Determine the IP version to look for in ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */ #define NIG_REG_LLH0_IPV4_IPV6_0 … /* [RW 1] t bit for llh0 */ #define NIG_REG_LLH0_T_BIT … /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */ #define NIG_REG_LLH0_VLAN_ID_0 … /* [RW 8] init credit counter for port0 in LLH */ #define NIG_REG_LLH0_XCM_INIT_CREDIT … #define NIG_REG_LLH0_XCM_MASK … #define NIG_REG_LLH1_BRB1_DRV_MASK … /* [RW 1] send to BRB1 if no match on any of RMP rules. */ #define NIG_REG_LLH1_BRB1_NOT_MCP … /* [RW 2] Determine the classification participants. 0: no classification.1: classification upon VLAN id. 2: classification upon MAC address. 3: classification upon both VLAN id & MAC addr. */ #define NIG_REG_LLH1_CLS_TYPE … /* [RW 32] cm header for llh1 */ #define NIG_REG_LLH1_CM_HEADER … #define NIG_REG_LLH1_ERROR_MASK … /* [RW 8] event id for llh1 */ #define NIG_REG_LLH1_EVENT_ID … #define NIG_REG_LLH1_FUNC_EN … #define NIG_REG_LLH1_FUNC_MEM … #define NIG_REG_LLH1_FUNC_MEM_ENABLE … #define NIG_REG_LLH1_FUNC_MEM_SIZE … /* [RW 1] When this bit is set; the LLH will classify the packet before * sending it to the BRB or calculating WoL on it. This bit controls port 1 * only. The legacy llh_multi_function_mode bit controls port 0. */ #define NIG_REG_LLH1_MF_MODE … /* [RW 8] init credit counter for port1 in LLH */ #define NIG_REG_LLH1_XCM_INIT_CREDIT … #define NIG_REG_LLH1_XCM_MASK … /* [RW 1] When this bit is set; the LLH will expect all packets to be with e1hov */ #define NIG_REG_LLH_E1HOV_MODE … /* [RW 16] Outer VLAN type identifier for multi-function mode. In non * multi-function mode; it will hold the inner VLAN type. Typically 0x8100. */ #define NIG_REG_LLH_E1HOV_TYPE_1 … /* [RW 1] When this bit is set; the LLH will classify the packet before sending it to the BRB or calculating WoL on it. */ #define NIG_REG_LLH_MF_MODE … #define NIG_REG_MASK_INTERRUPT_PORT0 … #define NIG_REG_MASK_INTERRUPT_PORT1 … /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */ #define NIG_REG_NIG_EMAC0_EN … /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */ #define NIG_REG_NIG_EMAC1_EN … /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the EMAC0 to strip the CRC from the ingress packets. */ #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC … /* [R 32] Interrupt register #0 read */ #define NIG_REG_NIG_INT_STS_0 … #define NIG_REG_NIG_INT_STS_1 … /* [RC 32] Interrupt register #0 read clear */ #define NIG_REG_NIG_INT_STS_CLR_0 … /* [R 32] Legacy E1 and E1H location for parity error mask register. */ #define NIG_REG_NIG_PRTY_MASK … /* [RW 32] Parity mask register #0 read/write */ #define NIG_REG_NIG_PRTY_MASK_0 … #define NIG_REG_NIG_PRTY_MASK_1 … /* [R 32] Legacy E1 and E1H location for parity error status register. */ #define NIG_REG_NIG_PRTY_STS … /* [R 32] Parity register #0 read */ #define NIG_REG_NIG_PRTY_STS_0 … #define NIG_REG_NIG_PRTY_STS_1 … /* [R 32] Legacy E1 and E1H location for parity error status clear register. */ #define NIG_REG_NIG_PRTY_STS_CLR … /* [RC 32] Parity register #0 read clear */ #define NIG_REG_NIG_PRTY_STS_CLR_0 … #define NIG_REG_NIG_PRTY_STS_CLR_1 … #define MCPR_IMC_COMMAND_ENABLE … #define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT … #define MCPR_IMC_COMMAND_OPERATION_BITSHIFT … #define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT … /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic * Ethernet header. */ #define NIG_REG_P0_HDRS_AFTER_BASIC … /* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be * disabled when this bit is set. */ #define NIG_REG_P0_HWPFC_ENABLE … #define NIG_REG_P0_LLH_FUNC_MEM2 … #define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE … /* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for * the host. Bits [15:0] return the sequence ID of the packet. Bit 16 * indicates the validity of the data in the buffer. Writing a 1 to bit 16 * will clear the buffer. */ #define NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID … /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for * the host. This location returns the lower 32 bits of timestamp value. */ #define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB … /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for * the host. This location returns the upper 32 bits of timestamp value. */ #define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB … /* [RW 11] Mask register for the various parameters used in determining PTP * packet presence. Set each bit to 1 to mask out the particular parameter. * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable * MAC DA 2. The reset default is set to mask out all parameters. */ #define NIG_REG_P0_LLH_PTP_PARAM_MASK … /* [RW 14] Mask register for the rules used in detecting PTP packets. Set * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset * default is to mask out all of the rules. Note that rules 0-3 are for IPv4 * packets only and require that the packet is IPv4 for the rules to match. * Note that rules 4-7 are for IPv6 packets only and require that the packet * is IPv6 for the rules to match. */ #define NIG_REG_P0_LLH_PTP_RULE_MASK … /* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */ #define NIG_REG_P0_LLH_PTP_TO_HOST … /* [RW 1] Input enable for RX MAC interface. */ #define NIG_REG_P0_MAC_IN_EN … /* [RW 1] Output enable for TX MAC interface */ #define NIG_REG_P0_MAC_OUT_EN … /* [RW 1] Output enable for TX PAUSE signal to the MAC. */ #define NIG_REG_P0_MAC_PAUSE_OUT_EN … /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for * future expansion) each priorty is to be mapped to. Bits 3:0 specify the * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit * priority field is extracted from the outer-most VLAN in receive packet. * Only COS 0 and COS 1 are supported in E2. */ #define NIG_REG_P0_PKT_PRIORITY_TO_COS … /* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables * V1 frame format in timesync event detection on RX side. Bit 2 enables V2 * frame format in timesync event detection on RX side. Bit 3 enables * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event * detection on TX side. Bit 5 enables V2 frame format in timesync event * detection on TX side. Note that for HW to detect PTP packet and extract * data from the packet, at least one of the version bits of that traffic * direction has to be enabled. */ #define NIG_REG_P0_PTP_EN … /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A * priority is mapped to COS 0 when the corresponding mask bit is 1. More * than one bit may be set; allowing multiple priorities to be mapped to one * COS. */ #define NIG_REG_P0_RX_COS0_PRIORITY_MASK … /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A * priority is mapped to COS 1 when the corresponding mask bit is 1. More * than one bit may be set; allowing multiple priorities to be mapped to one * COS. */ #define NIG_REG_P0_RX_COS1_PRIORITY_MASK … /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A * priority is mapped to COS 2 when the corresponding mask bit is 1. More * than one bit may be set; allowing multiple priorities to be mapped to one * COS. */ #define NIG_REG_P0_RX_COS2_PRIORITY_MASK … /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A * priority is mapped to COS 3 when the corresponding mask bit is 1. More * than one bit may be set; allowing multiple priorities to be mapped to one * COS. */ #define NIG_REG_P0_RX_COS3_PRIORITY_MASK … /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A * priority is mapped to COS 4 when the corresponding mask bit is 1. More * than one bit may be set; allowing multiple priorities to be mapped to one * COS. */ #define NIG_REG_P0_RX_COS4_PRIORITY_MASK … /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A * priority is mapped to COS 5 when the corresponding mask bit is 1. More * than one bit may be set; allowing multiple priorities to be mapped to one * COS. */ #define NIG_REG_P0_RX_COS5_PRIORITY_MASK … /* [R 1] RX FIFO for receiving data from MAC is empty. */ /* [RW 15] Specify which of the credit registers the client is to be mapped * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For * clients that are not subject to WFQ credit blocking - their * specifications here are not used. */ #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP … /* [RW 32] Specify which of the credit registers the client is to be mapped * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are * for client 0; bits [35:32] are for client 8. For clients that are not * subject to WFQ credit blocking - their specifications here are not used. * This is a new register (with 2_) added in E3 B0 to accommodate the 9 * input clients to ETS arbiter. The reset default is set for management and * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to * use credit registers 0-5 respectively (0x543210876). Note that credit * registers can not be shared between clients. */ #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB … /* [RW 4] Specify which of the credit registers the client is to be mapped * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are * for client 0; bits [35:32] are for client 8. For clients that are not * subject to WFQ credit blocking - their specifications here are not used. * This is a new register (with 2_) added in E3 B0 to accommodate the 9 * input clients to ETS arbiter. The reset default is set for management and * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to * use credit registers 0-5 respectively (0x543210876). Note that credit * registers can not be shared between clients. */ #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB … /* [RW 5] Specify whether the client competes directly in the strict * priority arbiter. The bits are mapped according to client ID (client IDs * are defined in tx_arb_priority_client). Default value is set to enable * strict priorities for clients 0-2 -- management and debug traffic. */ #define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT … /* [RW 5] Specify whether the client is subject to WFQ credit blocking. The * bits are mapped according to client ID (client IDs are defined in * tx_arb_priority_client). Default value is 0 for not using WFQ credit * blocking. */ #define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ … /* [RW 32] Specify the upper bound that credit register 0 is allowed to * reach. */ #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 … #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 … #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 … #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 … #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 … #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 … #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 … #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 … #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 … /* [RW 32] Specify the weight (in bytes) to be added to credit register 0 * when it is time to increment. */ #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 … #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 … #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 … #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 … #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 … #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 … #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 … #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 … #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 … /* [RW 12] Specify the number of strict priority arbitration slots between * two round-robin arbitration slots to avoid starvation. A value of 0 means * no strict priority cycles - the strict priority with anti-starvation * arbiter becomes a round-robin arbiter. */ #define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS … /* [RW 15] Specify the client number to be assigned to each priority of the * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0] * are for priority 0 client; bits [14:12] are for priority 4 client. The * clients are assigned the following IDs: 0-management; 1-debug traffic * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000) * for management at priority 0; debug traffic at priorities 1 and 2; COS0 * traffic at priority 3; and COS1 traffic at priority 4. */ #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT … /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic * Ethernet header. */ #define NIG_REG_P1_HDRS_AFTER_BASIC … #define NIG_REG_P1_LLH_FUNC_MEM2 … #define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE … /* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for * the host. Bits [15:0] return the sequence ID of the packet. Bit 16 * indicates the validity of the data in the buffer. Writing a 1 to bit 16 * will clear the buffer. */ #define NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID … /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for * the host. This location returns the lower 32 bits of timestamp value. */ #define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB … /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for * the host. This location returns the upper 32 bits of timestamp value. */ #define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB … /* [RW 11] Mask register for the various parameters used in determining PTP * packet presence. Set each bit to 1 to mask out the particular parameter. * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable * MAC DA 2. The reset default is set to mask out all parameters. */ #define NIG_REG_P1_LLH_PTP_PARAM_MASK … /* [RW 14] Mask register for the rules used in detecting PTP packets. Set * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset * default is to mask out all of the rules. Note that rules 0-3 are for IPv4 * packets only and require that the packet is IPv4 for the rules to match. * Note that rules 4-7 are for IPv6 packets only and require that the packet * is IPv6 for the rules to match. */ #define NIG_REG_P1_LLH_PTP_RULE_MASK … /* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */ #define NIG_REG_P1_LLH_PTP_TO_HOST … /* [RW 32] Specify the client number to be assigned to each priority of the * strict priority arbiter. This register specifies bits 31:0 of the 36-bit * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 * client; bits [35-32] are for priority 8 client. The clients are assigned * the following IDs: 0-management; 1-debug traffic from this port; 2-debug * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to * accommodate the 9 input clients to ETS arbiter. */ #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB … /* [RW 4] Specify the client number to be assigned to each priority of the * strict priority arbiter. This register specifies bits 35:32 of the 36-bit * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 * client; bits [35-32] are for priority 8 client. The clients are assigned * the following IDs: 0-management; 1-debug traffic from this port; 2-debug * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to * accommodate the 9 input clients to ETS arbiter. */ #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB … /* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP * packets to BRB LB interface to forward the packet to the host. All * packets from MCP are forwarded to the network when this bit is cleared - * regardless of the configured destination in tx_mng_destination register. * When MCP-to-host paths for both ports 0 and 1 are disabled - the arbiter * for BRB LB interface is bypassed and PBF LB traffic is always selected to * send to BRB LB. */ #define NIG_REG_P0_TX_MNG_HOST_ENABLE … #define NIG_REG_P1_HWPFC_ENABLE … #define NIG_REG_P1_MAC_IN_EN … /* [RW 1] Output enable for TX MAC interface */ #define NIG_REG_P1_MAC_OUT_EN … /* [RW 1] Output enable for TX PAUSE signal to the MAC. */ #define NIG_REG_P1_MAC_PAUSE_OUT_EN … /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for * future expansion) each priorty is to be mapped to. Bits 3:0 specify the * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit * priority field is extracted from the outer-most VLAN in receive packet. * Only COS 0 and COS 1 are supported in E2. */ #define NIG_REG_P1_PKT_PRIORITY_TO_COS … /* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables * V1 frame format in timesync event detection on RX side. Bit 2 enables V2 * frame format in timesync event detection on RX side. Bit 3 enables * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event * detection on TX side. Bit 5 enables V2 frame format in timesync event * detection on TX side. Note that for HW to detect PTP packet and extract * data from the packet, at least one of the version bits of that traffic * direction has to be enabled. */ #define NIG_REG_P1_PTP_EN … /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A * priority is mapped to COS 0 when the corresponding mask bit is 1. More * than one bit may be set; allowing multiple priorities to be mapped to one * COS. */ #define NIG_REG_P1_RX_COS0_PRIORITY_MASK … /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A * priority is mapped to COS 1 when the corresponding mask bit is 1. More * than one bit may be set; allowing multiple priorities to be mapped to one * COS. */ #define NIG_REG_P1_RX_COS1_PRIORITY_MASK … /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A * priority is mapped to COS 2 when the corresponding mask bit is 1. More * than one bit may be set; allowing multiple priorities to be mapped to one * COS. */ #define NIG_REG_P1_RX_COS2_PRIORITY_MASK … /* [R 1] RX FIFO for receiving data from MAC is empty. */ #define NIG_REG_P1_RX_MACFIFO_EMPTY … /* [R 1] TLLH FIFO is empty. */ #define NIG_REG_P1_TLLH_FIFO_EMPTY … /* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16 * indicates the validity of the data in the buffer. Bit 17 indicates that * the sequence ID is valid and it is waiting for the TX timestamp value. * Bit 18 indicates whether the timestamp is from a SW request (value of 1) * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer. */ #define NIG_REG_P0_TLLH_PTP_BUF_SEQID … /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for * MCP. This location returns the lower 32 bits of timestamp value. */ #define NIG_REG_P0_TLLH_PTP_BUF_TS_LSB … /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for * MCP. This location returns the upper 32 bits of timestamp value. */ #define NIG_REG_P0_TLLH_PTP_BUF_TS_MSB … /* [RW 11] Mask register for the various parameters used in determining PTP * packet presence. Set each bit to 1 to mask out the particular parameter. * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable * MAC DA 2. The reset default is set to mask out all parameters. */ #define NIG_REG_P0_TLLH_PTP_PARAM_MASK … /* [RW 14] Mask register for the rules used in detecting PTP packets. Set * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset * default is to mask out all of the rules. */ #define NIG_REG_P0_TLLH_PTP_RULE_MASK … /* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16 * indicates the validity of the data in the buffer. Bit 17 indicates that * the sequence ID is valid and it is waiting for the TX timestamp value. * Bit 18 indicates whether the timestamp is from a SW request (value of 1) * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer. */ #define NIG_REG_P1_TLLH_PTP_BUF_SEQID … /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for * MCP. This location returns the lower 32 bits of timestamp value. */ #define NIG_REG_P1_TLLH_PTP_BUF_TS_LSB … /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for * MCP. This location returns the upper 32 bits of timestamp value. */ #define NIG_REG_P1_TLLH_PTP_BUF_TS_MSB … /* [RW 11] Mask register for the various parameters used in determining PTP * packet presence. Set each bit to 1 to mask out the particular parameter. * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable * MAC DA 2. The reset default is set to mask out all parameters. */ #define NIG_REG_P1_TLLH_PTP_PARAM_MASK … /* [RW 14] Mask register for the rules used in detecting PTP packets. Set * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset * default is to mask out all of the rules. */ #define NIG_REG_P1_TLLH_PTP_RULE_MASK … /* [RW 32] Specify which of the credit registers the client is to be mapped * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are * for client 0; bits [35:32] are for client 8. For clients that are not * subject to WFQ credit blocking - their specifications here are not used. * This is a new register (with 2_) added in E3 B0 to accommodate the 9 * input clients to ETS arbiter. The reset default is set for management and * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to * use credit registers 0-5 respectively (0x543210876). Note that credit * registers can not be shared between clients. Note also that there are * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only * credit registers 0-5 are valid. This register should be configured * appropriately before enabling WFQ. */ #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB … /* [RW 4] Specify which of the credit registers the client is to be mapped * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are * for client 0; bits [35:32] are for client 8. For clients that are not * subject to WFQ credit blocking - their specifications here are not used. * This is a new register (with 2_) added in E3 B0 to accommodate the 9 * input clients to ETS arbiter. The reset default is set for management and * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to * use credit registers 0-5 respectively (0x543210876). Note that credit * registers can not be shared between clients. Note also that there are * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only * credit registers 0-5 are valid. This register should be configured * appropriately before enabling WFQ. */ #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB … /* [RW 9] Specify whether the client competes directly in the strict * priority arbiter. The bits are mapped according to client ID (client IDs * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. * Default value is set to enable strict priorities for all clients. */ #define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT … /* [RW 9] Specify whether the client is subject to WFQ credit blocking. The * bits are mapped according to client ID (client IDs are defined in * tx_arb_priority_client2): 0-management; 1-debug traffic from this port; * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is * 0 for not using WFQ credit blocking. */ #define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ … #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 … #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 … #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 … #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 … #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 … #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 … /* [RW 32] Specify the weight (in bytes) to be added to credit register 0 * when it is time to increment. */ #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 … #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 … #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 … #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 … #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 … #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 … /* [RW 12] Specify the number of strict priority arbitration slots between two round-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the strict priority with anti-starvation arbiter becomes a round-robin arbiter. */ #define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS … /* [RW 32] Specify the client number to be assigned to each priority of the strict priority arbiter. This register specifies bits 31:0 of the 36-bit value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 client; bits [35-32] are for priority 8 client. The clients are assigned the following IDs: 0-management; 1-debug traffic from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is set to 0x345678021. This is a new register (with 2_) added in E3 B0 to accommodate the 9 input clients to ETS arbiter. Note that this register is the same as the one for port 0, except that port 1 only has COS 0-2 traffic. There is no traffic for COS 3-5 of port 1. */ #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB … /* [RW 4] Specify the client number to be assigned to each priority of the strict priority arbiter. This register specifies bits 35:32 of the 36-bit value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 client; bits [35-32] are for priority 8 client. The clients are assigned the following IDs: 0-management; 1-debug traffic from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is set to 0x345678021. This is a new register (with 2_) added in E3 B0 to accommodate the 9 input clients to ETS arbiter. Note that this register is the same as the one for port 0, except that port 1 only has COS 0-2 traffic. There is no traffic for COS 3-5 of port 1. */ #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB … /* [R 1] TX FIFO for transmitting data to MAC is empty. */ #define NIG_REG_P1_TX_MACFIFO_EMPTY … /* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP * packets to BRB LB interface to forward the packet to the host. All * packets from MCP are forwarded to the network when this bit is cleared - * regardless of the configured destination in tx_mng_destination register. */ #define NIG_REG_P1_TX_MNG_HOST_ENABLE … /* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets forwarded to the host. */ #define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY … /* [RW 32] Specify the upper bound that credit register 0 is allowed to * reach. */ /* [RW 1] Pause enable for port0. This register may get 1 only when ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same port */ #define NIG_REG_PAUSE_ENABLE_0 … #define NIG_REG_PAUSE_ENABLE_1 … /* [RW 1] Input enable for RX PBF LP IF */ #define NIG_REG_PBF_LB_IN_EN … /* [RW 1] Value of this register will be transmitted to port swap when ~nig_registers_strap_override.strap_override =1 */ #define NIG_REG_PORT_SWAP … /* [RW 1] PPP enable for port0. This register may get 1 only when * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the * same port */ #define NIG_REG_PPP_ENABLE_0 … #define NIG_REG_PPP_ENABLE_1 … /* [RW 1] output enable for RX parser descriptor IF */ #define NIG_REG_PRS_EOP_OUT_EN … /* [RW 1] Input enable for RX parser request IF */ #define NIG_REG_PRS_REQ_IN_EN … /* [RW 5] control to serdes - CL45 DEVAD */ #define NIG_REG_SERDES0_CTRL_MD_DEVAD … /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */ #define NIG_REG_SERDES0_CTRL_MD_ST … /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */ #define NIG_REG_SERDES0_CTRL_PHY_ADDR … /* [R 1] status from serdes0 that inputs to interrupt logic of link status */ #define NIG_REG_SERDES0_STATUS_LINK_STATUS … /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure for port0 */ #define NIG_REG_STAT0_BRB_DISCARD … /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure for port0 */ #define NIG_REG_STAT0_BRB_TRUNCATE … /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that between 1024 and 1522 bytes for port0 */ #define NIG_REG_STAT0_EGRESS_MAC_PKT0 … /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that between 1523 bytes and above for port0 */ #define NIG_REG_STAT0_EGRESS_MAC_PKT1 … /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure for port1 */ #define NIG_REG_STAT1_BRB_DISCARD … /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that between 1024 and 1522 bytes for port1 */ #define NIG_REG_STAT1_EGRESS_MAC_PKT0 … /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that between 1523 bytes and above for port1 */ #define NIG_REG_STAT1_EGRESS_MAC_PKT1 … /* [WB_R 64] Rx statistics : User octets received for LP */ #define NIG_REG_STAT2_BRB_OCTET … #define NIG_REG_STATUS_INTERRUPT_PORT0 … #define NIG_REG_STATUS_INTERRUPT_PORT1 … /* [RW 1] port swap mux selection. If this register equal to 0 then port swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then ort swap is equal to ~nig_registers_port_swap.port_swap */ #define NIG_REG_STRAP_OVERRIDE … /* [WB 64] Addresses for TimeSync related registers in the timesync * generator sub-module. */ #define NIG_REG_TIMESYNC_GEN_REG … /* [RW 1] output enable for RX_XCM0 IF */ #define NIG_REG_XCM0_OUT_EN … /* [RW 1] output enable for RX_XCM1 IF */ #define NIG_REG_XCM1_OUT_EN … /* [RW 1] control to xgxs - remote PHY in-band MDIO */ #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST … /* [RW 5] control to xgxs - CL45 DEVAD */ #define NIG_REG_XGXS0_CTRL_MD_DEVAD … /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */ #define NIG_REG_XGXS0_CTRL_MD_ST … /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */ #define NIG_REG_XGXS0_CTRL_PHY_ADDR … /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */ #define NIG_REG_XGXS0_STATUS_LINK10G … /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */ #define NIG_REG_XGXS0_STATUS_LINK_STATUS … /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */ #define NIG_REG_XGXS_LANE_SEL_P0 … /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */ #define NIG_REG_XGXS_SERDES0_MODE_SEL … #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT … #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS … #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G … #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS … #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE … /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */ #define PBF_REG_COS0_UPPER_BOUND … /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter * of port 0. */ #define PBF_REG_COS0_UPPER_BOUND_P0 … /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter * of port 1. */ #define PBF_REG_COS0_UPPER_BOUND_P1 … /* [RW 31] The weight of COS0 in the ETS command arbiter. */ #define PBF_REG_COS0_WEIGHT … /* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */ #define PBF_REG_COS0_WEIGHT_P0 … /* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */ #define PBF_REG_COS0_WEIGHT_P1 … /* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */ #define PBF_REG_COS1_UPPER_BOUND … /* [RW 31] The weight of COS1 in the ETS command arbiter. */ #define PBF_REG_COS1_WEIGHT … /* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */ #define PBF_REG_COS1_WEIGHT_P0 … /* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */ #define PBF_REG_COS1_WEIGHT_P1 … /* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */ #define PBF_REG_COS2_WEIGHT_P0 … /* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */ #define PBF_REG_COS2_WEIGHT_P1 … /* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */ #define PBF_REG_COS3_WEIGHT_P0 … /* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */ #define PBF_REG_COS4_WEIGHT_P0 … /* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */ #define PBF_REG_COS5_WEIGHT_P0 … /* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte * lines. */ #define PBF_REG_CREDIT_LB_Q … /* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte * lines. */ #define PBF_REG_CREDIT_Q0 … /* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte * lines. */ #define PBF_REG_CREDIT_Q1 … /* [RW 1] Disable processing further tasks from port 0 (after ending the current task in process). */ #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 … /* [RW 1] Disable processing further tasks from port 1 (after ending the current task in process). */ #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 … /* [RW 1] Disable processing further tasks from port 4 (after ending the current task in process). */ #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 … #define PBF_REG_DISABLE_PF … #define PBF_REG_DISABLE_VF … /* [RW 18] For port 0: For each client that is subject to WFQ (the * corresponding bit is 1); indicates to which of the credit registers this * client is mapped. For clients which are not credit blocked; their mapping * is dont care. */ #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 … /* [RW 9] For port 1: For each client that is subject to WFQ (the * corresponding bit is 1); indicates to which of the credit registers this * client is mapped. For clients which are not credit blocked; their mapping * is dont care. */ #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 … /* [RW 6] For port 0: Bit per client to indicate if the client competes in * the strict priority arbiter directly (corresponding bit = 1); or first * goes to the RR arbiter (corresponding bit = 0); and then competes in the * lowest priority in the strict-priority arbiter. */ #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 … /* [RW 3] For port 1: Bit per client to indicate if the client competes in * the strict priority arbiter directly (corresponding bit = 1); or first * goes to the RR arbiter (corresponding bit = 0); and then competes in the * lowest priority in the strict-priority arbiter. */ #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 … /* [RW 6] For port 0: Bit per client to indicate if the client is subject to * WFQ credit blocking (corresponding bit = 1). */ #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 … /* [RW 3] For port 0: Bit per client to indicate if the client is subject to * WFQ credit blocking (corresponding bit = 1). */ #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 … /* [RW 16] For port 0: The number of strict priority arbitration slots * between 2 RR arbitration slots. A value of 0 means no strict priority * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR * arbiter. */ #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 … /* [RW 16] For port 1: The number of strict priority arbitration slots * between 2 RR arbitration slots. A value of 0 means no strict priority * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR * arbiter. */ #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 … /* [RW 18] For port 0: Indicates which client is connected to each priority * in the strict-priority arbiter. Priority 0 is the highest priority, and * priority 5 is the lowest; to which the RR output is connected to (this is * not configurable). */ #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 … /* [RW 9] For port 1: Indicates which client is connected to each priority * in the strict-priority arbiter. Priority 0 is the highest priority, and * priority 5 is the lowest; to which the RR output is connected to (this is * not configurable). */ #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 … /* [RW 1] Indicates that ETS is performed between the COSes in the command * arbiter. If reset strict priority w/ anti-starvation will be performed * w/o WFQ. */ #define PBF_REG_ETS_ENABLED … /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic * Ethernet header. */ #define PBF_REG_HDRS_AFTER_BASIC … /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */ #define PBF_REG_HDRS_AFTER_TAG_0 … /* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest * priority in the command arbiter. */ #define PBF_REG_HIGH_PRIORITY_COS_NUM … #define PBF_REG_IF_ENABLE_REG … /* [RW 1] Init bit. When set the initial credits are copied to the credit registers (except the port credits). Should be set and then reset after the configuration of the block has ended. */ #define PBF_REG_INIT … /* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte * lines. */ #define PBF_REG_INIT_CRD_LB_Q … /* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte * lines. */ #define PBF_REG_INIT_CRD_Q0 … /* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte * lines. */ #define PBF_REG_INIT_CRD_Q1 … /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is copied to the credit register. Should be set and then reset after the configuration of the port has ended. */ #define PBF_REG_INIT_P0 … /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is copied to the credit register. Should be set and then reset after the configuration of the port has ended. */ #define PBF_REG_INIT_P1 … /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is copied to the credit register. Should be set and then reset after the configuration of the port has ended. */ #define PBF_REG_INIT_P4 … /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for * the LB queue. Reset upon init. */ #define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q … /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for * queue 0. Reset upon init. */ #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 … /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for * queue 1. Reset upon init. */ #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 … /* [RW 1] Enable for mac interface 0. */ #define PBF_REG_MAC_IF0_ENABLE … /* [RW 1] Enable for mac interface 1. */ #define PBF_REG_MAC_IF1_ENABLE … /* [RW 1] Enable for the loopback interface. */ #define PBF_REG_MAC_LB_ENABLE … /* [RW 6] Bit-map indicating which headers must appear in the packet */ #define PBF_REG_MUST_HAVE_HDRS … /* [RW 16] The number of strict priority arbitration slots between 2 RR * arbitration slots. A value of 0 means no strict priority cycles; i.e. the * strict-priority w/ anti-starvation arbiter is a RR arbiter. */ #define PBF_REG_NUM_STRICT_ARB_SLOTS … /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause not suppoterd. */ #define PBF_REG_P0_ARB_THRSH … /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */ #define PBF_REG_P0_CREDIT … /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte lines. */ #define PBF_REG_P0_INIT_CRD … /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for * port 0. Reset upon init. */ #define PBF_REG_P0_INTERNAL_CRD_FREED_CNT … /* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */ #define PBF_REG_P0_PAUSE_ENABLE … /* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */ #define PBF_REG_P0_TASK_CNT … /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines * freed from the task queue of port 0. Reset upon init. */ #define PBF_REG_P0_TQ_LINES_FREED_CNT … /* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */ #define PBF_REG_P0_TQ_OCCUPANCY … /* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port * buffers in 16 byte lines. */ #define PBF_REG_P1_CREDIT … /* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port * buffers in 16 byte lines. */ #define PBF_REG_P1_INIT_CRD … /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for * port 1. Reset upon init. */ #define PBF_REG_P1_INTERNAL_CRD_FREED_CNT … /* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */ #define PBF_REG_P1_TASK_CNT … /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines * freed from the task queue of port 1. Reset upon init. */ #define PBF_REG_P1_TQ_LINES_FREED_CNT … /* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */ #define PBF_REG_P1_TQ_OCCUPANCY … /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */ #define PBF_REG_P4_CREDIT … /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte lines. */ #define PBF_REG_P4_INIT_CRD … /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for * port 4. Reset upon init. */ #define PBF_REG_P4_INTERNAL_CRD_FREED_CNT … /* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */ #define PBF_REG_P4_TASK_CNT … /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines * freed from the task queue of port 4. Reset upon init. */ #define PBF_REG_P4_TQ_LINES_FREED_CNT … /* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */ #define PBF_REG_P4_TQ_OCCUPANCY … /* [RW 5] Interrupt mask register #0 read/write */ #define PBF_REG_PBF_INT_MASK … /* [R 5] Interrupt register #0 read */ #define PBF_REG_PBF_INT_STS … /* [RW 20] Parity mask register #0 read/write */ #define PBF_REG_PBF_PRTY_MASK … /* [R 28] Parity register #0 read */ #define PBF_REG_PBF_PRTY_STS … /* [RC 20] Parity register #0 read clear */ #define PBF_REG_PBF_PRTY_STS_CLR … /* [RW 16] The Ethernet type value for L2 tag 0 */ #define PBF_REG_TAG_ETHERTYPE_0 … /* [RW 4] The length of the info field for L2 tag 0. The length is between * 2B and 14B; in 2B granularity */ #define PBF_REG_TAG_LEN_0 … /* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task * queue. Reset upon init. */ #define PBF_REG_TQ_LINES_FREED_CNT_LB_Q … /* [R 32] Cyclic counter for number of 8 byte lines freed from the task * queue 0. Reset upon init. */ #define PBF_REG_TQ_LINES_FREED_CNT_Q0 … /* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1. * Reset upon init. */ #define PBF_REG_TQ_LINES_FREED_CNT_Q1 … /* [R 13] Number of 8 bytes lines occupied in the task queue of the LB * queue. */ #define PBF_REG_TQ_OCCUPANCY_LB_Q … /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */ #define PBF_REG_TQ_OCCUPANCY_Q0 … /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */ #define PBF_REG_TQ_OCCUPANCY_Q1 … /* [RW 16] One of 8 values that should be compared to type in Ethernet * parsing. If there is a match; the field after Ethernet is the first VLAN. * Reset value is 0x8100 which is the standard VLAN type. Note that when * checking second VLAN; type is compared only to 0x8100. */ #define PBF_REG_VLAN_TYPE_0 … /* [RW 2] Interrupt mask register #0 read/write */ #define PB_REG_PB_INT_MASK … /* [R 2] Interrupt register #0 read */ #define PB_REG_PB_INT_STS … /* [RW 4] Parity mask register #0 read/write */ #define PB_REG_PB_PRTY_MASK … /* [R 4] Parity register #0 read */ #define PB_REG_PB_PRTY_STS … /* [RC 4] Parity register #0 read clear */ #define PB_REG_PB_PRTY_STS_CLR … #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR … #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW … #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR … #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN … #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN … #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN … #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN … #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN … #define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN … /* [R 8] Config space A attention dirty bits. Each bit indicates that the * corresponding PF generates config space A attention. Set by PXP. Reset by * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits * from both paths. */ #define PGLUE_B_REG_CFG_SPACE_A_REQUEST … /* [R 8] Config space B attention dirty bits. Each bit indicates that the * corresponding PF generates config space B attention. Set by PXP. Reset by * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits * from both paths. */ #define PGLUE_B_REG_CFG_SPACE_B_REQUEST … /* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1 * - enable. */ #define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE … /* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask; * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */ #define PGLUE_B_REG_CSDM_INB_INT_B_VF … /* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1 * - enable. */ #define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE … /* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */ #define PGLUE_B_REG_CSDM_START_OFFSET_A … /* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */ #define PGLUE_B_REG_CSDM_START_OFFSET_B … /* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */ #define PGLUE_B_REG_CSDM_VF_SHIFT_B … /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ #define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF … /* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates * that the FLR register of the corresponding PF was set. Set by PXP. Reset * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits * from both paths. */ #define PGLUE_B_REG_FLR_REQUEST_PF_7_0 … /* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1 * to a bit in this register in order to clear the corresponding bit in * flr_request_pf_7_0 register. Note: register contains bits from both * paths. */ #define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR … /* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit * indicates that the FLR register of the corresponding VF was set. Set by * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */ #define PGLUE_B_REG_FLR_REQUEST_VF_127_96 … /* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit * indicates that the FLR register of the corresponding VF was set. Set by * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */ #define PGLUE_B_REG_FLR_REQUEST_VF_31_0 … /* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit * indicates that the FLR register of the corresponding VF was set. Set by * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */ #define PGLUE_B_REG_FLR_REQUEST_VF_63_32 … /* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit * indicates that the FLR register of the corresponding VF was set. Set by * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */ #define PGLUE_B_REG_FLR_REQUEST_VF_95_64 … /* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit * 0 - Target memory read arrived with a correctable error. Bit 1 - Target * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW * arrived with a correctable error. Bit 3 - Configuration RW arrived with * an uncorrectable error. Bit 4 - Completion with Configuration Request * Retry Status. Bit 5 - Expansion ROM access received with a write request. * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010; * and pcie_rx_last not asserted. */ #define PGLUE_B_REG_INCORRECT_RCV_DETAILS … #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER … #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ … #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE … #define PGLUE_B_REG_INTERNAL_VFID_ENABLE … /* [W 7] Writing 1 to each bit in this register clears a corresponding error * details register and enables logging new error details. Bit 0 - clears * INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears * TX_ERR_WR_ADD_31_0 TX_ERR_WR_ADD_63_32 TX_ERR_WR_DETAILS * TX_ERR_WR_DETAILS2 TX_ERR_RD_ADD_31_0 TX_ERR_RD_ADD_63_32 * TX_ERR_RD_DETAILS TX_ERR_RD_DETAILS2 TX_ERR_WR_DETAILS_ICPL; Bit 3 - * clears VF_LENGTH_VIOLATION_DETAILS. Bit 4 - clears * VF_GRC_SPACE_VIOLATION_DETAILS. Bit 5 - clears RX_TCPL_ERR_DETAILS. Bit 6 * - clears TCPL_IN_TWO_RCBS_DETAILS. */ #define PGLUE_B_REG_LATCHED_ERRORS_CLR … /* [R 9] Interrupt register #0 read */ #define PGLUE_B_REG_PGLUE_B_INT_STS … /* [RC 9] Interrupt register #0 read clear */ #define PGLUE_B_REG_PGLUE_B_INT_STS_CLR … /* [RW 2] Parity mask register #0 read/write */ #define PGLUE_B_REG_PGLUE_B_PRTY_MASK … /* [R 2] Parity register #0 read */ #define PGLUE_B_REG_PGLUE_B_PRTY_STS … /* [RC 2] Parity register #0 read clear */ #define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR … /* [R 13] Details of first request received with error. [2:0] - PFID. [3] - * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 - * completer abort. 3 - Illegal value for this field. [12] valid - indicates * if there was a completion error since the last time this register was * cleared. */ #define PGLUE_B_REG_RX_ERR_DETAILS … /* [R 18] Details of first ATS Translation Completion request received with * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code - * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 - * unsupported request. 2 - completer abort. 3 - Illegal value for this * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a * completion error since the last time this register was cleared. */ #define PGLUE_B_REG_RX_TCPL_ERR_DETAILS … /* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to * a bit in this register in order to clear the corresponding bit in * shadow_bme_pf_7_0 register. MCP should never use this unless a * work-around is needed. Note: register contains bits from both paths. */ #define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR … /* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the * VF enable register of the corresponding PF is written to 0 and was * previously 1. Set by PXP. Reset by MCP writing 1 to * sr_iov_disabled_request_clr. Note: register contains bits from both * paths. */ #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST … /* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read * completion did not return yet. 1 - tag is unused. Same functionality as * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */ #define PGLUE_B_REG_TAGS_63_32 … /* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1 * - enable. */ #define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE … /* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */ #define PGLUE_B_REG_TSDM_START_OFFSET_A … /* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */ #define PGLUE_B_REG_TSDM_START_OFFSET_B … /* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */ #define PGLUE_B_REG_TSDM_VF_SHIFT_B … /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ #define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF … /* [R 32] Address [31:0] of first read request not submitted due to error */ #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 … /* [R 32] Address [63:32] of first read request not submitted due to error */ #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 … /* [R 31] Details of first read request not submitted due to error. [4:0] * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] - * VFID. */ #define PGLUE_B_REG_TX_ERR_RD_DETAILS … /* [R 26] Details of first read request not submitted due to error. [15:0] * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type - * [21] - Indicates was_error was set; [22] - Indicates BME was cleared; * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid - * indicates if there was a request not submitted due to error since the * last time this register was cleared. */ #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 … /* [R 32] Address [31:0] of first write request not submitted due to error */ #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 … /* [R 32] Address [63:32] of first write request not submitted due to error */ #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 … /* [R 31] Details of first write request not submitted due to error. [4:0] * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] * - VFID. */ #define PGLUE_B_REG_TX_ERR_WR_DETAILS … /* [R 26] Details of first write request not submitted due to error. [15:0] * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type - * [21] - Indicates was_error was set; [22] - Indicates BME was cleared; * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid - * indicates if there was a request not submitted due to error since the * last time this register was cleared. */ #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 … /* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask; * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any * value (Byte resolution address). */ #define PGLUE_B_REG_USDM_INB_INT_A_0 … #define PGLUE_B_REG_USDM_INB_INT_A_1 … #define PGLUE_B_REG_USDM_INB_INT_A_2 … #define PGLUE_B_REG_USDM_INB_INT_A_3 … #define PGLUE_B_REG_USDM_INB_INT_A_4 … #define PGLUE_B_REG_USDM_INB_INT_A_5 … #define PGLUE_B_REG_USDM_INB_INT_A_6 … /* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1 * - enable. */ #define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE … /* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1 * - enable. */ #define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE … /* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1 * - enable. */ #define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE … /* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */ #define PGLUE_B_REG_USDM_START_OFFSET_A … /* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */ #define PGLUE_B_REG_USDM_START_OFFSET_B … /* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */ #define PGLUE_B_REG_USDM_VF_SHIFT_B … /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ #define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF … /* [R 26] Details of first target VF request accessing VF GRC space that * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write. * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a * request accessing VF GRC space that failed permission check since the * last time this register was cleared. Permission checks are: function * permission; R/W permission; address range permission. */ #define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS … /* [R 31] Details of first target VF request with length violation (too many * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address). * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30] * valid - indicates if there was a request with length violation since the * last time this register was cleared. Length violations: length of more * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and * length is more than 1 DW. */ #define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS … /* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates * that there was a completion with uncorrectable error for the * corresponding PF. Set by PXP. Reset by MCP writing 1 to * was_error_pf_7_0_clr. */ #define PGLUE_B_REG_WAS_ERROR_PF_7_0 … /* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1 * to a bit in this register in order to clear the corresponding bit in * flr_request_pf_7_0 register. */ #define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR … /* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit * indicates that there was a completion with uncorrectable error for the * corresponding VF. Set by PXP. Reset by MCP writing 1 to * was_error_vf_127_96_clr. */ #define PGLUE_B_REG_WAS_ERROR_VF_127_96 … /* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP * writes 1 to a bit in this register in order to clear the corresponding * bit in was_error_vf_127_96 register. */ #define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR … /* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit * indicates that there was a completion with uncorrectable error for the * corresponding VF. Set by PXP. Reset by MCP writing 1 to * was_error_vf_31_0_clr. */ #define PGLUE_B_REG_WAS_ERROR_VF_31_0 … /* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes * 1 to a bit in this register in order to clear the corresponding bit in * was_error_vf_31_0 register. */ #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR … /* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit * indicates that there was a completion with uncorrectable error for the * corresponding VF. Set by PXP. Reset by MCP writing 1 to * was_error_vf_63_32_clr. */ #define PGLUE_B_REG_WAS_ERROR_VF_63_32 … /* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes * 1 to a bit in this register in order to clear the corresponding bit in * was_error_vf_63_32 register. */ #define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR … /* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit * indicates that there was a completion with uncorrectable error for the * corresponding VF. Set by PXP. Reset by MCP writing 1 to * was_error_vf_95_64_clr. */ #define PGLUE_B_REG_WAS_ERROR_VF_95_64 … /* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes * 1 to a bit in this register in order to clear the corresponding bit in * was_error_vf_95_64 register. */ #define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR … /* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1 * - enable. */ #define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE … /* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */ #define PGLUE_B_REG_XSDM_START_OFFSET_A … /* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */ #define PGLUE_B_REG_XSDM_START_OFFSET_B … /* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */ #define PGLUE_B_REG_XSDM_VF_SHIFT_B … /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ #define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF … #define PRS_REG_A_PRSU_20 … /* [R 8] debug only: CFC load request current credit. Transaction based. */ #define PRS_REG_CFC_LD_CURRENT_CREDIT … /* [R 8] debug only: CFC search request current credit. Transaction based. */ #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT … /* [RW 6] The initial credit for the search message to the CFC interface. Credit is transaction based. */ #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT … /* [RW 24] CID for port 0 if no match */ #define PRS_REG_CID_PORT_0 … /* [RW 32] The CM header for flush message where 'load existed' bit in CFC load response is reset and packet type is 0. Used in packet start message to TCM. */ #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 … #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 … #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 … #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 … #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 … #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 … /* [RW 32] The CM header for flush message where 'load existed' bit in CFC load response is set and packet type is 0. Used in packet start message to TCM. */ #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 … #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 … #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 … #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 … #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 … #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 … /* [RW 32] The CM header for a match and packet type 1 for loopback port. Used in packet start message to TCM. */ #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 … #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 … #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 … #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 … /* [RW 32] The CM header for a match and packet type 0. Used in packet start message to TCM. */ #define PRS_REG_CM_HDR_TYPE_0 … #define PRS_REG_CM_HDR_TYPE_1 … #define PRS_REG_CM_HDR_TYPE_2 … #define PRS_REG_CM_HDR_TYPE_3 … #define PRS_REG_CM_HDR_TYPE_4 … /* [RW 32] The CM header in case there was not a match on the connection */ #define PRS_REG_CM_NO_MATCH_HDR … /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */ #define PRS_REG_E1HOV_MODE … /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet start message to TCM. */ #define PRS_REG_EVENT_ID_1 … #define PRS_REG_EVENT_ID_2 … #define PRS_REG_EVENT_ID_3 … /* [RW 16] The Ethernet type value for FCoE */ #define PRS_REG_FCOE_TYPE … /* [RW 8] Context region for flush packet with packet type 0. Used in CFC load request message. */ #define PRS_REG_FLUSH_REGIONS_TYPE_0 … #define PRS_REG_FLUSH_REGIONS_TYPE_1 … #define PRS_REG_FLUSH_REGIONS_TYPE_2 … #define PRS_REG_FLUSH_REGIONS_TYPE_3 … #define PRS_REG_FLUSH_REGIONS_TYPE_4 … #define PRS_REG_FLUSH_REGIONS_TYPE_5 … #define PRS_REG_FLUSH_REGIONS_TYPE_6 … #define PRS_REG_FLUSH_REGIONS_TYPE_7 … /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic * Ethernet header. */ #define PRS_REG_HDRS_AFTER_BASIC … /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic * Ethernet header for port 0 packets. */ #define PRS_REG_HDRS_AFTER_BASIC_PORT_0 … #define PRS_REG_HDRS_AFTER_BASIC_PORT_1 … /* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */ #define PRS_REG_HDRS_AFTER_TAG_0 … /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for * port 0 packets */ #define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 … #define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 … /* [RW 4] The increment value to send in the CFC load request message */ #define PRS_REG_INC_VALUE … /* [RW 6] Bit-map indicating which headers must appear in the packet */ #define PRS_REG_MUST_HAVE_HDRS … /* [RW 6] Bit-map indicating which headers must appear in the packet for * port 0 packets */ #define PRS_REG_MUST_HAVE_HDRS_PORT_0 … #define PRS_REG_MUST_HAVE_HDRS_PORT_1 … #define PRS_REG_NIC_MODE … /* [RW 8] The 8-bit event ID for cases where there is no match on the connection. Used in packet start message to TCM. */ #define PRS_REG_NO_MATCH_EVENT_ID … /* [ST 24] The number of input CFC flush packets */ #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES … /* [ST 32] The number of cycles the Parser halted its operation since it could not allocate the next serial number */ #define PRS_REG_NUM_OF_DEAD_CYCLES … /* [ST 24] The number of input packets */ #define PRS_REG_NUM_OF_PACKETS … /* [ST 24] The number of input transparent flush packets */ #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES … /* [RW 8] Context region for received Ethernet packet with a match and packet type 0. Used in CFC load request message */ #define PRS_REG_PACKET_REGIONS_TYPE_0 … #define PRS_REG_PACKET_REGIONS_TYPE_1 … #define PRS_REG_PACKET_REGIONS_TYPE_2 … #define PRS_REG_PACKET_REGIONS_TYPE_3 … #define PRS_REG_PACKET_REGIONS_TYPE_4 … #define PRS_REG_PACKET_REGIONS_TYPE_5 … #define PRS_REG_PACKET_REGIONS_TYPE_6 … #define PRS_REG_PACKET_REGIONS_TYPE_7 … /* [R 2] debug only: Number of pending requests for CAC on port 0. */ #define PRS_REG_PENDING_BRB_CAC0_RQ … /* [R 2] debug only: Number of pending requests for header parsing. */ #define PRS_REG_PENDING_BRB_PRS_RQ … /* [R 1] Interrupt register #0 read */ #define PRS_REG_PRS_INT_STS … /* [RW 8] Parity mask register #0 read/write */ #define PRS_REG_PRS_PRTY_MASK … /* [R 8] Parity register #0 read */ #define PRS_REG_PRS_PRTY_STS … /* [RC 8] Parity register #0 read clear */ #define PRS_REG_PRS_PRTY_STS_CLR … /* [RW 8] Context region for pure acknowledge packets. Used in CFC load request message */ #define PRS_REG_PURE_REGIONS … /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this serail number was released by SDM but cannot be used because a previous serial number was not released. */ #define PRS_REG_SERIAL_NUM_STATUS_LSB … /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this serail number was released by SDM but cannot be used because a previous serial number was not released. */ #define PRS_REG_SERIAL_NUM_STATUS_MSB … /* [R 4] debug only: SRC current credit. Transaction based. */ #define PRS_REG_SRC_CURRENT_CREDIT … /* [RW 16] The Ethernet type value for L2 tag 0 */ #define PRS_REG_TAG_ETHERTYPE_0 … /* [RW 4] The length of the info field for L2 tag 0. The length is between * 2B and 14B; in 2B granularity */ #define PRS_REG_TAG_LEN_0 … /* [R 8] debug only: TCM current credit. Cycle based. */ #define PRS_REG_TCM_CURRENT_CREDIT … /* [R 8] debug only: TSDM current credit. Transaction based. */ #define PRS_REG_TSDM_CURRENT_CREDIT … /* [RW 16] One of 8 values that should be compared to type in Ethernet * parsing. If there is a match; the field after Ethernet is the first VLAN. * Reset value is 0x8100 which is the standard VLAN type. Note that when * checking second VLAN; type is compared only to 0x8100. */ #define PRS_REG_VLAN_TYPE_0 … #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT … #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF … #define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN … #define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED … #define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED … #define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR … #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR … /* [R 6] Debug only: Number of used entries in the data FIFO */ #define PXP2_REG_HST_DATA_FIFO_STATUS … /* [R 7] Debug only: Number of used entries in the header FIFO */ #define PXP2_REG_HST_HEADER_FIFO_STATUS … #define PXP2_REG_PGL_ADDR_88_F0 … /* [R 32] GRC address for configuration access to PCIE config address 0x88. * any write to this PCIE address will cause a GRC write access to the * address that's in t this register */ #define PXP2_REG_PGL_ADDR_88_F1 … #define PXP2_REG_PGL_ADDR_8C_F0 … /* [R 32] GRC address for configuration access to PCIE config address 0x8c. * any write to this PCIE address will cause a GRC write access to the * address that's in t this register */ #define PXP2_REG_PGL_ADDR_8C_F1 … #define PXP2_REG_PGL_ADDR_90_F0 … /* [R 32] GRC address for configuration access to PCIE config address 0x90. * any write to this PCIE address will cause a GRC write access to the * address that's in t this register */ #define PXP2_REG_PGL_ADDR_90_F1 … #define PXP2_REG_PGL_ADDR_94_F0 … /* [R 32] GRC address for configuration access to PCIE config address 0x94. * any write to this PCIE address will cause a GRC write access to the * address that's in t this register */ #define PXP2_REG_PGL_ADDR_94_F1 … #define PXP2_REG_PGL_CONTROL0 … #define PXP2_REG_PGL_CONTROL1 … #define PXP2_REG_PGL_DEBUG … /* [RW 32] third dword data of expansion rom request. this register is special. reading from it provides a vector outstanding read requests. if a bit is zero it means that a read request on the corresponding tag did not finish yet (not all completions have arrived for it) */ #define PXP2_REG_PGL_EXP_ROM2 … /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask; its[15:0]-address */ #define PXP2_REG_PGL_INT_CSDM_0 … #define PXP2_REG_PGL_INT_CSDM_1 … #define PXP2_REG_PGL_INT_CSDM_2 … #define PXP2_REG_PGL_INT_CSDM_3 … #define PXP2_REG_PGL_INT_CSDM_4 … #define PXP2_REG_PGL_INT_CSDM_5 … #define PXP2_REG_PGL_INT_CSDM_6 … #define PXP2_REG_PGL_INT_CSDM_7 … /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask; its[15:0]-address */ #define PXP2_REG_PGL_INT_TSDM_0 … #define PXP2_REG_PGL_INT_TSDM_1 … #define PXP2_REG_PGL_INT_TSDM_2 … #define PXP2_REG_PGL_INT_TSDM_3 … #define PXP2_REG_PGL_INT_TSDM_4 … #define PXP2_REG_PGL_INT_TSDM_5 … #define PXP2_REG_PGL_INT_TSDM_6 … #define PXP2_REG_PGL_INT_TSDM_7 … /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask; its[15:0]-address */ #define PXP2_REG_PGL_INT_USDM_0 … #define PXP2_REG_PGL_INT_USDM_1 … #define PXP2_REG_PGL_INT_USDM_2 … #define PXP2_REG_PGL_INT_USDM_3 … #define PXP2_REG_PGL_INT_USDM_4 … #define PXP2_REG_PGL_INT_USDM_5 … #define PXP2_REG_PGL_INT_USDM_6 … #define PXP2_REG_PGL_INT_USDM_7 … /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask; its[15:0]-address */ #define PXP2_REG_PGL_INT_XSDM_0 … #define PXP2_REG_PGL_INT_XSDM_1 … #define PXP2_REG_PGL_INT_XSDM_2 … #define PXP2_REG_PGL_INT_XSDM_3 … #define PXP2_REG_PGL_INT_XSDM_4 … #define PXP2_REG_PGL_INT_XSDM_5 … #define PXP2_REG_PGL_INT_XSDM_6 … #define PXP2_REG_PGL_INT_XSDM_7 … /* [RW 3] this field allows one function to pretend being another function when accessing any BAR mapped resource within the device. the value of the field is the number of the function that will be accessed effectively. after software write to this bit it must read it in order to know that the new value is updated */ #define PXP2_REG_PGL_PRETEND_FUNC_F0 … #define PXP2_REG_PGL_PRETEND_FUNC_F1 … #define PXP2_REG_PGL_PRETEND_FUNC_F2 … #define PXP2_REG_PGL_PRETEND_FUNC_F3 … #define PXP2_REG_PGL_PRETEND_FUNC_F4 … #define PXP2_REG_PGL_PRETEND_FUNC_F5 … #define PXP2_REG_PGL_PRETEND_FUNC_F6 … #define PXP2_REG_PGL_PRETEND_FUNC_F7 … /* [R 1] this bit indicates that a read request was blocked because of bus_master_en was deasserted */ #define PXP2_REG_PGL_READ_BLOCKED … #define PXP2_REG_PGL_TAGS_LIMIT … /* [R 18] debug only */ #define PXP2_REG_PGL_TXW_CDTS … /* [R 1] this bit indicates that a write request was blocked because of bus_master_en was deasserted */ #define PXP2_REG_PGL_WRITE_BLOCKED … #define PXP2_REG_PSWRQ_BW_ADD1 … #define PXP2_REG_PSWRQ_BW_ADD10 … #define PXP2_REG_PSWRQ_BW_ADD11 … #define PXP2_REG_PSWRQ_BW_ADD2 … #define PXP2_REG_PSWRQ_BW_ADD28 … #define PXP2_REG_PSWRQ_BW_ADD3 … #define PXP2_REG_PSWRQ_BW_ADD6 … #define PXP2_REG_PSWRQ_BW_ADD7 … #define PXP2_REG_PSWRQ_BW_ADD8 … #define PXP2_REG_PSWRQ_BW_ADD9 … #define PXP2_REG_PSWRQ_BW_CREDIT … #define PXP2_REG_PSWRQ_BW_L1 … #define PXP2_REG_PSWRQ_BW_L10 … #define PXP2_REG_PSWRQ_BW_L11 … #define PXP2_REG_PSWRQ_BW_L2 … #define PXP2_REG_PSWRQ_BW_L28 … #define PXP2_REG_PSWRQ_BW_L3 … #define PXP2_REG_PSWRQ_BW_L6 … #define PXP2_REG_PSWRQ_BW_L7 … #define PXP2_REG_PSWRQ_BW_L8 … #define PXP2_REG_PSWRQ_BW_L9 … #define PXP2_REG_PSWRQ_BW_RD … #define PXP2_REG_PSWRQ_BW_UB1 … #define PXP2_REG_PSWRQ_BW_UB10 … #define PXP2_REG_PSWRQ_BW_UB11 … #define PXP2_REG_PSWRQ_BW_UB2 … #define PXP2_REG_PSWRQ_BW_UB28 … #define PXP2_REG_PSWRQ_BW_UB3 … #define PXP2_REG_PSWRQ_BW_UB6 … #define PXP2_REG_PSWRQ_BW_UB7 … #define PXP2_REG_PSWRQ_BW_UB8 … #define PXP2_REG_PSWRQ_BW_UB9 … #define PXP2_REG_PSWRQ_BW_WR … #define PXP2_REG_PSWRQ_CDU0_L2P … #define PXP2_REG_PSWRQ_QM0_L2P … #define PXP2_REG_PSWRQ_SRC0_L2P … #define PXP2_REG_PSWRQ_TM0_L2P … #define PXP2_REG_PSWRQ_TSDM0_L2P … /* [RW 32] Interrupt mask register #0 read/write */ #define PXP2_REG_PXP2_INT_MASK_0 … /* [R 32] Interrupt register #0 read */ #define PXP2_REG_PXP2_INT_STS_0 … #define PXP2_REG_PXP2_INT_STS_1 … /* [RC 32] Interrupt register #0 read clear */ #define PXP2_REG_PXP2_INT_STS_CLR_0 … /* [RW 32] Parity mask register #0 read/write */ #define PXP2_REG_PXP2_PRTY_MASK_0 … #define PXP2_REG_PXP2_PRTY_MASK_1 … /* [R 32] Parity register #0 read */ #define PXP2_REG_PXP2_PRTY_STS_0 … #define PXP2_REG_PXP2_PRTY_STS_1 … /* [RC 32] Parity register #0 read clear */ #define PXP2_REG_PXP2_PRTY_STS_CLR_0 … #define PXP2_REG_PXP2_PRTY_STS_CLR_1 … /* [R 1] Debug only: The 'almost full' indication from each fifo (gives indication about backpressure) */ #define PXP2_REG_RD_ALMOST_FULL_0 … /* [R 8] Debug only: The blocks counter - number of unused block ids */ #define PXP2_REG_RD_BLK_CNT … /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer. Must be bigger than 6. Normally should not be changed. */ #define PXP2_REG_RD_BLK_NUM_CFG … /* [RW 2] CDU byte swapping mode configuration for master read requests */ #define PXP2_REG_RD_CDURD_SWAP_MODE … /* [RW 1] When '1'; inputs to the PSWRD block are ignored */ #define PXP2_REG_RD_DISABLE_INPUTS … /* [R 1] PSWRD internal memories initialization is done */ #define PXP2_REG_RD_INIT_DONE … /* [RW 8] The maximum number of blocks in Tetris Buffer that can be allocated for vq10 */ #define PXP2_REG_RD_MAX_BLKS_VQ10 … /* [RW 8] The maximum number of blocks in Tetris Buffer that can be allocated for vq11 */ #define PXP2_REG_RD_MAX_BLKS_VQ11 … /* [RW 8] The maximum number of blocks in Tetris Buffer that can be allocated for vq17 */ #define PXP2_REG_RD_MAX_BLKS_VQ17 … /* [RW 8] The maximum number of blocks in Tetris Buffer that can be allocated for vq18 */ #define PXP2_REG_RD_MAX_BLKS_VQ18 … /* [RW 8] The maximum number of blocks in Tetris Buffer that can be allocated for vq19 */ #define PXP2_REG_RD_MAX_BLKS_VQ19 … /* [RW 8] The maximum number of blocks in Tetris Buffer that can be allocated for vq22 */ #define PXP2_REG_RD_MAX_BLKS_VQ22 … /* [RW 8] The maximum number of blocks in Tetris Buffer that can be allocated for vq25 */ #define PXP2_REG_RD_MAX_BLKS_VQ25 … /* [RW 8] The maximum number of blocks in Tetris Buffer that can be allocated for vq6 */ #define PXP2_REG_RD_MAX_BLKS_VQ6 … /* [RW 8] The maximum number of blocks in Tetris Buffer that can be allocated for vq9 */ #define PXP2_REG_RD_MAX_BLKS_VQ9 … /* [RW 2] PBF byte swapping mode configuration for master read requests */ #define PXP2_REG_RD_PBF_SWAP_MODE … /* [R 1] Debug only: Indication if delivery ports are idle */ #define PXP2_REG_RD_PORT_IS_IDLE_0 … #define PXP2_REG_RD_PORT_IS_IDLE_1 … /* [RW 2] QM byte swapping mode configuration for master read requests */ #define PXP2_REG_RD_QM_SWAP_MODE … /* [R 7] Debug only: The SR counter - number of unused sub request ids */ #define PXP2_REG_RD_SR_CNT … /* [RW 2] SRC byte swapping mode configuration for master read requests */ #define PXP2_REG_RD_SRC_SWAP_MODE … /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must be bigger than 1. Normally should not be changed. */ #define PXP2_REG_RD_SR_NUM_CFG … /* [RW 1] Signals the PSWRD block to start initializing internal memories */ #define PXP2_REG_RD_START_INIT … /* [RW 2] TM byte swapping mode configuration for master read requests */ #define PXP2_REG_RD_TM_SWAP_MODE … /* [RW 10] Bandwidth addition to VQ0 write requests */ #define PXP2_REG_RQ_BW_RD_ADD0 … /* [RW 10] Bandwidth addition to VQ12 read requests */ #define PXP2_REG_RQ_BW_RD_ADD12 … /* [RW 10] Bandwidth addition to VQ13 read requests */ #define PXP2_REG_RQ_BW_RD_ADD13 … /* [RW 10] Bandwidth addition to VQ14 read requests */ #define PXP2_REG_RQ_BW_RD_ADD14 … /* [RW 10] Bandwidth addition to VQ15 read requests */ #define PXP2_REG_RQ_BW_RD_ADD15 … /* [RW 10] Bandwidth addition to VQ16 read requests */ #define PXP2_REG_RQ_BW_RD_ADD16 … /* [RW 10] Bandwidth addition to VQ17 read requests */ #define PXP2_REG_RQ_BW_RD_ADD17 … /* [RW 10] Bandwidth addition to VQ18 read requests */ #define PXP2_REG_RQ_BW_RD_ADD18 … /* [RW 10] Bandwidth addition to VQ19 read requests */ #define PXP2_REG_RQ_BW_RD_ADD19 … /* [RW 10] Bandwidth addition to VQ20 read requests */ #define PXP2_REG_RQ_BW_RD_ADD20 … /* [RW 10] Bandwidth addition to VQ22 read requests */ #define PXP2_REG_RQ_BW_RD_ADD22 … /* [RW 10] Bandwidth addition to VQ23 read requests */ #define PXP2_REG_RQ_BW_RD_ADD23 … /* [RW 10] Bandwidth addition to VQ24 read requests */ #define PXP2_REG_RQ_BW_RD_ADD24 … /* [RW 10] Bandwidth addition to VQ25 read requests */ #define PXP2_REG_RQ_BW_RD_ADD25 … /* [RW 10] Bandwidth addition to VQ26 read requests */ #define PXP2_REG_RQ_BW_RD_ADD26 … /* [RW 10] Bandwidth addition to VQ27 read requests */ #define PXP2_REG_RQ_BW_RD_ADD27 … /* [RW 10] Bandwidth addition to VQ4 read requests */ #define PXP2_REG_RQ_BW_RD_ADD4 … /* [RW 10] Bandwidth addition to VQ5 read requests */ #define PXP2_REG_RQ_BW_RD_ADD5 … /* [RW 10] Bandwidth Typical L for VQ0 Read requests */ #define PXP2_REG_RQ_BW_RD_L0 … /* [RW 10] Bandwidth Typical L for VQ12 Read requests */ #define PXP2_REG_RQ_BW_RD_L12 … /* [RW 10] Bandwidth Typical L for VQ13 Read requests */ #define PXP2_REG_RQ_BW_RD_L13 … /* [RW 10] Bandwidth Typical L for VQ14 Read requests */ #define PXP2_REG_RQ_BW_RD_L14 … /* [RW 10] Bandwidth Typical L for VQ15 Read requests */ #define PXP2_REG_RQ_BW_RD_L15 … /* [RW 10] Bandwidth Typical L for VQ16 Read requests */ #define PXP2_REG_RQ_BW_RD_L16 … /* [RW 10] Bandwidth Typical L for VQ17 Read requests */ #define PXP2_REG_RQ_BW_RD_L17 … /* [RW 10] Bandwidth Typical L for VQ18 Read requests */ #define PXP2_REG_RQ_BW_RD_L18 … /* [RW 10] Bandwidth Typical L for VQ19 Read requests */ #define PXP2_REG_RQ_BW_RD_L19 … /* [RW 10] Bandwidth Typical L for VQ20 Read requests */ #define PXP2_REG_RQ_BW_RD_L20 … /* [RW 10] Bandwidth Typical L for VQ22 Read requests */ #define PXP2_REG_RQ_BW_RD_L22 … /* [RW 10] Bandwidth Typical L for VQ23 Read requests */ #define PXP2_REG_RQ_BW_RD_L23 … /* [RW 10] Bandwidth Typical L for VQ24 Read requests */ #define PXP2_REG_RQ_BW_RD_L24 … /* [RW 10] Bandwidth Typical L for VQ25 Read requests */ #define PXP2_REG_RQ_BW_RD_L25 … /* [RW 10] Bandwidth Typical L for VQ26 Read requests */ #define PXP2_REG_RQ_BW_RD_L26 … /* [RW 10] Bandwidth Typical L for VQ27 Read requests */ #define PXP2_REG_RQ_BW_RD_L27 … /* [RW 10] Bandwidth Typical L for VQ4 Read requests */ #define PXP2_REG_RQ_BW_RD_L4 … /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */ #define PXP2_REG_RQ_BW_RD_L5 … /* [RW 7] Bandwidth upper bound for VQ0 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND0 … /* [RW 7] Bandwidth upper bound for VQ12 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND12 … /* [RW 7] Bandwidth upper bound for VQ13 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND13 … /* [RW 7] Bandwidth upper bound for VQ14 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND14 … /* [RW 7] Bandwidth upper bound for VQ15 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND15 … /* [RW 7] Bandwidth upper bound for VQ16 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND16 … /* [RW 7] Bandwidth upper bound for VQ17 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND17 … /* [RW 7] Bandwidth upper bound for VQ18 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND18 … /* [RW 7] Bandwidth upper bound for VQ19 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND19 … /* [RW 7] Bandwidth upper bound for VQ20 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND20 … /* [RW 7] Bandwidth upper bound for VQ22 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND22 … /* [RW 7] Bandwidth upper bound for VQ23 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND23 … /* [RW 7] Bandwidth upper bound for VQ24 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND24 … /* [RW 7] Bandwidth upper bound for VQ25 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND25 … /* [RW 7] Bandwidth upper bound for VQ26 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND26 … /* [RW 7] Bandwidth upper bound for VQ27 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND27 … /* [RW 7] Bandwidth upper bound for VQ4 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND4 … /* [RW 7] Bandwidth upper bound for VQ5 read requests */ #define PXP2_REG_RQ_BW_RD_UBOUND5 … /* [RW 10] Bandwidth addition to VQ29 write requests */ #define PXP2_REG_RQ_BW_WR_ADD29 … /* [RW 10] Bandwidth addition to VQ30 write requests */ #define PXP2_REG_RQ_BW_WR_ADD30 … /* [RW 10] Bandwidth Typical L for VQ29 Write requests */ #define PXP2_REG_RQ_BW_WR_L29 … /* [RW 10] Bandwidth Typical L for VQ30 Write requests */ #define PXP2_REG_RQ_BW_WR_L30 … /* [RW 7] Bandwidth upper bound for VQ29 */ #define PXP2_REG_RQ_BW_WR_UBOUND29 … /* [RW 7] Bandwidth upper bound for VQ30 */ #define PXP2_REG_RQ_BW_WR_UBOUND30 … /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */ #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR … /* [RW 2] Endian mode for cdu */ #define PXP2_REG_RQ_CDU_ENDIAN_M … #define PXP2_REG_RQ_CDU_FIRST_ILT … #define PXP2_REG_RQ_CDU_LAST_ILT … /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k; -128k */ #define PXP2_REG_RQ_CDU_P_SIZE … /* [R 1] 1' indicates that the requester has finished its internal configuration */ #define PXP2_REG_RQ_CFG_DONE … /* [RW 2] Endian mode for debug */ #define PXP2_REG_RQ_DBG_ENDIAN_M … /* [RW 1] When '1'; requests will enter input buffers but wont get out towards the glue */ #define PXP2_REG_RQ_DISABLE_INPUTS … /* [RW 4] Determines alignment of write SRs when a request is split into * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B * aligned. 4 - 512B aligned. */ #define PXP2_REG_RQ_DRAM_ALIGN … /* [RW 4] Determines alignment of read SRs when a request is split into * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B * aligned. 4 - 512B aligned. */ #define PXP2_REG_RQ_DRAM_ALIGN_RD … /* [RW 1] when set the new alignment method (E2) will be applied; when reset * the original alignment method (E1 E1H) will be applied */ #define PXP2_REG_RQ_DRAM_ALIGN_SEL … /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will be asserted */ #define PXP2_REG_RQ_ELT_DISABLE … /* [RW 2] Endian mode for hc */ #define PXP2_REG_RQ_HC_ENDIAN_M … /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back compatibility needs; Note that different registers are used per mode */ #define PXP2_REG_RQ_ILT_MODE … /* [WB 53] Onchip address table */ #define PXP2_REG_RQ_ONCHIP_AT … /* [WB 53] Onchip address table - B0 */ #define PXP2_REG_RQ_ONCHIP_AT_B0 … /* [RW 13] Pending read limiter threshold; in Dwords */ #define PXP2_REG_RQ_PDR_LIMIT … /* [RW 2] Endian mode for qm */ #define PXP2_REG_RQ_QM_ENDIAN_M … #define PXP2_REG_RQ_QM_FIRST_ILT … #define PXP2_REG_RQ_QM_LAST_ILT … /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k; -128k */ #define PXP2_REG_RQ_QM_P_SIZE … /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */ #define PXP2_REG_RQ_RBC_DONE … /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B; 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ #define PXP2_REG_RQ_RD_MBS0 … /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B; 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ #define PXP2_REG_RQ_RD_MBS1 … /* [RW 2] Endian mode for src */ #define PXP2_REG_RQ_SRC_ENDIAN_M … #define PXP2_REG_RQ_SRC_FIRST_ILT … #define PXP2_REG_RQ_SRC_LAST_ILT … /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k; -128k */ #define PXP2_REG_RQ_SRC_P_SIZE … /* [RW 2] Endian mode for tm */ #define PXP2_REG_RQ_TM_ENDIAN_M … #define PXP2_REG_RQ_TM_FIRST_ILT … #define PXP2_REG_RQ_TM_LAST_ILT … /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k; -128k */ #define PXP2_REG_RQ_TM_P_SIZE … /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */ #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY … /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */ #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR … /* [R 8] Number of entries occupied by vq 0 in pswrq memory */ #define PXP2_REG_RQ_VQ0_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 10 in pswrq memory */ #define PXP2_REG_RQ_VQ10_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 11 in pswrq memory */ #define PXP2_REG_RQ_VQ11_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 12 in pswrq memory */ #define PXP2_REG_RQ_VQ12_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 13 in pswrq memory */ #define PXP2_REG_RQ_VQ13_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 14 in pswrq memory */ #define PXP2_REG_RQ_VQ14_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 15 in pswrq memory */ #define PXP2_REG_RQ_VQ15_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 16 in pswrq memory */ #define PXP2_REG_RQ_VQ16_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 17 in pswrq memory */ #define PXP2_REG_RQ_VQ17_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 18 in pswrq memory */ #define PXP2_REG_RQ_VQ18_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 19 in pswrq memory */ #define PXP2_REG_RQ_VQ19_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 1 in pswrq memory */ #define PXP2_REG_RQ_VQ1_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 20 in pswrq memory */ #define PXP2_REG_RQ_VQ20_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 21 in pswrq memory */ #define PXP2_REG_RQ_VQ21_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 22 in pswrq memory */ #define PXP2_REG_RQ_VQ22_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 23 in pswrq memory */ #define PXP2_REG_RQ_VQ23_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 24 in pswrq memory */ #define PXP2_REG_RQ_VQ24_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 25 in pswrq memory */ #define PXP2_REG_RQ_VQ25_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 26 in pswrq memory */ #define PXP2_REG_RQ_VQ26_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 27 in pswrq memory */ #define PXP2_REG_RQ_VQ27_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 28 in pswrq memory */ #define PXP2_REG_RQ_VQ28_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 29 in pswrq memory */ #define PXP2_REG_RQ_VQ29_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 2 in pswrq memory */ #define PXP2_REG_RQ_VQ2_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 30 in pswrq memory */ #define PXP2_REG_RQ_VQ30_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 31 in pswrq memory */ #define PXP2_REG_RQ_VQ31_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 3 in pswrq memory */ #define PXP2_REG_RQ_VQ3_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 4 in pswrq memory */ #define PXP2_REG_RQ_VQ4_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 5 in pswrq memory */ #define PXP2_REG_RQ_VQ5_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 6 in pswrq memory */ #define PXP2_REG_RQ_VQ6_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 7 in pswrq memory */ #define PXP2_REG_RQ_VQ7_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 8 in pswrq memory */ #define PXP2_REG_RQ_VQ8_ENTRY_CNT … /* [R 8] Number of entries occupied by vq 9 in pswrq memory */ #define PXP2_REG_RQ_VQ9_ENTRY_CNT … /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B; 001:256B; 010: 512B; */ #define PXP2_REG_RQ_WR_MBS0 … /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B; 001:256B; 010: 512B; */ #define PXP2_REG_RQ_WR_MBS1 … /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the buffer reaches this number has_payload will be asserted */ #define PXP2_REG_WR_CDU_MPS … /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the buffer reaches this number has_payload will be asserted */ #define PXP2_REG_WR_CSDM_MPS … /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the buffer reaches this number has_payload will be asserted */ #define PXP2_REG_WR_DBG_MPS … /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the buffer reaches this number has_payload will be asserted */ #define PXP2_REG_WR_DMAE_MPS … /* [RW 10] if Number of entries in dmae fifo will be higher than this threshold then has_payload indication will be asserted; the default value should be equal to > write MBS size! */ #define PXP2_REG_WR_DMAE_TH … /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the buffer reaches this number has_payload will be asserted */ #define PXP2_REG_WR_HC_MPS … /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the buffer reaches this number has_payload will be asserted */ #define PXP2_REG_WR_QM_MPS … /* [RW 1] 0 - working in A0 mode; - working in B0 mode */ #define PXP2_REG_WR_REV_MODE … /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the buffer reaches this number has_payload will be asserted */ #define PXP2_REG_WR_SRC_MPS … /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the buffer reaches this number has_payload will be asserted */ #define PXP2_REG_WR_TM_MPS … /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the buffer reaches this number has_payload will be asserted */ #define PXP2_REG_WR_TSDM_MPS … /* [RW 10] if Number of entries in usdmdp fifo will be higher than this threshold then has_payload indication will be asserted; the default value should be equal to > write MBS size! */ #define PXP2_REG_WR_USDMDP_TH … /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the buffer reaches this number has_payload will be asserted */ #define PXP2_REG_WR_USDM_MPS … /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the buffer reaches this number has_payload will be asserted */ #define PXP2_REG_WR_XSDM_MPS … /* [R 1] debug only: Indication if PSWHST arbiter is idle */ #define PXP_REG_HST_ARB_IS_IDLE … /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means this client is waiting for the arbiter. */ #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB … /* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue block. Should be used for close the gates. */ #define PXP_REG_HST_DISCARD_DOORBELLS … /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit should update according to 'hst_discard_doorbells' register when the state machine is idle */ #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS … /* [RW 1] When 1; new internal writes arriving to the block are discarded. Should be used for close the gates. */ #define PXP_REG_HST_DISCARD_INTERNAL_WRITES … /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1' means this PSWHST is discarding inputs from this client. Each bit should update according to 'hst_discard_internal_writes' register when the state machine is idle. */ #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS … /* [WB 160] Used for initialization of the inbound interrupts memory */ #define PXP_REG_HST_INBOUND_INT … /* [RW 7] Indirect access to the permission table. The fields are : {Valid; * VFID[5:0]} */ #define PXP_REG_HST_ZONE_PERMISSION_TABLE … /* [RW 32] Interrupt mask register #0 read/write */ #define PXP_REG_PXP_INT_MASK_0 … #define PXP_REG_PXP_INT_MASK_1 … /* [R 32] Interrupt register #0 read */ #define PXP_REG_PXP_INT_STS_0 … #define PXP_REG_PXP_INT_STS_1 … /* [RC 32] Interrupt register #0 read clear */ #define PXP_REG_PXP_INT_STS_CLR_0 … #define PXP_REG_PXP_INT_STS_CLR_1 … /* [RW 27] Parity mask register #0 read/write */ #define PXP_REG_PXP_PRTY_MASK … /* [R 26] Parity register #0 read */ #define PXP_REG_PXP_PRTY_STS … /* [RC 27] Parity register #0 read clear */ #define PXP_REG_PXP_PRTY_STS_CLR … /* [RW 4] The activity counter initial increment value sent in the load request */ #define QM_REG_ACTCTRINITVAL_0 … #define QM_REG_ACTCTRINITVAL_1 … #define QM_REG_ACTCTRINITVAL_2 … #define QM_REG_ACTCTRINITVAL_3 … /* [RW 32] The base logical address (in bytes) of each physical queue. The index I represents the physical queue number. The 12 lsbs are ignore and considered zero so practically there are only 20 bits in this register; queues 63-0 */ #define QM_REG_BASEADDR … /* [RW 32] The base logical address (in bytes) of each physical queue. The index I represents the physical queue number. The 12 lsbs are ignore and considered zero so practically there are only 20 bits in this register; queues 127-64 */ #define QM_REG_BASEADDR_EXT_A … /* [RW 16] The byte credit cost for each task. This value is for both ports */ #define QM_REG_BYTECRDCOST … /* [RW 16] The initial byte credit value for both ports. */ #define QM_REG_BYTECRDINITVAL … /* [RW 32] A bit per physical queue. If the bit is cleared then the physical queue uses port 0 else it uses port 1; queues 31-0 */ #define QM_REG_BYTECRDPORT_LSB … /* [RW 32] A bit per physical queue. If the bit is cleared then the physical queue uses port 0 else it uses port 1; queues 95-64 */ #define QM_REG_BYTECRDPORT_LSB_EXT_A … /* [RW 32] A bit per physical queue. If the bit is cleared then the physical queue uses port 0 else it uses port 1; queues 63-32 */ #define QM_REG_BYTECRDPORT_MSB … /* [RW 32] A bit per physical queue. If the bit is cleared then the physical queue uses port 0 else it uses port 1; queues 127-96 */ #define QM_REG_BYTECRDPORT_MSB_EXT_A … /* [RW 16] The byte credit value that if above the QM is considered almost full */ #define QM_REG_BYTECREDITAFULLTHR … /* [RW 4] The initial credit for interface */ #define QM_REG_CMINITCRD_0 … #define QM_REG_BYTECRDCMDQ_0 … #define QM_REG_CMINITCRD_1 … #define QM_REG_CMINITCRD_2 … #define QM_REG_CMINITCRD_3 … #define QM_REG_CMINITCRD_4 … #define QM_REG_CMINITCRD_5 … #define QM_REG_CMINITCRD_6 … #define QM_REG_CMINITCRD_7 … /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface is masked */ #define QM_REG_CMINTEN … /* [RW 12] A bit vector which indicates which one of the queues are tied to interface 0 */ #define QM_REG_CMINTVOQMASK_0 … #define QM_REG_CMINTVOQMASK_1 … #define QM_REG_CMINTVOQMASK_2 … #define QM_REG_CMINTVOQMASK_3 … #define QM_REG_CMINTVOQMASK_4 … #define QM_REG_CMINTVOQMASK_5 … #define QM_REG_CMINTVOQMASK_6 … #define QM_REG_CMINTVOQMASK_7 … /* [RW 20] The number of connections divided by 16 which dictates the size of each queue which belongs to even function number. */ #define QM_REG_CONNNUM_0 … /* [R 6] Keep the fill level of the fifo from write client 4 */ #define QM_REG_CQM_WRC_FIFOLVL … /* [RW 8] The context regions sent in the CFC load request */ #define QM_REG_CTXREG_0 … #define QM_REG_CTXREG_1 … #define QM_REG_CTXREG_2 … #define QM_REG_CTXREG_3 … /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for bypass enable */ #define QM_REG_ENBYPVOQMASK … /* [RW 32] A bit mask per each physical queue. If a bit is set then the physical queue uses the byte credit; queues 31-0 */ #define QM_REG_ENBYTECRD_LSB … /* [RW 32] A bit mask per each physical queue. If a bit is set then the physical queue uses the byte credit; queues 95-64 */ #define QM_REG_ENBYTECRD_LSB_EXT_A … /* [RW 32] A bit mask per each physical queue. If a bit is set then the physical queue uses the byte credit; queues 63-32 */ #define QM_REG_ENBYTECRD_MSB … /* [RW 32] A bit mask per each physical queue. If a bit is set then the physical queue uses the byte credit; queues 127-96 */ #define QM_REG_ENBYTECRD_MSB_EXT_A … /* [RW 4] If cleared then the secondary interface will not be served by the RR arbiter */ #define QM_REG_ENSEC … /* [RW 32] NA */ #define QM_REG_FUNCNUMSEL_LSB … /* [RW 32] NA */ #define QM_REG_FUNCNUMSEL_MSB … /* [RW 32] A mask register to mask the Almost empty signals which will not be use for the almost empty indication to the HW block; queues 31:0 */ #define QM_REG_HWAEMPTYMASK_LSB … /* [RW 32] A mask register to mask the Almost empty signals which will not be use for the almost empty indication to the HW block; queues 95-64 */ #define QM_REG_HWAEMPTYMASK_LSB_EXT_A … /* [RW 32] A mask register to mask the Almost empty signals which will not be use for the almost empty indication to the HW block; queues 63:32 */ #define QM_REG_HWAEMPTYMASK_MSB … /* [RW 32] A mask register to mask the Almost empty signals which will not be use for the almost empty indication to the HW block; queues 127-96 */ #define QM_REG_HWAEMPTYMASK_MSB_EXT_A … /* [RW 4] The number of outstanding request to CFC */ #define QM_REG_OUTLDREQ … /* [RC 1] A flag to indicate that overflow error occurred in one of the queues. */ #define QM_REG_OVFERROR … /* [RC 7] the Q where the overflow occurs */ #define QM_REG_OVFQNUM … /* [R 16] Pause state for physical queues 15-0 */ #define QM_REG_PAUSESTATE0 … /* [R 16] Pause state for physical queues 31-16 */ #define QM_REG_PAUSESTATE1 … /* [R 16] Pause state for physical queues 47-32 */ #define QM_REG_PAUSESTATE2 … /* [R 16] Pause state for physical queues 63-48 */ #define QM_REG_PAUSESTATE3 … /* [R 16] Pause state for physical queues 79-64 */ #define QM_REG_PAUSESTATE4 … /* [R 16] Pause state for physical queues 95-80 */ #define QM_REG_PAUSESTATE5 … /* [R 16] Pause state for physical queues 111-96 */ #define QM_REG_PAUSESTATE6 … /* [R 16] Pause state for physical queues 127-112 */ #define QM_REG_PAUSESTATE7 … /* [RW 2] The PCI attributes field used in the PCI request. */ #define QM_REG_PCIREQAT … #define QM_REG_PF_EN … /* [R 24] The number of tasks stored in the QM for the PF. only even * functions are valid in E2 (odd I registers will be hard wired to 0) */ #define QM_REG_PF_USG_CNT_0 … /* [R 16] NOT USED */ #define QM_REG_PORT0BYTECRD … /* [R 16] The byte credit of port 1 */ #define QM_REG_PORT1BYTECRD … /* [RW 3] pci function number of queues 15-0 */ #define QM_REG_PQ2PCIFUNC_0 … #define QM_REG_PQ2PCIFUNC_1 … #define QM_REG_PQ2PCIFUNC_2 … #define QM_REG_PQ2PCIFUNC_3 … #define QM_REG_PQ2PCIFUNC_4 … #define QM_REG_PQ2PCIFUNC_5 … #define QM_REG_PQ2PCIFUNC_6 … #define QM_REG_PQ2PCIFUNC_7 … /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow: ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ #define QM_REG_PTRTBL … /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow: ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ #define QM_REG_PTRTBL_EXT_A … /* [RW 2] Interrupt mask register #0 read/write */ #define QM_REG_QM_INT_MASK … /* [R 2] Interrupt register #0 read */ #define QM_REG_QM_INT_STS … /* [RW 12] Parity mask register #0 read/write */ #define QM_REG_QM_PRTY_MASK … /* [R 12] Parity register #0 read */ #define QM_REG_QM_PRTY_STS … /* [RC 12] Parity register #0 read clear */ #define QM_REG_QM_PRTY_STS_CLR … /* [R 32] Current queues in pipeline: Queues from 32 to 63 */ #define QM_REG_QSTATUS_HIGH … /* [R 32] Current queues in pipeline: Queues from 96 to 127 */ #define QM_REG_QSTATUS_HIGH_EXT_A … /* [R 32] Current queues in pipeline: Queues from 0 to 31 */ #define QM_REG_QSTATUS_LOW … /* [R 32] Current queues in pipeline: Queues from 64 to 95 */ #define QM_REG_QSTATUS_LOW_EXT_A … /* [R 24] The number of tasks queued for each queue; queues 63-0 */ #define QM_REG_QTASKCTR_0 … /* [R 24] The number of tasks queued for each queue; queues 127-64 */ #define QM_REG_QTASKCTR_EXT_A_0 … /* [RW 4] Queue tied to VOQ */ #define QM_REG_QVOQIDX_0 … #define QM_REG_QVOQIDX_10 … #define QM_REG_QVOQIDX_100 … #define QM_REG_QVOQIDX_101 … #define QM_REG_QVOQIDX_102 … #define QM_REG_QVOQIDX_103 … #define QM_REG_QVOQIDX_104 … #define QM_REG_QVOQIDX_105 … #define QM_REG_QVOQIDX_106 … #define QM_REG_QVOQIDX_107 … #define QM_REG_QVOQIDX_108 … #define QM_REG_QVOQIDX_109 … #define QM_REG_QVOQIDX_11 … #define QM_REG_QVOQIDX_110 … #define QM_REG_QVOQIDX_111 … #define QM_REG_QVOQIDX_112 … #define QM_REG_QVOQIDX_113 … #define QM_REG_QVOQIDX_114 … #define QM_REG_QVOQIDX_115 … #define QM_REG_QVOQIDX_116 … #define QM_REG_QVOQIDX_117 … #define QM_REG_QVOQIDX_118 … #define QM_REG_QVOQIDX_119 … #define QM_REG_QVOQIDX_12 … #define QM_REG_QVOQIDX_120 … #define QM_REG_QVOQIDX_121 … #define QM_REG_QVOQIDX_122 … #define QM_REG_QVOQIDX_123 … #define QM_REG_QVOQIDX_124 … #define QM_REG_QVOQIDX_125 … #define QM_REG_QVOQIDX_126 … #define QM_REG_QVOQIDX_127 … #define QM_REG_QVOQIDX_13 … #define QM_REG_QVOQIDX_14 … #define QM_REG_QVOQIDX_15 … #define QM_REG_QVOQIDX_16 … #define QM_REG_QVOQIDX_17 … #define QM_REG_QVOQIDX_21 … #define QM_REG_QVOQIDX_22 … #define QM_REG_QVOQIDX_23 … #define QM_REG_QVOQIDX_24 … #define QM_REG_QVOQIDX_25 … #define QM_REG_QVOQIDX_26 … #define QM_REG_QVOQIDX_27 … #define QM_REG_QVOQIDX_28 … #define QM_REG_QVOQIDX_29 … #define QM_REG_QVOQIDX_30 … #define QM_REG_QVOQIDX_31 … #define QM_REG_QVOQIDX_32 … #define QM_REG_QVOQIDX_33 … #define QM_REG_QVOQIDX_34 … #define QM_REG_QVOQIDX_35 … #define QM_REG_QVOQIDX_36 … #define QM_REG_QVOQIDX_37 … #define QM_REG_QVOQIDX_38 … #define QM_REG_QVOQIDX_39 … #define QM_REG_QVOQIDX_40 … #define QM_REG_QVOQIDX_41 … #define QM_REG_QVOQIDX_42 … #define QM_REG_QVOQIDX_43 … #define QM_REG_QVOQIDX_44 … #define QM_REG_QVOQIDX_45 … #define QM_REG_QVOQIDX_46 … #define QM_REG_QVOQIDX_47 … #define QM_REG_QVOQIDX_48 … #define QM_REG_QVOQIDX_49 … #define QM_REG_QVOQIDX_5 … #define QM_REG_QVOQIDX_50 … #define QM_REG_QVOQIDX_51 … #define QM_REG_QVOQIDX_52 … #define QM_REG_QVOQIDX_53 … #define QM_REG_QVOQIDX_54 … #define QM_REG_QVOQIDX_55 … #define QM_REG_QVOQIDX_56 … #define QM_REG_QVOQIDX_57 … #define QM_REG_QVOQIDX_58 … #define QM_REG_QVOQIDX_59 … #define QM_REG_QVOQIDX_6 … #define QM_REG_QVOQIDX_60 … #define QM_REG_QVOQIDX_61 … #define QM_REG_QVOQIDX_62 … #define QM_REG_QVOQIDX_63 … #define QM_REG_QVOQIDX_64 … #define QM_REG_QVOQIDX_65 … #define QM_REG_QVOQIDX_69 … #define QM_REG_QVOQIDX_7 … #define QM_REG_QVOQIDX_70 … #define QM_REG_QVOQIDX_71 … #define QM_REG_QVOQIDX_72 … #define QM_REG_QVOQIDX_73 … #define QM_REG_QVOQIDX_74 … #define QM_REG_QVOQIDX_75 … #define QM_REG_QVOQIDX_76 … #define QM_REG_QVOQIDX_77 … #define QM_REG_QVOQIDX_78 … #define QM_REG_QVOQIDX_79 … #define QM_REG_QVOQIDX_8 … #define QM_REG_QVOQIDX_80 … #define QM_REG_QVOQIDX_81 … #define QM_REG_QVOQIDX_85 … #define QM_REG_QVOQIDX_86 … #define QM_REG_QVOQIDX_87 … #define QM_REG_QVOQIDX_88 … #define QM_REG_QVOQIDX_89 … #define QM_REG_QVOQIDX_9 … #define QM_REG_QVOQIDX_90 … #define QM_REG_QVOQIDX_91 … #define QM_REG_QVOQIDX_92 … #define QM_REG_QVOQIDX_93 … #define QM_REG_QVOQIDX_94 … #define QM_REG_QVOQIDX_95 … #define QM_REG_QVOQIDX_96 … #define QM_REG_QVOQIDX_97 … #define QM_REG_QVOQIDX_98 … #define QM_REG_QVOQIDX_99 … /* [RW 1] Initialization bit command */ #define QM_REG_SOFT_RESET … /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */ #define QM_REG_TASKCRDCOST_0 … #define QM_REG_TASKCRDCOST_1 … #define QM_REG_TASKCRDCOST_2 … #define QM_REG_TASKCRDCOST_4 … #define QM_REG_TASKCRDCOST_5 … /* [R 6] Keep the fill level of the fifo from write client 3 */ #define QM_REG_TQM_WRC_FIFOLVL … /* [R 6] Keep the fill level of the fifo from write client 2 */ #define QM_REG_UQM_WRC_FIFOLVL … /* [RC 32] Credit update error register */ #define QM_REG_VOQCRDERRREG … /* [R 16] The credit value for each VOQ */ #define QM_REG_VOQCREDIT_0 … #define QM_REG_VOQCREDIT_1 … #define QM_REG_VOQCREDIT_4 … /* [RW 16] The credit value that if above the QM is considered almost full */ #define QM_REG_VOQCREDITAFULLTHR … /* [RW 16] The init and maximum credit for each VoQ */ #define QM_REG_VOQINITCREDIT_0 … #define QM_REG_VOQINITCREDIT_1 … #define QM_REG_VOQINITCREDIT_2 … #define QM_REG_VOQINITCREDIT_4 … #define QM_REG_VOQINITCREDIT_5 … /* [RW 1] The port of which VOQ belongs */ #define QM_REG_VOQPORT_0 … #define QM_REG_VOQPORT_1 … #define QM_REG_VOQPORT_2 … /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ #define QM_REG_VOQQMASK_0_LSB … /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ #define QM_REG_VOQQMASK_0_LSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ #define QM_REG_VOQQMASK_0_MSB … /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ #define QM_REG_VOQQMASK_0_MSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ #define QM_REG_VOQQMASK_10_LSB … /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ #define QM_REG_VOQQMASK_10_LSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ #define QM_REG_VOQQMASK_10_MSB … /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ #define QM_REG_VOQQMASK_10_MSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ #define QM_REG_VOQQMASK_11_LSB … /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ #define QM_REG_VOQQMASK_11_LSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ #define QM_REG_VOQQMASK_11_MSB … /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ #define QM_REG_VOQQMASK_11_MSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ #define QM_REG_VOQQMASK_1_LSB … /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ #define QM_REG_VOQQMASK_1_LSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ #define QM_REG_VOQQMASK_1_MSB … /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ #define QM_REG_VOQQMASK_1_MSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ #define QM_REG_VOQQMASK_2_LSB … /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ #define QM_REG_VOQQMASK_2_LSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ #define QM_REG_VOQQMASK_2_MSB … /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ #define QM_REG_VOQQMASK_2_MSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ #define QM_REG_VOQQMASK_3_LSB … /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ #define QM_REG_VOQQMASK_3_LSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ #define QM_REG_VOQQMASK_3_MSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ #define QM_REG_VOQQMASK_4_LSB … /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ #define QM_REG_VOQQMASK_4_LSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ #define QM_REG_VOQQMASK_4_MSB … /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ #define QM_REG_VOQQMASK_4_MSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ #define QM_REG_VOQQMASK_5_LSB … /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ #define QM_REG_VOQQMASK_5_LSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ #define QM_REG_VOQQMASK_5_MSB … /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ #define QM_REG_VOQQMASK_5_MSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ #define QM_REG_VOQQMASK_6_LSB … /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ #define QM_REG_VOQQMASK_6_LSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ #define QM_REG_VOQQMASK_6_MSB … /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ #define QM_REG_VOQQMASK_6_MSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ #define QM_REG_VOQQMASK_7_LSB … /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ #define QM_REG_VOQQMASK_7_LSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ #define QM_REG_VOQQMASK_7_MSB … /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ #define QM_REG_VOQQMASK_7_MSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ #define QM_REG_VOQQMASK_8_LSB … /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ #define QM_REG_VOQQMASK_8_LSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ #define QM_REG_VOQQMASK_8_MSB … /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ #define QM_REG_VOQQMASK_8_MSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ #define QM_REG_VOQQMASK_9_LSB … /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ #define QM_REG_VOQQMASK_9_LSB_EXT_A … /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ #define QM_REG_VOQQMASK_9_MSB_EXT_A … /* [RW 32] Wrr weights */ #define QM_REG_WRRWEIGHTS_0 … #define QM_REG_WRRWEIGHTS_1 … #define QM_REG_WRRWEIGHTS_10 … #define QM_REG_WRRWEIGHTS_11 … #define QM_REG_WRRWEIGHTS_12 … #define QM_REG_WRRWEIGHTS_13 … #define QM_REG_WRRWEIGHTS_14 … #define QM_REG_WRRWEIGHTS_15 … #define QM_REG_WRRWEIGHTS_16 … #define QM_REG_WRRWEIGHTS_17 … #define QM_REG_WRRWEIGHTS_18 … #define QM_REG_WRRWEIGHTS_19 … #define QM_REG_WRRWEIGHTS_2 … #define QM_REG_WRRWEIGHTS_20 … #define QM_REG_WRRWEIGHTS_21 … #define QM_REG_WRRWEIGHTS_22 … #define QM_REG_WRRWEIGHTS_23 … #define QM_REG_WRRWEIGHTS_24 … #define QM_REG_WRRWEIGHTS_25 … #define QM_REG_WRRWEIGHTS_26 … #define QM_REG_WRRWEIGHTS_27 … #define QM_REG_WRRWEIGHTS_28 … #define QM_REG_WRRWEIGHTS_29 … #define QM_REG_WRRWEIGHTS_3 … #define QM_REG_WRRWEIGHTS_30 … #define QM_REG_WRRWEIGHTS_31 … #define QM_REG_WRRWEIGHTS_4 … #define QM_REG_WRRWEIGHTS_5 … #define QM_REG_WRRWEIGHTS_6 … #define QM_REG_WRRWEIGHTS_7 … #define QM_REG_WRRWEIGHTS_8 … #define QM_REG_WRRWEIGHTS_9 … /* [R 6] Keep the fill level of the fifo from write client 1 */ #define QM_REG_XQM_WRC_FIFOLVL … /* [W 1] reset to parity interrupt */ #define SEM_FAST_REG_PARITY_RST … #define SRC_REG_COUNTFREE0 … /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two ports. If set the searcher support 8 functions. */ #define SRC_REG_E1HMF_ENABLE … #define SRC_REG_FIRSTFREE0 … #define SRC_REG_KEYRSS0_0 … #define SRC_REG_KEYRSS0_7 … #define SRC_REG_KEYRSS1_9 … #define SRC_REG_KEYSEARCH_0 … #define SRC_REG_KEYSEARCH_1 … #define SRC_REG_KEYSEARCH_2 … #define SRC_REG_KEYSEARCH_3 … #define SRC_REG_KEYSEARCH_4 … #define SRC_REG_KEYSEARCH_5 … #define SRC_REG_KEYSEARCH_6 … #define SRC_REG_KEYSEARCH_7 … #define SRC_REG_KEYSEARCH_8 … #define SRC_REG_KEYSEARCH_9 … #define SRC_REG_LASTFREE0 … #define SRC_REG_NUMBER_HASH_BITS0 … /* [RW 1] Reset internal state machines. */ #define SRC_REG_SOFT_RST … /* [R 3] Interrupt register #0 read */ #define SRC_REG_SRC_INT_STS … /* [RW 3] Parity mask register #0 read/write */ #define SRC_REG_SRC_PRTY_MASK … /* [R 3] Parity register #0 read */ #define SRC_REG_SRC_PRTY_STS … /* [RC 3] Parity register #0 read clear */ #define SRC_REG_SRC_PRTY_STS_CLR … /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */ #define TCM_REG_CAM_OCCUP … /* [RW 1] CDU AG read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define TCM_REG_CDU_AG_RD_IFEN … /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input are disregarded; all other signals are treated as usual; if 1 - normal activity. */ #define TCM_REG_CDU_AG_WR_IFEN … /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define TCM_REG_CDU_SM_RD_IFEN … /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid input is disregarded; all other signals are treated as usual; if 1 - normal activity. */ #define TCM_REG_CDU_SM_WR_IFEN … /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 1 at start-up. */ #define TCM_REG_CFC_INIT_CRD … /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define TCM_REG_CP_WEIGHT … /* [RW 1] Input csem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define TCM_REG_CSEM_IFEN … /* [RC 1] Message length mismatch (relative to last indication) at the In#9 interface. */ #define TCM_REG_CSEM_LENGTH_MIS … /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define TCM_REG_CSEM_WEIGHT … /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */ #define TCM_REG_ERR_EVNT_ID … /* [RW 28] The CM erroneous header for QM and Timers formatting. */ #define TCM_REG_ERR_TCM_HDR … /* [RW 8] The Event ID for Timers expiration. */ #define TCM_REG_EXPR_EVNT_ID … /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 64 at start-up. */ #define TCM_REG_FIC0_INIT_CRD … /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 64 at start-up. */ #define TCM_REG_FIC1_INIT_CRD … /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr; ~tcm_registers_gr_ld0_pr.gr_ld0_pr and ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */ #define TCM_REG_GR_ARB_TYPE … /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Store channel is the complement of the other 3 groups. */ #define TCM_REG_GR_LD0_PR … /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Store channel is the complement of the other 3 groups. */ #define TCM_REG_GR_LD1_PR … /* [RW 4] The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16). */ #define TCM_REG_N_SM_CTX_LD_0 … #define TCM_REG_N_SM_CTX_LD_1 … #define TCM_REG_N_SM_CTX_LD_2 … #define TCM_REG_N_SM_CTX_LD_3 … #define TCM_REG_N_SM_CTX_LD_4 … #define TCM_REG_N_SM_CTX_LD_5 … /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define TCM_REG_PBF_IFEN … /* [RC 1] Message length mismatch (relative to last indication) at the In#7 interface. */ #define TCM_REG_PBF_LENGTH_MIS … /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define TCM_REG_PBF_WEIGHT … #define TCM_REG_PHYS_QNUM0_0 … #define TCM_REG_PHYS_QNUM0_1 … #define TCM_REG_PHYS_QNUM1_0 … #define TCM_REG_PHYS_QNUM1_1 … #define TCM_REG_PHYS_QNUM2_0 … #define TCM_REG_PHYS_QNUM2_1 … #define TCM_REG_PHYS_QNUM3_0 … #define TCM_REG_PHYS_QNUM3_1 … /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define TCM_REG_PRS_IFEN … /* [RC 1] Message length mismatch (relative to last indication) at the In#6 interface. */ #define TCM_REG_PRS_LENGTH_MIS … /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define TCM_REG_PRS_WEIGHT … /* [RW 8] The Event ID for Timers formatting in case of stop done. */ #define TCM_REG_STOP_EVNT_ID … /* [RC 1] Message length mismatch (relative to last indication) at the STORM interface. */ #define TCM_REG_STORM_LENGTH_MIS … /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define TCM_REG_STORM_TCM_IFEN … /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define TCM_REG_STORM_WEIGHT … /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define TCM_REG_TCM_CFC_IFEN … /* [RW 11] Interrupt mask register #0 read/write */ #define TCM_REG_TCM_INT_MASK … /* [R 11] Interrupt register #0 read */ #define TCM_REG_TCM_INT_STS … /* [RW 27] Parity mask register #0 read/write */ #define TCM_REG_TCM_PRTY_MASK … /* [R 27] Parity register #0 read */ #define TCM_REG_TCM_PRTY_STS … /* [RC 27] Parity register #0 read clear */ #define TCM_REG_TCM_PRTY_STS_CLR … /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). Is used to determine the number of the AG context REG-pairs written back; when the input message Reg1WbFlg isn't set. */ #define TCM_REG_TCM_REG0_SZ … /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define TCM_REG_TCM_STORM0_IFEN … /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define TCM_REG_TCM_STORM1_IFEN … /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define TCM_REG_TCM_TQM_IFEN … /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ #define TCM_REG_TCM_TQM_USE_Q … /* [RW 28] The CM header for Timers expiration command. */ #define TCM_REG_TM_TCM_HDR … /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define TCM_REG_TM_TCM_IFEN … /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define TCM_REG_TM_WEIGHT … /* [RW 6] QM output initial credit. Max credit available - 32.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 32 at start-up. */ #define TCM_REG_TQM_INIT_CRD … /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define TCM_REG_TQM_P_WEIGHT … /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define TCM_REG_TQM_S_WEIGHT … /* [RW 28] The CM header value for QM request (primary). */ #define TCM_REG_TQM_TCM_HDR_P … /* [RW 28] The CM header value for QM request (secondary). */ #define TCM_REG_TQM_TCM_HDR_S … /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define TCM_REG_TQM_TCM_IFEN … /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define TCM_REG_TSDM_IFEN … /* [RC 1] Message length mismatch (relative to last indication) at the SDM interface. */ #define TCM_REG_TSDM_LENGTH_MIS … /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define TCM_REG_TSDM_WEIGHT … /* [RW 1] Input usem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define TCM_REG_USEM_IFEN … /* [RC 1] Message length mismatch (relative to last indication) at the In#8 interface. */ #define TCM_REG_USEM_LENGTH_MIS … /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define TCM_REG_USEM_WEIGHT … /* [RW 21] Indirect access to the descriptor table of the XX protection mechanism. The fields are: [5:0] - length of the message; 15:6] - message pointer; 20:16] - next pointer. */ #define TCM_REG_XX_DESCR_TABLE … #define TCM_REG_XX_DESCR_TABLE_SIZE … /* [R 6] Use to read the value of XX protection Free counter. */ #define TCM_REG_XX_FREE … /* [RW 6] Initial value for the credit counter; responsible for fulfilling of the Input Stage XX protection buffer by the XX protection pending messages. Max credit available - 127.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 19 at start-up. */ #define TCM_REG_XX_INIT_CRD … /* [RW 6] Maximum link list size (messages locked) per connection in the XX protection. */ #define TCM_REG_XX_MAX_LL_SZ … /* [RW 6] The maximum number of pending messages; which may be stored in XX protection. ~tcm_registers_xx_free.xx_free is read on read. */ #define TCM_REG_XX_MSG_NUM … /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ #define TCM_REG_XX_OVFL_EVNT_ID … /* [RW 16] Indirect access to the XX table of the XX protection mechanism. The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] - header pointer. */ #define TCM_REG_XX_TABLE … /* [RW 4] Load value for cfc ac credit cnt. */ #define TM_REG_CFC_AC_CRDCNT_VAL … /* [RW 4] Load value for cfc cld credit cnt. */ #define TM_REG_CFC_CLD_CRDCNT_VAL … /* [RW 8] Client0 context region. */ #define TM_REG_CL0_CONT_REGION … /* [RW 8] Client1 context region. */ #define TM_REG_CL1_CONT_REGION … /* [RW 8] Client2 context region. */ #define TM_REG_CL2_CONT_REGION … /* [RW 2] Client in High priority client number. */ #define TM_REG_CLIN_PRIOR0_CLIENT … /* [RW 4] Load value for clout0 cred cnt. */ #define TM_REG_CLOUT_CRDCNT0_VAL … /* [RW 4] Load value for clout1 cred cnt. */ #define TM_REG_CLOUT_CRDCNT1_VAL … /* [RW 4] Load value for clout2 cred cnt. */ #define TM_REG_CLOUT_CRDCNT2_VAL … /* [RW 1] Enable client0 input. */ #define TM_REG_EN_CL0_INPUT … /* [RW 1] Enable client1 input. */ #define TM_REG_EN_CL1_INPUT … /* [RW 1] Enable client2 input. */ #define TM_REG_EN_CL2_INPUT … #define TM_REG_EN_LINEAR0_TIMER … /* [RW 1] Enable real time counter. */ #define TM_REG_EN_REAL_TIME_CNT … /* [RW 1] Enable for Timers state machines. */ #define TM_REG_EN_TIMERS … /* [RW 4] Load value for expiration credit cnt. CFC max number of outstanding load requests for timers (expiration) context loading. */ #define TM_REG_EXP_CRDCNT_VAL … /* [RW 32] Linear0 logic address. */ #define TM_REG_LIN0_LOGIC_ADDR … /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */ #define TM_REG_LIN0_MAX_ACTIVE_CID … /* [ST 16] Linear0 Number of scans counter. */ #define TM_REG_LIN0_NUM_SCANS … /* [WB 64] Linear0 phy address. */ #define TM_REG_LIN0_PHY_ADDR … /* [RW 1] Linear0 physical address valid. */ #define TM_REG_LIN0_PHY_ADDR_VALID … #define TM_REG_LIN0_SCAN_ON … /* [RW 24] Linear0 array scan timeout. */ #define TM_REG_LIN0_SCAN_TIME … #define TM_REG_LIN0_VNIC_UC … /* [RW 32] Linear1 logic address. */ #define TM_REG_LIN1_LOGIC_ADDR … /* [WB 64] Linear1 phy address. */ #define TM_REG_LIN1_PHY_ADDR … /* [RW 1] Linear1 physical address valid. */ #define TM_REG_LIN1_PHY_ADDR_VALID … /* [RW 6] Linear timer set_clear fifo threshold. */ #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR … /* [RW 2] Load value for pci arbiter credit cnt. */ #define TM_REG_PCIARB_CRDCNT_VAL … /* [RW 20] The amount of hardware cycles for each timer tick. */ #define TM_REG_TIMER_TICK_SIZE … /* [RW 8] Timers Context region. */ #define TM_REG_TM_CONTEXT_REGION … /* [RW 1] Interrupt mask register #0 read/write */ #define TM_REG_TM_INT_MASK … /* [R 1] Interrupt register #0 read */ #define TM_REG_TM_INT_STS … /* [RW 7] Parity mask register #0 read/write */ #define TM_REG_TM_PRTY_MASK … /* [R 7] Parity register #0 read */ #define TM_REG_TM_PRTY_STS … /* [RC 7] Parity register #0 read clear */ #define TM_REG_TM_PRTY_STS_CLR … /* [RW 8] The event id for aggregated interrupt 0 */ #define TSDM_REG_AGG_INT_EVENT_0 … #define TSDM_REG_AGG_INT_EVENT_1 … #define TSDM_REG_AGG_INT_EVENT_2 … #define TSDM_REG_AGG_INT_EVENT_3 … #define TSDM_REG_AGG_INT_EVENT_4 … /* [RW 1] The T bit for aggregated interrupt 0 */ #define TSDM_REG_AGG_INT_T_0 … #define TSDM_REG_AGG_INT_T_1 … /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ #define TSDM_REG_CFC_RSP_START_ADDR … /* [RW 16] The maximum value of the completion counter #0 */ #define TSDM_REG_CMP_COUNTER_MAX0 … /* [RW 16] The maximum value of the completion counter #1 */ #define TSDM_REG_CMP_COUNTER_MAX1 … /* [RW 16] The maximum value of the completion counter #2 */ #define TSDM_REG_CMP_COUNTER_MAX2 … /* [RW 16] The maximum value of the completion counter #3 */ #define TSDM_REG_CMP_COUNTER_MAX3 … /* [RW 13] The start address in the internal RAM for the completion counters. */ #define TSDM_REG_CMP_COUNTER_START_ADDR … #define TSDM_REG_ENABLE_IN1 … #define TSDM_REG_ENABLE_IN2 … #define TSDM_REG_ENABLE_OUT1 … #define TSDM_REG_ENABLE_OUT2 … /* [RW 4] The initial number of messages that can be sent to the pxp control interface without receiving any ACK. */ #define TSDM_REG_INIT_CREDIT_PXP_CTRL … /* [ST 32] The number of ACK after placement messages received */ #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE … /* [ST 32] The number of packet end messages received from the parser */ #define TSDM_REG_NUM_OF_PKT_END_MSG … /* [ST 32] The number of requests received from the pxp async if */ #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ … /* [ST 32] The number of commands received in queue 0 */ #define TSDM_REG_NUM_OF_Q0_CMD … /* [ST 32] The number of commands received in queue 10 */ #define TSDM_REG_NUM_OF_Q10_CMD … /* [ST 32] The number of commands received in queue 11 */ #define TSDM_REG_NUM_OF_Q11_CMD … /* [ST 32] The number of commands received in queue 1 */ #define TSDM_REG_NUM_OF_Q1_CMD … /* [ST 32] The number of commands received in queue 3 */ #define TSDM_REG_NUM_OF_Q3_CMD … /* [ST 32] The number of commands received in queue 4 */ #define TSDM_REG_NUM_OF_Q4_CMD … /* [ST 32] The number of commands received in queue 5 */ #define TSDM_REG_NUM_OF_Q5_CMD … /* [ST 32] The number of commands received in queue 6 */ #define TSDM_REG_NUM_OF_Q6_CMD … /* [ST 32] The number of commands received in queue 7 */ #define TSDM_REG_NUM_OF_Q7_CMD … /* [ST 32] The number of commands received in queue 8 */ #define TSDM_REG_NUM_OF_Q8_CMD … /* [ST 32] The number of commands received in queue 9 */ #define TSDM_REG_NUM_OF_Q9_CMD … /* [RW 13] The start address in the internal RAM for the packet end message */ #define TSDM_REG_PCK_END_MSG_START_ADDR … /* [RW 13] The start address in the internal RAM for queue counters */ #define TSDM_REG_Q_COUNTER_START_ADDR … /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY … /* [R 1] parser fifo empty in sdm_sync block */ #define TSDM_REG_SYNC_PARSER_EMPTY … /* [R 1] parser serial fifo empty in sdm_sync block */ #define TSDM_REG_SYNC_SYNC_EMPTY … /* [RW 32] Tick for timer counter. Applicable only when ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */ #define TSDM_REG_TIMER_TICK … /* [RW 32] Interrupt mask register #0 read/write */ #define TSDM_REG_TSDM_INT_MASK_0 … #define TSDM_REG_TSDM_INT_MASK_1 … /* [R 32] Interrupt register #0 read */ #define TSDM_REG_TSDM_INT_STS_0 … #define TSDM_REG_TSDM_INT_STS_1 … /* [RW 11] Parity mask register #0 read/write */ #define TSDM_REG_TSDM_PRTY_MASK … /* [R 11] Parity register #0 read */ #define TSDM_REG_TSDM_PRTY_STS … /* [RC 11] Parity register #0 read clear */ #define TSDM_REG_TSDM_PRTY_STS_CLR … /* [RW 5] The number of time_slots in the arbitration cycle */ #define TSEM_REG_ARB_CYCLE_SIZE … /* [RW 3] The source that is associated with arbitration element 0. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2 */ #define TSEM_REG_ARB_ELEMENT0 … /* [RW 3] The source that is associated with arbitration element 1. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */ #define TSEM_REG_ARB_ELEMENT1 … /* [RW 3] The source that is associated with arbitration element 2. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~tsem_registers_arb_element0.arb_element0 and ~tsem_registers_arb_element1.arb_element1 */ #define TSEM_REG_ARB_ELEMENT2 … /* [RW 3] The source that is associated with arbitration element 3. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2.Could not be equal to register ~tsem_registers_arb_element0.arb_element0 and ~tsem_registers_arb_element1.arb_element1 and ~tsem_registers_arb_element2.arb_element2 */ #define TSEM_REG_ARB_ELEMENT3 … /* [RW 3] The source that is associated with arbitration element 4. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~tsem_registers_arb_element0.arb_element0 and ~tsem_registers_arb_element1.arb_element1 and ~tsem_registers_arb_element2.arb_element2 and ~tsem_registers_arb_element3.arb_element3 */ #define TSEM_REG_ARB_ELEMENT4 … #define TSEM_REG_ENABLE_IN … #define TSEM_REG_ENABLE_OUT … /* [RW 32] This address space contains all registers and memories that are placed in SEM_FAST block. The SEM_FAST registers are described in appendix B. In order to access the sem_fast registers the base address ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ #define TSEM_REG_FAST_MEMORY … /* [RW 1] Disables input messages from FIC0 May be updated during run_time by the microcode */ #define TSEM_REG_FIC0_DISABLE … /* [RW 1] Disables input messages from FIC1 May be updated during run_time by the microcode */ #define TSEM_REG_FIC1_DISABLE … /* [RW 15] Interrupt table Read and write access to it is not possible in the middle of the work */ #define TSEM_REG_INT_TABLE … /* [ST 24] Statistics register. The number of messages that entered through FIC0 */ #define TSEM_REG_MSG_NUM_FIC0 … /* [ST 24] Statistics register. The number of messages that entered through FIC1 */ #define TSEM_REG_MSG_NUM_FIC1 … /* [ST 24] Statistics register. The number of messages that were sent to FOC0 */ #define TSEM_REG_MSG_NUM_FOC0 … /* [ST 24] Statistics register. The number of messages that were sent to FOC1 */ #define TSEM_REG_MSG_NUM_FOC1 … /* [ST 24] Statistics register. The number of messages that were sent to FOC2 */ #define TSEM_REG_MSG_NUM_FOC2 … /* [ST 24] Statistics register. The number of messages that were sent to FOC3 */ #define TSEM_REG_MSG_NUM_FOC3 … /* [RW 1] Disables input messages from the passive buffer May be updated during run_time by the microcode */ #define TSEM_REG_PAS_DISABLE … /* [WB 128] Debug only. Passive buffer memory */ #define TSEM_REG_PASSIVE_BUFFER … /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ #define TSEM_REG_PRAM … /* [R 8] Valid sleeping threads indication have bit per thread */ #define TSEM_REG_SLEEP_THREADS_VALID … /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ #define TSEM_REG_SLOW_EXT_STORE_EMPTY … /* [RW 8] List of free threads . There is a bit per thread. */ #define TSEM_REG_THREADS_LIST … /* [RC 32] Parity register #0 read clear */ #define TSEM_REG_TSEM_PRTY_STS_CLR_0 … #define TSEM_REG_TSEM_PRTY_STS_CLR_1 … /* [RW 3] The arbitration scheme of time_slot 0 */ #define TSEM_REG_TS_0_AS … /* [RW 3] The arbitration scheme of time_slot 10 */ #define TSEM_REG_TS_10_AS … /* [RW 3] The arbitration scheme of time_slot 11 */ #define TSEM_REG_TS_11_AS … /* [RW 3] The arbitration scheme of time_slot 12 */ #define TSEM_REG_TS_12_AS … /* [RW 3] The arbitration scheme of time_slot 13 */ #define TSEM_REG_TS_13_AS … /* [RW 3] The arbitration scheme of time_slot 14 */ #define TSEM_REG_TS_14_AS … /* [RW 3] The arbitration scheme of time_slot 15 */ #define TSEM_REG_TS_15_AS … /* [RW 3] The arbitration scheme of time_slot 16 */ #define TSEM_REG_TS_16_AS … /* [RW 3] The arbitration scheme of time_slot 17 */ #define TSEM_REG_TS_17_AS … /* [RW 3] The arbitration scheme of time_slot 18 */ #define TSEM_REG_TS_18_AS … /* [RW 3] The arbitration scheme of time_slot 1 */ #define TSEM_REG_TS_1_AS … /* [RW 3] The arbitration scheme of time_slot 2 */ #define TSEM_REG_TS_2_AS … /* [RW 3] The arbitration scheme of time_slot 3 */ #define TSEM_REG_TS_3_AS … /* [RW 3] The arbitration scheme of time_slot 4 */ #define TSEM_REG_TS_4_AS … /* [RW 3] The arbitration scheme of time_slot 5 */ #define TSEM_REG_TS_5_AS … /* [RW 3] The arbitration scheme of time_slot 6 */ #define TSEM_REG_TS_6_AS … /* [RW 3] The arbitration scheme of time_slot 7 */ #define TSEM_REG_TS_7_AS … /* [RW 3] The arbitration scheme of time_slot 8 */ #define TSEM_REG_TS_8_AS … /* [RW 3] The arbitration scheme of time_slot 9 */ #define TSEM_REG_TS_9_AS … /* [RW 32] Interrupt mask register #0 read/write */ #define TSEM_REG_TSEM_INT_MASK_0 … #define TSEM_REG_TSEM_INT_MASK_1 … /* [R 32] Interrupt register #0 read */ #define TSEM_REG_TSEM_INT_STS_0 … #define TSEM_REG_TSEM_INT_STS_1 … /* [RW 32] Parity mask register #0 read/write */ #define TSEM_REG_TSEM_PRTY_MASK_0 … #define TSEM_REG_TSEM_PRTY_MASK_1 … /* [R 32] Parity register #0 read */ #define TSEM_REG_TSEM_PRTY_STS_0 … #define TSEM_REG_TSEM_PRTY_STS_1 … /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ #define TSEM_REG_VFPF_ERR_NUM … /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits * [10:8] of the address should be the offset within the accessed LCID * context; the bits [7:0] are the accessed LCID.Example: to write to REG10 * LCID100. The RBC address should be 12'ha64. */ #define UCM_REG_AG_CTX … /* [R 5] Used to read the XX protection CAM occupancy counter. */ #define UCM_REG_CAM_OCCUP … /* [RW 1] CDU AG read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define UCM_REG_CDU_AG_RD_IFEN … /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input are disregarded; all other signals are treated as usual; if 1 - normal activity. */ #define UCM_REG_CDU_AG_WR_IFEN … /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define UCM_REG_CDU_SM_RD_IFEN … /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid input is disregarded; all other signals are treated as usual; if 1 - normal activity. */ #define UCM_REG_CDU_SM_WR_IFEN … /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 1 at start-up. */ #define UCM_REG_CFC_INIT_CRD … /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define UCM_REG_CP_WEIGHT … /* [RW 1] Input csem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define UCM_REG_CSEM_IFEN … /* [RC 1] Set when the message length mismatch (relative to last indication) at the csem interface is detected. */ #define UCM_REG_CSEM_LENGTH_MIS … /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define UCM_REG_CSEM_WEIGHT … /* [RW 1] Input dorq Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define UCM_REG_DORQ_IFEN … /* [RC 1] Set when the message length mismatch (relative to last indication) at the dorq interface is detected. */ #define UCM_REG_DORQ_LENGTH_MIS … /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define UCM_REG_DORQ_WEIGHT … /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */ #define UCM_REG_ERR_EVNT_ID … /* [RW 28] The CM erroneous header for QM and Timers formatting. */ #define UCM_REG_ERR_UCM_HDR … /* [RW 8] The Event ID for Timers expiration. */ #define UCM_REG_EXPR_EVNT_ID … /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 64 at start-up. */ #define UCM_REG_FIC0_INIT_CRD … /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 64 at start-up. */ #define UCM_REG_FIC1_INIT_CRD … /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr; ~ucm_registers_gr_ld0_pr.gr_ld0_pr and ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */ #define UCM_REG_GR_ARB_TYPE … /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Store channel group is complement to the others. */ #define UCM_REG_GR_LD0_PR … /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Store channel group is complement to the others. */ #define UCM_REG_GR_LD1_PR … /* [RW 2] The queue index for invalidate counter flag decision. */ #define UCM_REG_INV_CFLG_Q … /* [RW 5] The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. the double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16). */ #define UCM_REG_N_SM_CTX_LD_0 … #define UCM_REG_N_SM_CTX_LD_1 … #define UCM_REG_N_SM_CTX_LD_2 … #define UCM_REG_N_SM_CTX_LD_3 … #define UCM_REG_N_SM_CTX_LD_4 … #define UCM_REG_N_SM_CTX_LD_5 … #define UCM_REG_PHYS_QNUM0_0 … #define UCM_REG_PHYS_QNUM0_1 … #define UCM_REG_PHYS_QNUM1_0 … #define UCM_REG_PHYS_QNUM1_1 … #define UCM_REG_PHYS_QNUM2_0 … #define UCM_REG_PHYS_QNUM2_1 … #define UCM_REG_PHYS_QNUM3_0 … #define UCM_REG_PHYS_QNUM3_1 … /* [RW 8] The Event ID for Timers formatting in case of stop done. */ #define UCM_REG_STOP_EVNT_ID … /* [RC 1] Set when the message length mismatch (relative to last indication) at the STORM interface is detected. */ #define UCM_REG_STORM_LENGTH_MIS … /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define UCM_REG_STORM_UCM_IFEN … /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define UCM_REG_STORM_WEIGHT … /* [RW 4] Timers output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 4 at start-up. */ #define UCM_REG_TM_INIT_CRD … /* [RW 28] The CM header for Timers expiration command. */ #define UCM_REG_TM_UCM_HDR … /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define UCM_REG_TM_UCM_IFEN … /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define UCM_REG_TM_WEIGHT … /* [RW 1] Input tsem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define UCM_REG_TSEM_IFEN … /* [RC 1] Set when the message length mismatch (relative to last indication) at the tsem interface is detected. */ #define UCM_REG_TSEM_LENGTH_MIS … /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define UCM_REG_TSEM_WEIGHT … /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define UCM_REG_UCM_CFC_IFEN … /* [RW 11] Interrupt mask register #0 read/write */ #define UCM_REG_UCM_INT_MASK … /* [R 11] Interrupt register #0 read */ #define UCM_REG_UCM_INT_STS … /* [RW 27] Parity mask register #0 read/write */ #define UCM_REG_UCM_PRTY_MASK … /* [R 27] Parity register #0 read */ #define UCM_REG_UCM_PRTY_STS … /* [RC 27] Parity register #0 read clear */ #define UCM_REG_UCM_PRTY_STS_CLR … /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). Is used to determine the number of the AG context REG-pairs written back; when the Reg1WbFlg isn't set. */ #define UCM_REG_UCM_REG0_SZ … /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define UCM_REG_UCM_STORM0_IFEN … /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define UCM_REG_UCM_STORM1_IFEN … /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define UCM_REG_UCM_TM_IFEN … /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define UCM_REG_UCM_UQM_IFEN … /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ #define UCM_REG_UCM_UQM_USE_Q … /* [RW 6] QM output initial credit. Max credit available - 32.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 32 at start-up. */ #define UCM_REG_UQM_INIT_CRD … /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define UCM_REG_UQM_P_WEIGHT … /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define UCM_REG_UQM_S_WEIGHT … /* [RW 28] The CM header value for QM request (primary). */ #define UCM_REG_UQM_UCM_HDR_P … /* [RW 28] The CM header value for QM request (secondary). */ #define UCM_REG_UQM_UCM_HDR_S … /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define UCM_REG_UQM_UCM_IFEN … /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define UCM_REG_USDM_IFEN … /* [RC 1] Set when the message length mismatch (relative to last indication) at the SDM interface is detected. */ #define UCM_REG_USDM_LENGTH_MIS … /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define UCM_REG_USDM_WEIGHT … /* [RW 1] Input xsem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define UCM_REG_XSEM_IFEN … /* [RC 1] Set when the message length mismatch (relative to last indication) at the xsem interface isdetected. */ #define UCM_REG_XSEM_LENGTH_MIS … /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define UCM_REG_XSEM_WEIGHT … /* [RW 20] Indirect access to the descriptor table of the XX protection mechanism. The fields are:[5:0] - message length; 14:6] - message pointer; 19:15] - next pointer. */ #define UCM_REG_XX_DESCR_TABLE … #define UCM_REG_XX_DESCR_TABLE_SIZE … /* [R 6] Use to read the XX protection Free counter. */ #define UCM_REG_XX_FREE … /* [RW 6] Initial value for the credit counter; responsible for fulfilling of the Input Stage XX protection buffer by the XX protection pending messages. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 12 at start-up. */ #define UCM_REG_XX_INIT_CRD … /* [RW 6] The maximum number of pending messages; which may be stored in XX protection. ~ucm_registers_xx_free.xx_free read on read. */ #define UCM_REG_XX_MSG_NUM … /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ #define UCM_REG_XX_OVFL_EVNT_ID … /* [RW 16] Indirect access to the XX table of the XX protection mechanism. The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] - header pointer. */ #define UCM_REG_XX_TABLE … #define UMAC_COMMAND_CONFIG_REG_HD_ENA … #define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE … #define UMAC_COMMAND_CONFIG_REG_LOOP_ENA … #define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK … #define UMAC_COMMAND_CONFIG_REG_PAD_EN … #define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE … #define UMAC_COMMAND_CONFIG_REG_PROMIS_EN … #define UMAC_COMMAND_CONFIG_REG_RX_ENA … #define UMAC_COMMAND_CONFIG_REG_SW_RESET … #define UMAC_COMMAND_CONFIG_REG_TX_ENA … #define UMAC_REG_COMMAND_CONFIG … /* [RW 16] This is the duration for which MAC must wait to go back to ACTIVE * state from LPI state when it receives packet for transmission. The * decrement unit is 1 micro-second. */ #define UMAC_REG_EEE_WAKE_TIMER … /* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers * to bit 17 of the MAC address etc. */ #define UMAC_REG_MAC_ADDR0 … /* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1 * refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved. */ #define UMAC_REG_MAC_ADDR1 … /* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive * logic to check frames. */ #define UMAC_REG_MAXFR … #define UMAC_REG_UMAC_EEE_CTRL … #define UMAC_UMAC_EEE_CTRL_REG_EEE_EN … /* [RW 8] The event id for aggregated interrupt 0 */ #define USDM_REG_AGG_INT_EVENT_0 … #define USDM_REG_AGG_INT_EVENT_1 … #define USDM_REG_AGG_INT_EVENT_2 … #define USDM_REG_AGG_INT_EVENT_4 … #define USDM_REG_AGG_INT_EVENT_5 … #define USDM_REG_AGG_INT_EVENT_6 … /* [RW 1] For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1) */ #define USDM_REG_AGG_INT_MODE_0 … #define USDM_REG_AGG_INT_MODE_1 … #define USDM_REG_AGG_INT_MODE_4 … #define USDM_REG_AGG_INT_MODE_5 … #define USDM_REG_AGG_INT_MODE_6 … /* [RW 1] The T bit for aggregated interrupt 5 */ #define USDM_REG_AGG_INT_T_5 … #define USDM_REG_AGG_INT_T_6 … /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ #define USDM_REG_CFC_RSP_START_ADDR … /* [RW 16] The maximum value of the completion counter #0 */ #define USDM_REG_CMP_COUNTER_MAX0 … /* [RW 16] The maximum value of the completion counter #1 */ #define USDM_REG_CMP_COUNTER_MAX1 … /* [RW 16] The maximum value of the completion counter #2 */ #define USDM_REG_CMP_COUNTER_MAX2 … /* [RW 16] The maximum value of the completion counter #3 */ #define USDM_REG_CMP_COUNTER_MAX3 … /* [RW 13] The start address in the internal RAM for the completion counters. */ #define USDM_REG_CMP_COUNTER_START_ADDR … #define USDM_REG_ENABLE_IN1 … #define USDM_REG_ENABLE_IN2 … #define USDM_REG_ENABLE_OUT1 … #define USDM_REG_ENABLE_OUT2 … /* [RW 4] The initial number of messages that can be sent to the pxp control interface without receiving any ACK. */ #define USDM_REG_INIT_CREDIT_PXP_CTRL … /* [ST 32] The number of ACK after placement messages received */ #define USDM_REG_NUM_OF_ACK_AFTER_PLACE … /* [ST 32] The number of packet end messages received from the parser */ #define USDM_REG_NUM_OF_PKT_END_MSG … /* [ST 32] The number of requests received from the pxp async if */ #define USDM_REG_NUM_OF_PXP_ASYNC_REQ … /* [ST 32] The number of commands received in queue 0 */ #define USDM_REG_NUM_OF_Q0_CMD … /* [ST 32] The number of commands received in queue 10 */ #define USDM_REG_NUM_OF_Q10_CMD … /* [ST 32] The number of commands received in queue 11 */ #define USDM_REG_NUM_OF_Q11_CMD … /* [ST 32] The number of commands received in queue 1 */ #define USDM_REG_NUM_OF_Q1_CMD … /* [ST 32] The number of commands received in queue 2 */ #define USDM_REG_NUM_OF_Q2_CMD … /* [ST 32] The number of commands received in queue 3 */ #define USDM_REG_NUM_OF_Q3_CMD … /* [ST 32] The number of commands received in queue 4 */ #define USDM_REG_NUM_OF_Q4_CMD … /* [ST 32] The number of commands received in queue 5 */ #define USDM_REG_NUM_OF_Q5_CMD … /* [ST 32] The number of commands received in queue 6 */ #define USDM_REG_NUM_OF_Q6_CMD … /* [ST 32] The number of commands received in queue 7 */ #define USDM_REG_NUM_OF_Q7_CMD … /* [ST 32] The number of commands received in queue 8 */ #define USDM_REG_NUM_OF_Q8_CMD … /* [ST 32] The number of commands received in queue 9 */ #define USDM_REG_NUM_OF_Q9_CMD … /* [RW 13] The start address in the internal RAM for the packet end message */ #define USDM_REG_PCK_END_MSG_START_ADDR … /* [RW 13] The start address in the internal RAM for queue counters */ #define USDM_REG_Q_COUNTER_START_ADDR … /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY … /* [R 1] parser fifo empty in sdm_sync block */ #define USDM_REG_SYNC_PARSER_EMPTY … /* [R 1] parser serial fifo empty in sdm_sync block */ #define USDM_REG_SYNC_SYNC_EMPTY … /* [RW 32] Tick for timer counter. Applicable only when ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */ #define USDM_REG_TIMER_TICK … /* [RW 32] Interrupt mask register #0 read/write */ #define USDM_REG_USDM_INT_MASK_0 … #define USDM_REG_USDM_INT_MASK_1 … /* [R 32] Interrupt register #0 read */ #define USDM_REG_USDM_INT_STS_0 … #define USDM_REG_USDM_INT_STS_1 … /* [RW 11] Parity mask register #0 read/write */ #define USDM_REG_USDM_PRTY_MASK … /* [R 11] Parity register #0 read */ #define USDM_REG_USDM_PRTY_STS … /* [RC 11] Parity register #0 read clear */ #define USDM_REG_USDM_PRTY_STS_CLR … /* [RW 5] The number of time_slots in the arbitration cycle */ #define USEM_REG_ARB_CYCLE_SIZE … /* [RW 3] The source that is associated with arbitration element 0. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2 */ #define USEM_REG_ARB_ELEMENT0 … /* [RW 3] The source that is associated with arbitration element 1. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~usem_registers_arb_element0.arb_element0 */ #define USEM_REG_ARB_ELEMENT1 … /* [RW 3] The source that is associated with arbitration element 2. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~usem_registers_arb_element0.arb_element0 and ~usem_registers_arb_element1.arb_element1 */ #define USEM_REG_ARB_ELEMENT2 … /* [RW 3] The source that is associated with arbitration element 3. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2.Could not be equal to register ~usem_registers_arb_element0.arb_element0 and ~usem_registers_arb_element1.arb_element1 and ~usem_registers_arb_element2.arb_element2 */ #define USEM_REG_ARB_ELEMENT3 … /* [RW 3] The source that is associated with arbitration element 4. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~usem_registers_arb_element0.arb_element0 and ~usem_registers_arb_element1.arb_element1 and ~usem_registers_arb_element2.arb_element2 and ~usem_registers_arb_element3.arb_element3 */ #define USEM_REG_ARB_ELEMENT4 … #define USEM_REG_ENABLE_IN … #define USEM_REG_ENABLE_OUT … /* [RW 32] This address space contains all registers and memories that are placed in SEM_FAST block. The SEM_FAST registers are described in appendix B. In order to access the sem_fast registers the base address ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ #define USEM_REG_FAST_MEMORY … /* [RW 1] Disables input messages from FIC0 May be updated during run_time by the microcode */ #define USEM_REG_FIC0_DISABLE … /* [RW 1] Disables input messages from FIC1 May be updated during run_time by the microcode */ #define USEM_REG_FIC1_DISABLE … /* [RW 15] Interrupt table Read and write access to it is not possible in the middle of the work */ #define USEM_REG_INT_TABLE … /* [ST 24] Statistics register. The number of messages that entered through FIC0 */ #define USEM_REG_MSG_NUM_FIC0 … /* [ST 24] Statistics register. The number of messages that entered through FIC1 */ #define USEM_REG_MSG_NUM_FIC1 … /* [ST 24] Statistics register. The number of messages that were sent to FOC0 */ #define USEM_REG_MSG_NUM_FOC0 … /* [ST 24] Statistics register. The number of messages that were sent to FOC1 */ #define USEM_REG_MSG_NUM_FOC1 … /* [ST 24] Statistics register. The number of messages that were sent to FOC2 */ #define USEM_REG_MSG_NUM_FOC2 … /* [ST 24] Statistics register. The number of messages that were sent to FOC3 */ #define USEM_REG_MSG_NUM_FOC3 … /* [RW 1] Disables input messages from the passive buffer May be updated during run_time by the microcode */ #define USEM_REG_PAS_DISABLE … /* [WB 128] Debug only. Passive buffer memory */ #define USEM_REG_PASSIVE_BUFFER … /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ #define USEM_REG_PRAM … /* [R 16] Valid sleeping threads indication have bit per thread */ #define USEM_REG_SLEEP_THREADS_VALID … /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ #define USEM_REG_SLOW_EXT_STORE_EMPTY … /* [RW 16] List of free threads . There is a bit per thread. */ #define USEM_REG_THREADS_LIST … /* [RW 3] The arbitration scheme of time_slot 0 */ #define USEM_REG_TS_0_AS … /* [RW 3] The arbitration scheme of time_slot 10 */ #define USEM_REG_TS_10_AS … /* [RW 3] The arbitration scheme of time_slot 11 */ #define USEM_REG_TS_11_AS … /* [RW 3] The arbitration scheme of time_slot 12 */ #define USEM_REG_TS_12_AS … /* [RW 3] The arbitration scheme of time_slot 13 */ #define USEM_REG_TS_13_AS … /* [RW 3] The arbitration scheme of time_slot 14 */ #define USEM_REG_TS_14_AS … /* [RW 3] The arbitration scheme of time_slot 15 */ #define USEM_REG_TS_15_AS … /* [RW 3] The arbitration scheme of time_slot 16 */ #define USEM_REG_TS_16_AS … /* [RW 3] The arbitration scheme of time_slot 17 */ #define USEM_REG_TS_17_AS … /* [RW 3] The arbitration scheme of time_slot 18 */ #define USEM_REG_TS_18_AS … /* [RW 3] The arbitration scheme of time_slot 1 */ #define USEM_REG_TS_1_AS … /* [RW 3] The arbitration scheme of time_slot 2 */ #define USEM_REG_TS_2_AS … /* [RW 3] The arbitration scheme of time_slot 3 */ #define USEM_REG_TS_3_AS … /* [RW 3] The arbitration scheme of time_slot 4 */ #define USEM_REG_TS_4_AS … /* [RW 3] The arbitration scheme of time_slot 5 */ #define USEM_REG_TS_5_AS … /* [RW 3] The arbitration scheme of time_slot 6 */ #define USEM_REG_TS_6_AS … /* [RW 3] The arbitration scheme of time_slot 7 */ #define USEM_REG_TS_7_AS … /* [RW 3] The arbitration scheme of time_slot 8 */ #define USEM_REG_TS_8_AS … /* [RW 3] The arbitration scheme of time_slot 9 */ #define USEM_REG_TS_9_AS … /* [RW 32] Interrupt mask register #0 read/write */ #define USEM_REG_USEM_INT_MASK_0 … #define USEM_REG_USEM_INT_MASK_1 … /* [R 32] Interrupt register #0 read */ #define USEM_REG_USEM_INT_STS_0 … #define USEM_REG_USEM_INT_STS_1 … /* [RW 32] Parity mask register #0 read/write */ #define USEM_REG_USEM_PRTY_MASK_0 … #define USEM_REG_USEM_PRTY_MASK_1 … /* [R 32] Parity register #0 read */ #define USEM_REG_USEM_PRTY_STS_0 … #define USEM_REG_USEM_PRTY_STS_1 … /* [RC 32] Parity register #0 read clear */ #define USEM_REG_USEM_PRTY_STS_CLR_0 … #define USEM_REG_USEM_PRTY_STS_CLR_1 … /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ #define USEM_REG_VFPF_ERR_NUM … #define VFC_MEMORIES_RST_REG_CAM_RST … #define VFC_MEMORIES_RST_REG_RAM_RST … #define VFC_REG_MEMORIES_RST … /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits * [12:8] of the address should be the offset within the accessed LCID * context; the bits [7:0] are the accessed LCID.Example: to write to REG10 * LCID100. The RBC address should be 13'ha64. */ #define XCM_REG_AG_CTX … /* [RW 2] The queue index for registration on Aux1 counter flag. */ #define XCM_REG_AUX1_Q … /* [RW 2] Per each decision rule the queue index to register to. */ #define XCM_REG_AUX_CNT_FLG_Q_19 … /* [R 5] Used to read the XX protection CAM occupancy counter. */ #define XCM_REG_CAM_OCCUP … /* [RW 1] CDU AG read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_CDU_AG_RD_IFEN … /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input are disregarded; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_CDU_AG_WR_IFEN … /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_CDU_SM_RD_IFEN … /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid input is disregarded; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_CDU_SM_WR_IFEN … /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 1 at start-up. */ #define XCM_REG_CFC_INIT_CRD … /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define XCM_REG_CP_WEIGHT … /* [RW 1] Input csem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_CSEM_IFEN … /* [RC 1] Set at message length mismatch (relative to last indication) at the csem interface. */ #define XCM_REG_CSEM_LENGTH_MIS … /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define XCM_REG_CSEM_WEIGHT … /* [RW 1] Input dorq Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_DORQ_IFEN … /* [RC 1] Set at message length mismatch (relative to last indication) at the dorq interface. */ #define XCM_REG_DORQ_LENGTH_MIS … /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define XCM_REG_DORQ_WEIGHT … /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */ #define XCM_REG_ERR_EVNT_ID … /* [RW 28] The CM erroneous header for QM and Timers formatting. */ #define XCM_REG_ERR_XCM_HDR … /* [RW 8] The Event ID for Timers expiration. */ #define XCM_REG_EXPR_EVNT_ID … /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 64 at start-up. */ #define XCM_REG_FIC0_INIT_CRD … /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 64 at start-up. */ #define XCM_REG_FIC1_INIT_CRD … #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 … #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 … #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 … #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 … /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr; ~xcm_registers_gr_ld0_pr.gr_ld0_pr and ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */ #define XCM_REG_GR_ARB_TYPE … /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Channel group is the complement of the other 3 groups. */ #define XCM_REG_GR_LD0_PR … /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the highest priority is 3. It is supposed that the Channel group is the complement of the other 3 groups. */ #define XCM_REG_GR_LD1_PR … /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_NIG0_IFEN … /* [RC 1] Set at message length mismatch (relative to last indication) at the nig0 interface. */ #define XCM_REG_NIG0_LENGTH_MIS … /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define XCM_REG_NIG0_WEIGHT … /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_NIG1_IFEN … /* [RC 1] Set at message length mismatch (relative to last indication) at the nig1 interface. */ #define XCM_REG_NIG1_LENGTH_MIS … /* [RW 5] The number of double REG-pairs; loaded from the STORM context and sent to STORM; for a specific connection type. The double REG-pairs are used in order to align to STORM context row size of 128 bits. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 16). */ #define XCM_REG_N_SM_CTX_LD_0 … #define XCM_REG_N_SM_CTX_LD_1 … #define XCM_REG_N_SM_CTX_LD_2 … #define XCM_REG_N_SM_CTX_LD_3 … #define XCM_REG_N_SM_CTX_LD_4 … #define XCM_REG_N_SM_CTX_LD_5 … /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_PBF_IFEN … /* [RC 1] Set at message length mismatch (relative to last indication) at the pbf interface. */ #define XCM_REG_PBF_LENGTH_MIS … /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define XCM_REG_PBF_WEIGHT … #define XCM_REG_PHYS_QNUM3_0 … #define XCM_REG_PHYS_QNUM3_1 … /* [RW 8] The Event ID for Timers formatting in case of stop done. */ #define XCM_REG_STOP_EVNT_ID … /* [RC 1] Set at message length mismatch (relative to last indication) at the STORM interface. */ #define XCM_REG_STORM_LENGTH_MIS … /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define XCM_REG_STORM_WEIGHT … /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_STORM_XCM_IFEN … /* [RW 4] Timers output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 4 at start-up. */ #define XCM_REG_TM_INIT_CRD … /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define XCM_REG_TM_WEIGHT … /* [RW 28] The CM header for Timers expiration command. */ #define XCM_REG_TM_XCM_HDR … /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_TM_XCM_IFEN … /* [RW 1] Input tsem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_TSEM_IFEN … /* [RC 1] Set at message length mismatch (relative to last indication) at the tsem interface. */ #define XCM_REG_TSEM_LENGTH_MIS … /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define XCM_REG_TSEM_WEIGHT … /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */ #define XCM_REG_UNA_GT_NXT_Q … /* [RW 1] Input usem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_USEM_IFEN … /* [RC 1] Message length mismatch (relative to last indication) at the usem interface. */ #define XCM_REG_USEM_LENGTH_MIS … /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define XCM_REG_USEM_WEIGHT … #define XCM_REG_WU_DA_CNT_CMD00 … #define XCM_REG_WU_DA_CNT_CMD01 … #define XCM_REG_WU_DA_CNT_CMD10 … #define XCM_REG_WU_DA_CNT_CMD11 … #define XCM_REG_WU_DA_CNT_UPD_VAL00 … #define XCM_REG_WU_DA_CNT_UPD_VAL01 … #define XCM_REG_WU_DA_CNT_UPD_VAL10 … #define XCM_REG_WU_DA_CNT_UPD_VAL11 … #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 … #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 … #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 … #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 … /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_XCM_CFC_IFEN … /* [RW 14] Interrupt mask register #0 read/write */ #define XCM_REG_XCM_INT_MASK … /* [R 14] Interrupt register #0 read */ #define XCM_REG_XCM_INT_STS … /* [RW 30] Parity mask register #0 read/write */ #define XCM_REG_XCM_PRTY_MASK … /* [R 30] Parity register #0 read */ #define XCM_REG_XCM_PRTY_STS … /* [RC 30] Parity register #0 read clear */ #define XCM_REG_XCM_PRTY_STS_CLR … /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). Is used to determine the number of the AG context REG-pairs written back; when the Reg1WbFlg isn't set. */ #define XCM_REG_XCM_REG0_SZ … /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_XCM_STORM0_IFEN … /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_XCM_STORM1_IFEN … /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_XCM_TM_IFEN … /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_XCM_XQM_IFEN … /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ #define XCM_REG_XCM_XQM_USE_Q … /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */ #define XCM_REG_XQM_BYP_ACT_UPD … /* [RW 6] QM output initial credit. Max credit available - 32.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 32 at start-up. */ #define XCM_REG_XQM_INIT_CRD … /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define XCM_REG_XQM_P_WEIGHT … /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define XCM_REG_XQM_S_WEIGHT … /* [RW 28] The CM header value for QM request (primary). */ #define XCM_REG_XQM_XCM_HDR_P … /* [RW 28] The CM header value for QM request (secondary). */ #define XCM_REG_XQM_XCM_HDR_S … /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_XQM_XCM_IFEN … /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity. */ #define XCM_REG_XSDM_IFEN … /* [RC 1] Set at message length mismatch (relative to last indication) at the SDM interface. */ #define XCM_REG_XSDM_LENGTH_MIS … /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2; tc. */ #define XCM_REG_XSDM_WEIGHT … /* [RW 17] Indirect access to the descriptor table of the XX protection mechanism. The fields are: [5:0] - message length; 11:6] - message pointer; 16:12] - next pointer. */ #define XCM_REG_XX_DESCR_TABLE … #define XCM_REG_XX_DESCR_TABLE_SIZE … /* [R 6] Used to read the XX protection Free counter. */ #define XCM_REG_XX_FREE … /* [RW 6] Initial value for the credit counter; responsible for fulfilling of the Input Stage XX protection buffer by the XX protection pending messages. Max credit available - 3.Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 2 at start-up. */ #define XCM_REG_XX_INIT_CRD … /* [RW 6] The maximum number of pending messages; which may be stored in XX protection. ~xcm_registers_xx_free.xx_free read on read. */ #define XCM_REG_XX_MSG_NUM … /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ #define XCM_REG_XX_OVFL_EVNT_ID … #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS … #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS … #define XMAC_CTRL_REG_LINE_LOCAL_LPBK … #define XMAC_CTRL_REG_RX_EN … #define XMAC_CTRL_REG_SOFT_RESET … #define XMAC_CTRL_REG_TX_EN … #define XMAC_CTRL_REG_XLGMII_ALIGN_ENB … #define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN … #define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN … #define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON … #define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN … #define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN … #define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN … #define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN … #define XMAC_REG_CLEAR_RX_LSS_STATUS … #define XMAC_REG_CTRL … /* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC * packets transmitted by the MAC */ #define XMAC_REG_CTRL_SA_HI … /* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC * packets transmitted by the MAC */ #define XMAC_REG_CTRL_SA_LO … #define XMAC_REG_EEE_CTRL … #define XMAC_REG_EEE_TIMERS_HI … #define XMAC_REG_PAUSE_CTRL … #define XMAC_REG_PFC_CTRL … #define XMAC_REG_PFC_CTRL_HI … #define XMAC_REG_RX_LSS_CTRL … #define XMAC_REG_RX_LSS_STATUS … /* [RW 14] Maximum packet size in receive direction; exclusive of preamble & * CRC in strip mode */ #define XMAC_REG_RX_MAX_SIZE … #define XMAC_REG_TX_CTRL … #define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE … #define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE … /* [RW 16] Indirect access to the XX table of the XX protection mechanism. The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] - header pointer. */ #define XCM_REG_XX_TABLE … /* [RW 8] The event id for aggregated interrupt 0 */ #define XSDM_REG_AGG_INT_EVENT_0 … #define XSDM_REG_AGG_INT_EVENT_1 … #define XSDM_REG_AGG_INT_EVENT_10 … #define XSDM_REG_AGG_INT_EVENT_11 … #define XSDM_REG_AGG_INT_EVENT_12 … #define XSDM_REG_AGG_INT_EVENT_13 … #define XSDM_REG_AGG_INT_EVENT_14 … #define XSDM_REG_AGG_INT_EVENT_2 … #define XSDM_REG_AGG_INT_EVENT_3 … #define XSDM_REG_AGG_INT_EVENT_4 … #define XSDM_REG_AGG_INT_EVENT_5 … #define XSDM_REG_AGG_INT_EVENT_6 … #define XSDM_REG_AGG_INT_EVENT_7 … #define XSDM_REG_AGG_INT_EVENT_8 … #define XSDM_REG_AGG_INT_EVENT_9 … /* [RW 1] For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1) */ #define XSDM_REG_AGG_INT_MODE_0 … #define XSDM_REG_AGG_INT_MODE_1 … /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ #define XSDM_REG_CFC_RSP_START_ADDR … /* [RW 16] The maximum value of the completion counter #0 */ #define XSDM_REG_CMP_COUNTER_MAX0 … /* [RW 16] The maximum value of the completion counter #1 */ #define XSDM_REG_CMP_COUNTER_MAX1 … /* [RW 16] The maximum value of the completion counter #2 */ #define XSDM_REG_CMP_COUNTER_MAX2 … /* [RW 16] The maximum value of the completion counter #3 */ #define XSDM_REG_CMP_COUNTER_MAX3 … /* [RW 13] The start address in the internal RAM for the completion counters. */ #define XSDM_REG_CMP_COUNTER_START_ADDR … #define XSDM_REG_ENABLE_IN1 … #define XSDM_REG_ENABLE_IN2 … #define XSDM_REG_ENABLE_OUT1 … #define XSDM_REG_ENABLE_OUT2 … /* [RW 4] The initial number of messages that can be sent to the pxp control interface without receiving any ACK. */ #define XSDM_REG_INIT_CREDIT_PXP_CTRL … /* [ST 32] The number of ACK after placement messages received */ #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE … /* [ST 32] The number of packet end messages received from the parser */ #define XSDM_REG_NUM_OF_PKT_END_MSG … /* [ST 32] The number of requests received from the pxp async if */ #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ … /* [ST 32] The number of commands received in queue 0 */ #define XSDM_REG_NUM_OF_Q0_CMD … /* [ST 32] The number of commands received in queue 10 */ #define XSDM_REG_NUM_OF_Q10_CMD … /* [ST 32] The number of commands received in queue 11 */ #define XSDM_REG_NUM_OF_Q11_CMD … /* [ST 32] The number of commands received in queue 1 */ #define XSDM_REG_NUM_OF_Q1_CMD … /* [ST 32] The number of commands received in queue 3 */ #define XSDM_REG_NUM_OF_Q3_CMD … /* [ST 32] The number of commands received in queue 4 */ #define XSDM_REG_NUM_OF_Q4_CMD … /* [ST 32] The number of commands received in queue 5 */ #define XSDM_REG_NUM_OF_Q5_CMD … /* [ST 32] The number of commands received in queue 6 */ #define XSDM_REG_NUM_OF_Q6_CMD … /* [ST 32] The number of commands received in queue 7 */ #define XSDM_REG_NUM_OF_Q7_CMD … /* [ST 32] The number of commands received in queue 8 */ #define XSDM_REG_NUM_OF_Q8_CMD … /* [ST 32] The number of commands received in queue 9 */ #define XSDM_REG_NUM_OF_Q9_CMD … /* [RW 13] The start address in the internal RAM for queue counters */ #define XSDM_REG_Q_COUNTER_START_ADDR … /* [W 17] Generate an operation after completion; bit-16 is * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and * bits 4:0 are the T124Param[4:0] */ #define XSDM_REG_OPERATION_GEN … /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY … /* [R 1] parser fifo empty in sdm_sync block */ #define XSDM_REG_SYNC_PARSER_EMPTY … /* [R 1] parser serial fifo empty in sdm_sync block */ #define XSDM_REG_SYNC_SYNC_EMPTY … /* [RW 32] Tick for timer counter. Applicable only when ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */ #define XSDM_REG_TIMER_TICK … /* [RW 32] Interrupt mask register #0 read/write */ #define XSDM_REG_XSDM_INT_MASK_0 … #define XSDM_REG_XSDM_INT_MASK_1 … /* [R 32] Interrupt register #0 read */ #define XSDM_REG_XSDM_INT_STS_0 … #define XSDM_REG_XSDM_INT_STS_1 … /* [RW 11] Parity mask register #0 read/write */ #define XSDM_REG_XSDM_PRTY_MASK … /* [R 11] Parity register #0 read */ #define XSDM_REG_XSDM_PRTY_STS … /* [RC 11] Parity register #0 read clear */ #define XSDM_REG_XSDM_PRTY_STS_CLR … /* [RW 5] The number of time_slots in the arbitration cycle */ #define XSEM_REG_ARB_CYCLE_SIZE … /* [RW 3] The source that is associated with arbitration element 0. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2 */ #define XSEM_REG_ARB_ELEMENT0 … /* [RW 3] The source that is associated with arbitration element 1. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */ #define XSEM_REG_ARB_ELEMENT1 … /* [RW 3] The source that is associated with arbitration element 2. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~xsem_registers_arb_element0.arb_element0 and ~xsem_registers_arb_element1.arb_element1 */ #define XSEM_REG_ARB_ELEMENT2 … /* [RW 3] The source that is associated with arbitration element 3. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2.Could not be equal to register ~xsem_registers_arb_element0.arb_element0 and ~xsem_registers_arb_element1.arb_element1 and ~xsem_registers_arb_element2.arb_element2 */ #define XSEM_REG_ARB_ELEMENT3 … /* [RW 3] The source that is associated with arbitration element 4. Source decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- sleeping thread with priority 1; 4- sleeping thread with priority 2. Could not be equal to register ~xsem_registers_arb_element0.arb_element0 and ~xsem_registers_arb_element1.arb_element1 and ~xsem_registers_arb_element2.arb_element2 and ~xsem_registers_arb_element3.arb_element3 */ #define XSEM_REG_ARB_ELEMENT4 … #define XSEM_REG_ENABLE_IN … #define XSEM_REG_ENABLE_OUT … /* [RW 32] This address space contains all registers and memories that are placed in SEM_FAST block. The SEM_FAST registers are described in appendix B. In order to access the sem_fast registers the base address ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ #define XSEM_REG_FAST_MEMORY … /* [RW 1] Disables input messages from FIC0 May be updated during run_time by the microcode */ #define XSEM_REG_FIC0_DISABLE … /* [RW 1] Disables input messages from FIC1 May be updated during run_time by the microcode */ #define XSEM_REG_FIC1_DISABLE … /* [RW 15] Interrupt table Read and write access to it is not possible in the middle of the work */ #define XSEM_REG_INT_TABLE … /* [ST 24] Statistics register. The number of messages that entered through FIC0 */ #define XSEM_REG_MSG_NUM_FIC0 … /* [ST 24] Statistics register. The number of messages that entered through FIC1 */ #define XSEM_REG_MSG_NUM_FIC1 … /* [ST 24] Statistics register. The number of messages that were sent to FOC0 */ #define XSEM_REG_MSG_NUM_FOC0 … /* [ST 24] Statistics register. The number of messages that were sent to FOC1 */ #define XSEM_REG_MSG_NUM_FOC1 … /* [ST 24] Statistics register. The number of messages that were sent to FOC2 */ #define XSEM_REG_MSG_NUM_FOC2 … /* [ST 24] Statistics register. The number of messages that were sent to FOC3 */ #define XSEM_REG_MSG_NUM_FOC3 … /* [RW 1] Disables input messages from the passive buffer May be updated during run_time by the microcode */ #define XSEM_REG_PAS_DISABLE … /* [WB 128] Debug only. Passive buffer memory */ #define XSEM_REG_PASSIVE_BUFFER … /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ #define XSEM_REG_PRAM … /* [R 16] Valid sleeping threads indication have bit per thread */ #define XSEM_REG_SLEEP_THREADS_VALID … /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ #define XSEM_REG_SLOW_EXT_STORE_EMPTY … /* [RW 16] List of free threads . There is a bit per thread. */ #define XSEM_REG_THREADS_LIST … /* [RW 3] The arbitration scheme of time_slot 0 */ #define XSEM_REG_TS_0_AS … /* [RW 3] The arbitration scheme of time_slot 10 */ #define XSEM_REG_TS_10_AS … /* [RW 3] The arbitration scheme of time_slot 11 */ #define XSEM_REG_TS_11_AS … /* [RW 3] The arbitration scheme of time_slot 12 */ #define XSEM_REG_TS_12_AS … /* [RW 3] The arbitration scheme of time_slot 13 */ #define XSEM_REG_TS_13_AS … /* [RW 3] The arbitration scheme of time_slot 14 */ #define XSEM_REG_TS_14_AS … /* [RW 3] The arbitration scheme of time_slot 15 */ #define XSEM_REG_TS_15_AS … /* [RW 3] The arbitration scheme of time_slot 16 */ #define XSEM_REG_TS_16_AS … /* [RW 3] The arbitration scheme of time_slot 17 */ #define XSEM_REG_TS_17_AS … /* [RW 3] The arbitration scheme of time_slot 18 */ #define XSEM_REG_TS_18_AS … /* [RW 3] The arbitration scheme of time_slot 1 */ #define XSEM_REG_TS_1_AS … /* [RW 3] The arbitration scheme of time_slot 2 */ #define XSEM_REG_TS_2_AS … /* [RW 3] The arbitration scheme of time_slot 3 */ #define XSEM_REG_TS_3_AS … /* [RW 3] The arbitration scheme of time_slot 4 */ #define XSEM_REG_TS_4_AS … /* [RW 3] The arbitration scheme of time_slot 5 */ #define XSEM_REG_TS_5_AS … /* [RW 3] The arbitration scheme of time_slot 6 */ #define XSEM_REG_TS_6_AS … /* [RW 3] The arbitration scheme of time_slot 7 */ #define XSEM_REG_TS_7_AS … /* [RW 3] The arbitration scheme of time_slot 8 */ #define XSEM_REG_TS_8_AS … /* [RW 3] The arbitration scheme of time_slot 9 */ #define XSEM_REG_TS_9_AS … /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ #define XSEM_REG_VFPF_ERR_NUM … /* [RW 32] Interrupt mask register #0 read/write */ #define XSEM_REG_XSEM_INT_MASK_0 … #define XSEM_REG_XSEM_INT_MASK_1 … /* [R 32] Interrupt register #0 read */ #define XSEM_REG_XSEM_INT_STS_0 … #define XSEM_REG_XSEM_INT_STS_1 … /* [RW 32] Parity mask register #0 read/write */ #define XSEM_REG_XSEM_PRTY_MASK_0 … #define XSEM_REG_XSEM_PRTY_MASK_1 … /* [R 32] Parity register #0 read */ #define XSEM_REG_XSEM_PRTY_STS_0 … #define XSEM_REG_XSEM_PRTY_STS_1 … /* [RC 32] Parity register #0 read clear */ #define XSEM_REG_XSEM_PRTY_STS_CLR_0 … #define XSEM_REG_XSEM_PRTY_STS_CLR_1 … #define MCPR_ACCESS_LOCK_LOCK … #define MCPR_NVM_ACCESS_ENABLE_EN … #define MCPR_NVM_ACCESS_ENABLE_WR_EN … #define MCPR_NVM_ADDR_NVM_ADDR_VALUE … #define MCPR_NVM_CFG4_FLASH_SIZE … #define MCPR_NVM_COMMAND_DOIT … #define MCPR_NVM_COMMAND_DONE … #define MCPR_NVM_COMMAND_FIRST … #define MCPR_NVM_COMMAND_LAST … #define MCPR_NVM_COMMAND_WR … #define MCPR_NVM_SW_ARB_ARB_ARB1 … #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 … #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 … #define BIGMAC_REGISTER_BMAC_CONTROL … #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL … #define BIGMAC_REGISTER_CNT_MAX_SIZE … #define BIGMAC_REGISTER_RX_CONTROL … #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS … #define BIGMAC_REGISTER_RX_LSS_STATUS … #define BIGMAC_REGISTER_RX_MAX_SIZE … #define BIGMAC_REGISTER_RX_STAT_GR64 … #define BIGMAC_REGISTER_RX_STAT_GRIPJ … #define BIGMAC_REGISTER_TX_CONTROL … #define BIGMAC_REGISTER_TX_MAX_SIZE … #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD … #define BIGMAC_REGISTER_TX_SOURCE_ADDR … #define BIGMAC_REGISTER_TX_STAT_GTBYT … #define BIGMAC_REGISTER_TX_STAT_GTPKT … #define BIGMAC2_REGISTER_BMAC_CONTROL … #define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL … #define BIGMAC2_REGISTER_CNT_MAX_SIZE … #define BIGMAC2_REGISTER_PFC_CONTROL … #define BIGMAC2_REGISTER_RX_CONTROL … #define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS … #define BIGMAC2_REGISTER_RX_LSS_STAT … #define BIGMAC2_REGISTER_RX_MAX_SIZE … #define BIGMAC2_REGISTER_RX_STAT_GR64 … #define BIGMAC2_REGISTER_RX_STAT_GRIPJ … #define BIGMAC2_REGISTER_RX_STAT_GRPP … #define BIGMAC2_REGISTER_TX_CONTROL … #define BIGMAC2_REGISTER_TX_MAX_SIZE … #define BIGMAC2_REGISTER_TX_PAUSE_CONTROL … #define BIGMAC2_REGISTER_TX_SOURCE_ADDR … #define BIGMAC2_REGISTER_TX_STAT_GTBYT … #define BIGMAC2_REGISTER_TX_STAT_GTPOK … #define BIGMAC2_REGISTER_TX_STAT_GTPP … #define EMAC_LED_1000MB_OVERRIDE … #define EMAC_LED_100MB_OVERRIDE … #define EMAC_LED_10MB_OVERRIDE … #define EMAC_LED_2500MB_OVERRIDE … #define EMAC_LED_OVERRIDE … #define EMAC_LED_TRAFFIC … #define EMAC_MDIO_COMM_COMMAND_ADDRESS … #define EMAC_MDIO_COMM_COMMAND_READ_22 … #define EMAC_MDIO_COMM_COMMAND_READ_45 … #define EMAC_MDIO_COMM_COMMAND_WRITE_22 … #define EMAC_MDIO_COMM_COMMAND_WRITE_45 … #define EMAC_MDIO_COMM_DATA … #define EMAC_MDIO_COMM_START_BUSY … #define EMAC_MDIO_MODE_AUTO_POLL … #define EMAC_MDIO_MODE_CLAUSE_45 … #define EMAC_MDIO_MODE_CLOCK_CNT … #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT … #define EMAC_MDIO_STATUS_10MB … #define EMAC_MODE_25G_MODE … #define EMAC_MODE_HALF_DUPLEX … #define EMAC_MODE_PORT_GMII … #define EMAC_MODE_PORT_MII … #define EMAC_MODE_PORT_MII_10M … #define EMAC_MODE_RESET … #define EMAC_REG_EMAC_LED … #define EMAC_REG_EMAC_MAC_MATCH … #define EMAC_REG_EMAC_MDIO_COMM … #define EMAC_REG_EMAC_MDIO_MODE … #define EMAC_REG_EMAC_MDIO_STATUS … #define EMAC_REG_EMAC_MODE … #define EMAC_REG_EMAC_RX_MODE … #define EMAC_REG_EMAC_RX_MTU_SIZE … #define EMAC_REG_EMAC_RX_STAT_AC … #define EMAC_REG_EMAC_RX_STAT_AC_28 … #define EMAC_REG_EMAC_RX_STAT_AC_COUNT … #define EMAC_REG_EMAC_TX_MODE … #define EMAC_REG_EMAC_TX_STAT_AC … #define EMAC_REG_EMAC_TX_STAT_AC_COUNT … #define EMAC_REG_RX_PFC_MODE … #define EMAC_REG_RX_PFC_MODE_PRIORITIES … #define EMAC_REG_RX_PFC_MODE_RX_EN … #define EMAC_REG_RX_PFC_MODE_TX_EN … #define EMAC_REG_RX_PFC_PARAM … #define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT … #define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT … #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD … #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT … #define EMAC_REG_RX_PFC_STATS_XOFF_SENT … #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT … #define EMAC_REG_RX_PFC_STATS_XON_RCVD … #define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT … #define EMAC_REG_RX_PFC_STATS_XON_SENT … #define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT … #define EMAC_RX_MODE_FLOW_EN … #define EMAC_RX_MODE_KEEP_MAC_CONTROL … #define EMAC_RX_MODE_KEEP_VLAN_TAG … #define EMAC_RX_MODE_PROMISCUOUS … #define EMAC_RX_MODE_RESET … #define EMAC_RX_MTU_SIZE_JUMBO_ENA … #define EMAC_TX_MODE_EXT_PAUSE_EN … #define EMAC_TX_MODE_FLOW_EN … #define EMAC_TX_MODE_RESET … #define MISC_REGISTERS_GPIO_0 … #define MISC_REGISTERS_GPIO_1 … #define MISC_REGISTERS_GPIO_2 … #define MISC_REGISTERS_GPIO_3 … #define MISC_REGISTERS_GPIO_CLR_POS … #define MISC_REGISTERS_GPIO_FLOAT … #define MISC_REGISTERS_GPIO_FLOAT_POS … #define MISC_REGISTERS_GPIO_HIGH … #define MISC_REGISTERS_GPIO_INPUT_HI_Z … #define MISC_REGISTERS_GPIO_INT_CLR_POS … #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR … #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET … #define MISC_REGISTERS_GPIO_INT_SET_POS … #define MISC_REGISTERS_GPIO_LOW … #define MISC_REGISTERS_GPIO_OUTPUT_HIGH … #define MISC_REGISTERS_GPIO_OUTPUT_LOW … #define MISC_REGISTERS_GPIO_PORT_SHIFT … #define MISC_REGISTERS_GPIO_SET_POS … #define MISC_REGISTERS_RESET_REG_1_CLEAR … #define MISC_REGISTERS_RESET_REG_1_RST_BRB1 … #define MISC_REGISTERS_RESET_REG_1_RST_DORQ … #define MISC_REGISTERS_RESET_REG_1_RST_HC … #define MISC_REGISTERS_RESET_REG_1_RST_NIG … #define MISC_REGISTERS_RESET_REG_1_RST_PXP … #define MISC_REGISTERS_RESET_REG_1_RST_PXPV … #define MISC_REGISTERS_RESET_REG_1_RST_XSEM … #define MISC_REGISTERS_RESET_REG_1_SET … #define MISC_REGISTERS_RESET_REG_2_CLEAR … #define MISC_REGISTERS_RESET_REG_2_MSTAT0 … #define MISC_REGISTERS_RESET_REG_2_MSTAT1 … #define MISC_REGISTERS_RESET_REG_2_PGLC … #define MISC_REGISTERS_RESET_REG_2_RST_ATC … #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 … #define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 … #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 … #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE … #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 … #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE … #define MISC_REGISTERS_RESET_REG_2_RST_GRC … #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B … #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE … #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU … #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE … #define MISC_REGISTERS_RESET_REG_2_RST_MDIO … #define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE … #define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO … #define MISC_REGISTERS_RESET_REG_2_RST_RBCN … #define MISC_REGISTERS_RESET_REG_2_SET … #define MISC_REGISTERS_RESET_REG_2_UMAC0 … #define MISC_REGISTERS_RESET_REG_2_UMAC1 … #define MISC_REGISTERS_RESET_REG_2_XMAC … #define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT … #define MISC_REGISTERS_RESET_REG_3_CLEAR … #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ … #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN … #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD … #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW … #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ … #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN … #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD … #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW … #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB … #define MISC_REGISTERS_RESET_REG_3_SET … #define MISC_REGISTERS_SPIO_4 … #define MISC_REGISTERS_SPIO_5 … #define MISC_REGISTERS_SPIO_7 … #define MISC_REGISTERS_SPIO_CLR_POS … #define MISC_REGISTERS_SPIO_FLOAT … #define MISC_REGISTERS_SPIO_FLOAT_POS … #define MISC_REGISTERS_SPIO_INPUT_HI_Z … #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS … #define MISC_REGISTERS_SPIO_OUTPUT_HIGH … #define MISC_REGISTERS_SPIO_OUTPUT_LOW … #define MISC_REGISTERS_SPIO_SET_POS … #define MISC_SPIO_CLR_POS … #define MISC_SPIO_FLOAT … #define MISC_SPIO_FLOAT_POS … #define MISC_SPIO_INPUT_HI_Z … #define MISC_SPIO_INT_OLD_SET_POS … #define MISC_SPIO_OUTPUT_HIGH … #define MISC_SPIO_OUTPUT_LOW … #define MISC_SPIO_SET_POS … #define MISC_SPIO_SPIO4 … #define MISC_SPIO_SPIO5 … #define HW_LOCK_MAX_RESOURCE_VALUE … #define HW_LOCK_RESOURCE_DCBX_ADMIN_MIB … #define HW_LOCK_RESOURCE_DRV_FLAGS … #define HW_LOCK_RESOURCE_GPIO … #define HW_LOCK_RESOURCE_MDIO … #define HW_LOCK_RESOURCE_NVRAM … #define HW_LOCK_RESOURCE_PORT0_ATT_MASK … #define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 … #define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 … #define HW_LOCK_RESOURCE_RECOVERY_REG … #define HW_LOCK_RESOURCE_RESET … #define HW_LOCK_RESOURCE_SPIO … #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 … #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY … #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY … #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY … #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY … #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_SPIO5 … #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT … #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR … #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 … #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 … #define RESERVED_GENERAL_ATTENTION_BIT_0 … #define EVEREST_GEN_ATTN_IN_USE_MASK … #define EVEREST_LATCHED_ATTN_IN_USE_MASK … #define RESERVED_GENERAL_ATTENTION_BIT_6 … #define RESERVED_GENERAL_ATTENTION_BIT_7 … #define RESERVED_GENERAL_ATTENTION_BIT_8 … #define RESERVED_GENERAL_ATTENTION_BIT_9 … #define RESERVED_GENERAL_ATTENTION_BIT_10 … #define RESERVED_GENERAL_ATTENTION_BIT_11 … #define RESERVED_GENERAL_ATTENTION_BIT_12 … #define RESERVED_GENERAL_ATTENTION_BIT_13 … #define RESERVED_GENERAL_ATTENTION_BIT_14 … #define RESERVED_GENERAL_ATTENTION_BIT_15 … #define RESERVED_GENERAL_ATTENTION_BIT_16 … #define RESERVED_GENERAL_ATTENTION_BIT_17 … #define RESERVED_GENERAL_ATTENTION_BIT_18 … #define RESERVED_GENERAL_ATTENTION_BIT_19 … #define RESERVED_GENERAL_ATTENTION_BIT_20 … #define RESERVED_GENERAL_ATTENTION_BIT_21 … /* storm asserts attention bits */ #define TSTORM_FATAL_ASSERT_ATTENTION_BIT … #define USTORM_FATAL_ASSERT_ATTENTION_BIT … #define CSTORM_FATAL_ASSERT_ATTENTION_BIT … #define XSTORM_FATAL_ASSERT_ATTENTION_BIT … /* mcp error attention bit */ #define MCP_FATAL_ASSERT_ATTENTION_BIT … /*E1H NIG status sync attention mapped to group 4-7*/ #define LINK_SYNC_ATTENTION_BIT_FUNC_0 … #define LINK_SYNC_ATTENTION_BIT_FUNC_1 … #define LINK_SYNC_ATTENTION_BIT_FUNC_2 … #define LINK_SYNC_ATTENTION_BIT_FUNC_3 … #define LINK_SYNC_ATTENTION_BIT_FUNC_4 … #define LINK_SYNC_ATTENTION_BIT_FUNC_5 … #define LINK_SYNC_ATTENTION_BIT_FUNC_6 … #define LINK_SYNC_ATTENTION_BIT_FUNC_7 … #define LATCHED_ATTN_RBCR … #define LATCHED_ATTN_RBCT … #define LATCHED_ATTN_RBCN … #define LATCHED_ATTN_RBCU … #define LATCHED_ATTN_RBCP … #define LATCHED_ATTN_TIMEOUT_GRC … #define LATCHED_ATTN_RSVD_GRC … #define LATCHED_ATTN_ROM_PARITY_MCP … #define LATCHED_ATTN_UM_RX_PARITY_MCP … #define LATCHED_ATTN_UM_TX_PARITY_MCP … #define LATCHED_ATTN_SCPAD_PARITY_MCP … #define GENERAL_ATTEN_WORD(atten_name) … #define GENERAL_ATTEN_OFFSET(atten_name) … /* * This file defines GRC base address for every block. * This file is included by chipsim, asm microcode and cpp microcode. * These values are used in Design.xml on regBase attribute * Use the base with the generated offsets of specific registers. */ #define GRCBASE_PXPCS … #define GRCBASE_PCICONFIG … #define GRCBASE_PCIREG … #define GRCBASE_EMAC0 … #define GRCBASE_EMAC1 … #define GRCBASE_DBU … #define GRCBASE_MISC … #define GRCBASE_DBG … #define GRCBASE_NIG … #define GRCBASE_XCM … #define GRCBASE_PRS … #define GRCBASE_SRCH … #define GRCBASE_TSDM … #define GRCBASE_TCM … #define GRCBASE_BRB1 … #define GRCBASE_MCP … #define GRCBASE_UPB … #define GRCBASE_CSDM … #define GRCBASE_USDM … #define GRCBASE_CCM … #define GRCBASE_UCM … #define GRCBASE_CDU … #define GRCBASE_DMAE … #define GRCBASE_PXP … #define GRCBASE_CFC … #define GRCBASE_HC … #define GRCBASE_PXP2 … #define GRCBASE_PBF … #define GRCBASE_UMAC0 … #define GRCBASE_UMAC1 … #define GRCBASE_XPB … #define GRCBASE_MSTAT0 … #define GRCBASE_MSTAT1 … #define GRCBASE_XMAC0 … #define GRCBASE_XMAC1 … #define GRCBASE_TIMERS … #define GRCBASE_XSDM … #define GRCBASE_QM … #define GRCBASE_DQ … #define GRCBASE_TSEM … #define GRCBASE_CSEM … #define GRCBASE_XSEM … #define GRCBASE_USEM … #define GRCBASE_MISC_AEU … /* offset of configuration space in the pci core register */ #define PCICFG_OFFSET … #define PCICFG_VENDOR_ID_OFFSET … #define PCICFG_DEVICE_ID_OFFSET … #define PCICFG_COMMAND_OFFSET … #define PCICFG_COMMAND_IO_SPACE … #define PCICFG_COMMAND_MEM_SPACE … #define PCICFG_COMMAND_BUS_MASTER … #define PCICFG_COMMAND_SPECIAL_CYCLES … #define PCICFG_COMMAND_MWI_CYCLES … #define PCICFG_COMMAND_VGA_SNOOP … #define PCICFG_COMMAND_PERR_ENA … #define PCICFG_COMMAND_STEPPING … #define PCICFG_COMMAND_SERR_ENA … #define PCICFG_COMMAND_FAST_B2B … #define PCICFG_COMMAND_INT_DISABLE … #define PCICFG_COMMAND_RESERVED … #define PCICFG_STATUS_OFFSET … #define PCICFG_REVISION_ID_OFFSET … #define PCICFG_REVESION_ID_MASK … #define PCICFG_REVESION_ID_ERROR_VAL … #define PCICFG_CACHE_LINE_SIZE … #define PCICFG_LATENCY_TIMER … #define PCICFG_BAR_1_LOW … #define PCICFG_BAR_1_HIGH … #define PCICFG_BAR_2_LOW … #define PCICFG_BAR_2_HIGH … #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET … #define PCICFG_SUBSYSTEM_ID_OFFSET … #define PCICFG_INT_LINE … #define PCICFG_INT_PIN … #define PCICFG_PM_CAPABILITY … #define PCICFG_PM_CAPABILITY_VERSION … #define PCICFG_PM_CAPABILITY_CLOCK … #define PCICFG_PM_CAPABILITY_RESERVED … #define PCICFG_PM_CAPABILITY_DSI … #define PCICFG_PM_CAPABILITY_AUX_CURRENT … #define PCICFG_PM_CAPABILITY_D1_SUPPORT … #define PCICFG_PM_CAPABILITY_D2_SUPPORT … #define PCICFG_PM_CAPABILITY_PME_IN_D0 … #define PCICFG_PM_CAPABILITY_PME_IN_D1 … #define PCICFG_PM_CAPABILITY_PME_IN_D2 … #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT … #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD … #define PCICFG_PM_CSR_OFFSET … #define PCICFG_PM_CSR_STATE … #define PCICFG_PM_CSR_PME_ENABLE … #define PCICFG_PM_CSR_PME_STATUS … #define PCICFG_MSI_CAP_ID_OFFSET … #define PCICFG_MSI_CONTROL_ENABLE … #define PCICFG_MSI_CONTROL_MCAP … #define PCICFG_MSI_CONTROL_MENA … #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP … #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE … #define PCICFG_GRC_ADDRESS … #define PCICFG_GRC_DATA … #define PCICFG_ME_REGISTER … #define PCICFG_MSIX_CAP_ID_OFFSET … #define PCICFG_MSIX_CONTROL_TABLE_SIZE … #define PCICFG_MSIX_CONTROL_RESERVED … #define PCICFG_MSIX_CONTROL_FUNC_MASK … #define PCICFG_MSIX_CONTROL_MSIX_ENABLE … #define PCICFG_DEVICE_CONTROL … #define PCICFG_DEVICE_STATUS … #define PCICFG_DEVICE_STATUS_CORR_ERR_DET … #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET … #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET … #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET … #define PCICFG_DEVICE_STATUS_AUX_PWR_DET … #define PCICFG_DEVICE_STATUS_NO_PEND … #define PCICFG_LINK_CONTROL … #define BAR_USTRORM_INTMEM … #define BAR_CSTRORM_INTMEM … #define BAR_XSTRORM_INTMEM … #define BAR_TSTRORM_INTMEM … /* for accessing the IGU in case of status block ACK */ #define BAR_IGU_INTMEM … #define BAR_DOORBELL_OFFSET … #define BAR_ME_REGISTER … /* config_2 offset */ #define GRC_CONFIG_2_SIZE_REG … #define PCI_CONFIG_2_BAR1_SIZE … #define PCI_CONFIG_2_BAR1_SIZE_DISABLED … #define PCI_CONFIG_2_BAR1_SIZE_64K … #define PCI_CONFIG_2_BAR1_SIZE_128K … #define PCI_CONFIG_2_BAR1_SIZE_256K … #define PCI_CONFIG_2_BAR1_SIZE_512K … #define PCI_CONFIG_2_BAR1_SIZE_1M … #define PCI_CONFIG_2_BAR1_SIZE_2M … #define PCI_CONFIG_2_BAR1_SIZE_4M … #define PCI_CONFIG_2_BAR1_SIZE_8M … #define PCI_CONFIG_2_BAR1_SIZE_16M … #define PCI_CONFIG_2_BAR1_SIZE_32M … #define PCI_CONFIG_2_BAR1_SIZE_64M … #define PCI_CONFIG_2_BAR1_SIZE_128M … #define PCI_CONFIG_2_BAR1_SIZE_256M … #define PCI_CONFIG_2_BAR1_SIZE_512M … #define PCI_CONFIG_2_BAR1_SIZE_1G … #define PCI_CONFIG_2_BAR1_64ENA … #define PCI_CONFIG_2_EXP_ROM_RETRY … #define PCI_CONFIG_2_CFG_CYCLE_RETRY … #define PCI_CONFIG_2_FIRST_CFG_DONE … #define PCI_CONFIG_2_EXP_ROM_SIZE … #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED … #define PCI_CONFIG_2_EXP_ROM_SIZE_2K … #define PCI_CONFIG_2_EXP_ROM_SIZE_4K … #define PCI_CONFIG_2_EXP_ROM_SIZE_8K … #define PCI_CONFIG_2_EXP_ROM_SIZE_16K … #define PCI_CONFIG_2_EXP_ROM_SIZE_32K … #define PCI_CONFIG_2_EXP_ROM_SIZE_64K … #define PCI_CONFIG_2_EXP_ROM_SIZE_128K … #define PCI_CONFIG_2_EXP_ROM_SIZE_256K … #define PCI_CONFIG_2_EXP_ROM_SIZE_512K … #define PCI_CONFIG_2_EXP_ROM_SIZE_1M … #define PCI_CONFIG_2_EXP_ROM_SIZE_2M … #define PCI_CONFIG_2_EXP_ROM_SIZE_4M … #define PCI_CONFIG_2_EXP_ROM_SIZE_8M … #define PCI_CONFIG_2_EXP_ROM_SIZE_16M … #define PCI_CONFIG_2_EXP_ROM_SIZE_32M … #define PCI_CONFIG_2_BAR_PREFETCH … #define PCI_CONFIG_2_RESERVED0 … /* config_3 offset */ #define GRC_CONFIG_3_SIZE_REG … #define PCI_CONFIG_3_STICKY_BYTE … #define PCI_CONFIG_3_FORCE_PME … #define PCI_CONFIG_3_PME_STATUS … #define PCI_CONFIG_3_PME_ENABLE … #define PCI_CONFIG_3_PM_STATE … #define PCI_CONFIG_3_VAUX_PRESET … #define PCI_CONFIG_3_PCI_POWER … #define GRC_BAR2_CONFIG … #define PCI_CONFIG_2_BAR2_SIZE … #define PCI_CONFIG_2_BAR2_SIZE_DISABLED … #define PCI_CONFIG_2_BAR2_SIZE_64K … #define PCI_CONFIG_2_BAR2_SIZE_128K … #define PCI_CONFIG_2_BAR2_SIZE_256K … #define PCI_CONFIG_2_BAR2_SIZE_512K … #define PCI_CONFIG_2_BAR2_SIZE_1M … #define PCI_CONFIG_2_BAR2_SIZE_2M … #define PCI_CONFIG_2_BAR2_SIZE_4M … #define PCI_CONFIG_2_BAR2_SIZE_8M … #define PCI_CONFIG_2_BAR2_SIZE_16M … #define PCI_CONFIG_2_BAR2_SIZE_32M … #define PCI_CONFIG_2_BAR2_SIZE_64M … #define PCI_CONFIG_2_BAR2_SIZE_128M … #define PCI_CONFIG_2_BAR2_SIZE_256M … #define PCI_CONFIG_2_BAR2_SIZE_512M … #define PCI_CONFIG_2_BAR2_SIZE_1G … #define PCI_CONFIG_2_BAR2_64ENA … #define PCI_PM_DATA_A … #define PCI_PM_DATA_B … #define PCI_ID_VAL1 … #define PCI_ID_VAL2 … #define PCI_ID_VAL3 … #define GRC_CONFIG_REG_VF_MSIX_CONTROL … #define GRC_CONFIG_REG_PF_INIT_VF … #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK … /* First VF_NUM for PF is encoded in this register. * The number of VFs assigned to a PF is assumed to be a multiple of 8. * Software should program these bits based on Total Number of VFs \ * programmed for each PF. * Since registers from 0x000-0x7ff are split across functions, each PF will * have the same location for the same 4 bits */ #define PXPCS_TL_CONTROL_5 … #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN … #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN … #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN … #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN … #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR … #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW … #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN … #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN … #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE … #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG … #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 … #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 … #define PXPCS_TL_CONTROL_5_ERR_ECRC1 … #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 … #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 … #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 … #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 … #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 … #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 … #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 … #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT … #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT … #define PXPCS_TL_CONTROL_5_ERR_ECRC … #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP … #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW … #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL … #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT … #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT … #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL … #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP … #define PXPCS_TL_FUNC345_STAT … #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 … #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 … #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4 … #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4 … #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4 … #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4 … #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4 … #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4 … #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4 … #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4 … #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 … #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 … #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3 … #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3 … #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3 … #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3 … #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3 … #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3 … #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3 … #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3 … #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 … #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2 … #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2 … #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2 … #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2 … #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2 … #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2 … #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2 … #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2 … #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2 … #define PXPCS_TL_FUNC678_STAT … #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 … #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 … #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7 … #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7 … #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7 … #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7 … #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7 … #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7 … #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7 … #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7 … #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 … #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 … #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6 … #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6 … #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6 … #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6 … #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6 … #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6 … #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6 … #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6 … #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 … #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5 … #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5 … #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5 … #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5 … #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5 … #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5 … #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5 … #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5 … #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5 … #define BAR_USTRORM_INTMEM … #define BAR_CSTRORM_INTMEM … #define BAR_XSTRORM_INTMEM … #define BAR_TSTRORM_INTMEM … /* for accessing the IGU in case of status block ACK */ #define BAR_IGU_INTMEM … #define BAR_DOORBELL_OFFSET … #define BAR_ME_REGISTER … #define ME_REG_PF_NUM_SHIFT … #define ME_REG_PF_NUM … #define ME_REG_VF_VALID … #define ME_REG_VF_NUM_SHIFT … #define ME_REG_VF_NUM_MASK … #define ME_REG_VF_ERR … #define ME_REG_ABS_PF_NUM_SHIFT … #define ME_REG_ABS_PF_NUM … #define PXP_VF_ADDR_IGU_START … #define PXP_VF_ADDR_IGU_SIZE … #define PXP_VF_ADDR_IGU_END … #define PXP_VF_ADDR_USDM_QUEUES_START … #define PXP_VF_ADDR_USDM_QUEUES_SIZE … #define PXP_VF_ADDR_USDM_QUEUES_END … #define PXP_VF_ADDR_CSDM_GLOBAL_START … #define PXP_VF_ADDR_CSDM_GLOBAL_SIZE … #define PXP_VF_ADDR_CSDM_GLOBAL_END … #define PXP_VF_ADDR_DB_START … #define PXP_VF_ADDR_DB_SIZE … #define PXP_VF_ADDR_DB_END … #define MDIO_REG_BANK_CL73_IEEEB0 … #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL … #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN … #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN … #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST … #define MDIO_REG_BANK_CL73_IEEEB1 … #define MDIO_CL73_IEEEB1_AN_ADV1 … #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE … #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC … #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH … #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK … #define MDIO_CL73_IEEEB1_AN_ADV2 … #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M … #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX … #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 … #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR … #define MDIO_CL73_IEEEB1_AN_LP_ADV1 … #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE … #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC … #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH … #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK … #define MDIO_CL73_IEEEB1_AN_LP_ADV2 … #define MDIO_REG_BANK_RX0 … #define MDIO_RX0_RX_STATUS … #define MDIO_RX0_RX_STATUS_SIGDET … #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE … #define MDIO_RX0_RX_EQ_BOOST … #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK … #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL … #define MDIO_REG_BANK_RX1 … #define MDIO_RX1_RX_EQ_BOOST … #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK … #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL … #define MDIO_REG_BANK_RX2 … #define MDIO_RX2_RX_EQ_BOOST … #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK … #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL … #define MDIO_REG_BANK_RX3 … #define MDIO_RX3_RX_EQ_BOOST … #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK … #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL … #define MDIO_REG_BANK_RX_ALL … #define MDIO_RX_ALL_RX_EQ_BOOST … #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK … #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL … #define MDIO_REG_BANK_TX0 … #define MDIO_TX0_TX_DRIVER … #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK … #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT … #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK … #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT … #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK … #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT … #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK … #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT … #define MDIO_TX0_TX_DRIVER_ICBUF1T … #define MDIO_REG_BANK_TX1 … #define MDIO_TX1_TX_DRIVER … #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK … #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT … #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK … #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT … #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK … #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT … #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK … #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT … #define MDIO_TX0_TX_DRIVER_ICBUF1T … #define MDIO_REG_BANK_TX2 … #define MDIO_TX2_TX_DRIVER … #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK … #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT … #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK … #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT … #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK … #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT … #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK … #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT … #define MDIO_TX0_TX_DRIVER_ICBUF1T … #define MDIO_REG_BANK_TX3 … #define MDIO_TX3_TX_DRIVER … #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK … #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT … #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK … #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT … #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK … #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT … #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK … #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT … #define MDIO_TX0_TX_DRIVER_ICBUF1T … #define MDIO_REG_BANK_XGXS_BLOCK0 … #define MDIO_BLOCK0_XGXS_CONTROL … #define MDIO_REG_BANK_XGXS_BLOCK1 … #define MDIO_BLOCK1_LANE_CTRL0 … #define MDIO_BLOCK1_LANE_CTRL1 … #define MDIO_BLOCK1_LANE_CTRL2 … #define MDIO_BLOCK1_LANE_PRBS … #define MDIO_REG_BANK_XGXS_BLOCK2 … #define MDIO_XGXS_BLOCK2_RX_LN_SWAP … #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE … #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE … #define MDIO_XGXS_BLOCK2_TX_LN_SWAP … #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE … #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G … #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS … #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS … #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE … #define MDIO_REG_BANK_GP_STATUS … #define MDIO_GP_STATUS_TOP_AN_STATUS1 … #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE … #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE … #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS … #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS … #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE … #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE … #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE … #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI … #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 … #define MDIO_REG_BANK_10G_PARALLEL_DETECT … #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS … #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK … #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL … #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN … #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK … #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT … #define MDIO_REG_BANK_SERDES_DIGITAL … #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 … #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE … #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF … #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN … #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT … #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET … #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE … #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 … #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN … #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR … #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 … #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII … #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK … #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX … #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK … #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT … #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G … #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G … #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M … #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M … #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 … #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED … #define MDIO_SERDES_DIGITAL_MISC1 … #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK … #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M … #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M … #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M … #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M … #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M … #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL … #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK … #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G … #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G … #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G … #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG … #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 … #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G … #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G … #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G … #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G … #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G … #define MDIO_REG_BANK_OVER_1G … #define MDIO_OVER_1G_DIGCTL_3_4 … #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK … #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT … #define MDIO_OVER_1G_UP1 … #define MDIO_OVER_1G_UP1_2_5G … #define MDIO_OVER_1G_UP1_5G … #define MDIO_OVER_1G_UP1_6G … #define MDIO_OVER_1G_UP1_10G … #define MDIO_OVER_1G_UP1_10GH … #define MDIO_OVER_1G_UP1_12G … #define MDIO_OVER_1G_UP1_12_5G … #define MDIO_OVER_1G_UP1_13G … #define MDIO_OVER_1G_UP1_15G … #define MDIO_OVER_1G_UP1_16G … #define MDIO_OVER_1G_UP2 … #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK … #define MDIO_OVER_1G_UP2_IDRIVER_MASK … #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK … #define MDIO_OVER_1G_UP3 … #define MDIO_OVER_1G_UP3_HIGIG2 … #define MDIO_OVER_1G_LP_UP1 … #define MDIO_OVER_1G_LP_UP2 … #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK … #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK … #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT … #define MDIO_OVER_1G_LP_UP3 … #define MDIO_REG_BANK_REMOTE_PHY … #define MDIO_REMOTE_PHY_MISC_RX_STATUS … #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG … #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG … #define MDIO_REG_BANK_BAM_NEXT_PAGE … #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL … #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE … #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN … #define MDIO_REG_BANK_CL73_USERB0 … #define MDIO_CL73_USERB0_CL73_UCTRL … #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL … #define MDIO_CL73_USERB0_CL73_USTAT1 … #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK … #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 … #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 … #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN … #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN … #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN … #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 … #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR … #define MDIO_REG_BANK_AER_BLOCK … #define MDIO_AER_BLOCK_AER_REG … #define MDIO_REG_BANK_COMBO_IEEE0 … #define MDIO_COMBO_IEEE0_MII_CONTROL … #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK … #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 … #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 … #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 … #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX … #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN … #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN … #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK … #define MDIO_COMBO_IEEO_MII_CONTROL_RESET … #define MDIO_COMBO_IEEE0_MII_STATUS … #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS … #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE … #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV … #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX … #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX … #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK … #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE … #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC … #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC … #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH … #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE … #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 … #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE … #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK … #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK … #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE … #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH … #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP … #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP … /*WhenthelinkpartnerisinSGMIImode(bit0=1),then bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge. Theotherbitsarereservedandshouldbezero*/ #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE … #define MDIO_PMA_DEVAD … /*ieee*/ #define MDIO_PMA_REG_CTRL … #define MDIO_PMA_REG_STATUS … #define MDIO_PMA_REG_10G_CTRL2 … #define MDIO_PMA_REG_TX_DISABLE … #define MDIO_PMA_REG_RX_SD … /*bcm*/ #define MDIO_PMA_REG_BCM_CTRL … #define MDIO_PMA_REG_FEC_CTRL … #define MDIO_PMA_REG_PHY_IDENTIFIER … #define MDIO_PMA_REG_DIGITAL_CTRL … #define MDIO_PMA_REG_DIGITAL_STATUS … #define MDIO_PMA_REG_TX_POWER_DOWN … #define MDIO_PMA_REG_CMU_PLL_BYPASS … #define MDIO_PMA_REG_MISC_CTRL … #define MDIO_PMA_REG_GEN_CTRL … #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP … #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET … #define MDIO_PMA_REG_M8051_MSGIN_REG … #define MDIO_PMA_REG_M8051_MSGOUT_REG … #define MDIO_PMA_REG_ROM_VER1 … #define MDIO_PMA_REG_ROM_VER2 … #define MDIO_PMA_REG_EDC_FFE_MAIN … #define MDIO_PMA_REG_PLL_BANDWIDTH … #define MDIO_PMA_REG_PLL_CTRL … #define MDIO_PMA_REG_MISC_CTRL0 … #define MDIO_PMA_REG_LRM_MODE … #define MDIO_PMA_REG_CDR_BANDWIDTH … #define MDIO_PMA_REG_MISC_CTRL1 … #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL … #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK … #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE … #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE … #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS … #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED … #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT … #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR … #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF … #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK … #define MDIO_PMA_REG_8726_TX_CTRL1 … #define MDIO_PMA_REG_8726_TX_CTRL2 … #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR … #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF … #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK … #define MDIO_PMA_REG_8727_TX_CTRL1 … #define MDIO_PMA_REG_8727_TX_CTRL2 … #define MDIO_PMA_REG_8727_PCS_OPT_CTRL … #define MDIO_PMA_REG_8727_GPIO_CTRL … #define MDIO_PMA_REG_8727_PCS_GP … #define MDIO_PMA_REG_8727_OPT_CFG_REG … #define MDIO_AN_REG_8727_MISC_CTRL … #define MDIO_PMA_REG_8073_CHIP_REV … #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS … #define MDIO_PMA_REG_8073_XAUI_WA … #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL … #define MDIO_PMA_REG_7101_RESET … #define MDIO_PMA_REG_7107_LED_CNTL … #define MDIO_PMA_REG_7107_LINK_LED_CNTL … #define MDIO_PMA_REG_7101_VER1 … #define MDIO_PMA_REG_7101_VER2 … #define MDIO_PMA_REG_8481_PMD_SIGNAL … #define MDIO_PMA_REG_8481_LED1_MASK … #define MDIO_PMA_REG_8481_LED2_MASK … #define MDIO_PMA_REG_8481_LED3_MASK … #define MDIO_PMA_REG_8481_LED3_BLINK … #define MDIO_PMA_REG_8481_LED5_MASK … #define MDIO_PMA_REG_8481_SIGNAL_MASK … #define MDIO_PMA_REG_8481_LINK_SIGNAL … #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK … #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT … #define MDIO_WIS_DEVAD … /*bcm*/ #define MDIO_WIS_REG_LASI_CNTL … #define MDIO_WIS_REG_LASI_STATUS … #define MDIO_PCS_DEVAD … #define MDIO_PCS_REG_STATUS … #define MDIO_PCS_REG_LASI_STATUS … #define MDIO_PCS_REG_7101_DSP_ACCESS … #define MDIO_PCS_REG_7101_SPI_MUX … #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR … #define MDIO_PCS_REG_7101_SPI_RESET_BIT … #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR … #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD … #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD … #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD … #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR … #define MDIO_XS_DEVAD … #define MDIO_XS_PLL_SEQUENCER … #define MDIO_XS_SFX7101_XGXS_TEST1 … #define MDIO_XS_8706_REG_BANK_RX0 … #define MDIO_XS_8706_REG_BANK_RX1 … #define MDIO_XS_8706_REG_BANK_RX2 … #define MDIO_XS_8706_REG_BANK_RX3 … #define MDIO_XS_8706_REG_BANK_RXA … #define MDIO_XS_REG_8073_RX_CTRL_PCIE … #define MDIO_AN_DEVAD … /*ieee*/ #define MDIO_AN_REG_CTRL … #define MDIO_AN_REG_STATUS … #define MDIO_AN_REG_STATUS_AN_COMPLETE … #define MDIO_AN_REG_ADV_PAUSE … #define MDIO_AN_REG_ADV_PAUSE_PAUSE … #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC … #define MDIO_AN_REG_ADV_PAUSE_BOTH … #define MDIO_AN_REG_ADV_PAUSE_MASK … #define MDIO_AN_REG_ADV … #define MDIO_AN_REG_ADV2 … #define MDIO_AN_REG_LP_AUTO_NEG … #define MDIO_AN_REG_LP_AUTO_NEG2 … #define MDIO_AN_REG_MASTER_STATUS … #define MDIO_AN_REG_EEE_ADV … #define MDIO_AN_REG_LP_EEE_ADV … /*bcm*/ #define MDIO_AN_REG_LINK_STATUS … #define MDIO_AN_REG_CL37_CL73 … #define MDIO_AN_REG_CL37_AN … #define MDIO_AN_REG_CL37_FC_LD … #define MDIO_AN_REG_CL37_FC_LP … #define MDIO_AN_REG_1000T_STATUS … #define MDIO_AN_REG_8073_2_5G … #define MDIO_AN_REG_8073_BAM … #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL … #define MDIO_AN_REG_8481_LEGACY_MII_CTRL … #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G … #define MDIO_AN_REG_8481_LEGACY_MII_STATUS … #define MDIO_AN_REG_848xx_ID_MSB … #define BCM84858_PHY_ID … #define MDIO_AN_REG_848xx_ID_LSB … #define MDIO_AN_REG_8481_LEGACY_AN_ADV … #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION … #define MDIO_AN_REG_8481_1000T_CTRL … #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL … #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF … #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW … #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS … #define MDIO_AN_REG_8481_AUX_CTRL … #define MDIO_AN_REG_8481_LEGACY_SHADOW … /* BCM84823 only */ #define MDIO_CTL_DEVAD … #define MDIO_CTL_REG_84823_MEDIA … #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK … /* These pins configure the BCM84823 interface to MAC after reset. */ #define MDIO_CTL_REG_84823_CTRL_MAC_XFI … #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M … /* These pins configure the BCM84823 interface to Line after reset. */ #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK … #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L … #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI … /* When this pin is active high during reset, 10GBASE-T core is power * down, When it is active low the 10GBASE-T is power up */ #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN … #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK … #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER … #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER … #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G … #define MDIO_CTL_REG_84823_USER_CTRL_REG … #define MDIO_CTL_REG_84823_USER_CTRL_CMS … #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH … #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ … #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 … #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 … #define MDIO_PMA_REG_84823_LED3_STRETCH_EN … /* BCM84858 only */ #define MDIO_PMA_REG_84858_ALLOW_GPHY_ACT … /* BCM84833 only */ #define MDIO_84833_TOP_CFG_FW_REV … #define MDIO_84833_TOP_CFG_FW_EEE … #define MDIO_84833_TOP_CFG_FW_NO_EEE … #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 … #define MDIO_84833_SUPER_ISOLATE … /* These are mailbox register set used by 84833/84858. */ #define MDIO_848xx_TOP_CFG_SCRATCH_REG0 … #define MDIO_848xx_TOP_CFG_SCRATCH_REG1 … #define MDIO_848xx_TOP_CFG_SCRATCH_REG2 … #define MDIO_848xx_TOP_CFG_SCRATCH_REG3 … #define MDIO_848xx_TOP_CFG_SCRATCH_REG4 … #define MDIO_848xx_TOP_CFG_SCRATCH_REG26 … #define MDIO_848xx_TOP_CFG_SCRATCH_REG27 … #define MDIO_848xx_TOP_CFG_SCRATCH_REG28 … #define MDIO_848xx_TOP_CFG_SCRATCH_REG29 … #define MDIO_848xx_TOP_CFG_SCRATCH_REG30 … #define MDIO_848xx_TOP_CFG_SCRATCH_REG31 … #define MDIO_848xx_CMD_HDLR_COMMAND … #define MDIO_848xx_CMD_HDLR_STATUS … #define MDIO_848xx_CMD_HDLR_DATA1 … #define MDIO_848xx_CMD_HDLR_DATA2 … #define MDIO_848xx_CMD_HDLR_DATA3 … #define MDIO_848xx_CMD_HDLR_DATA4 … #define MDIO_848xx_CMD_HDLR_DATA5 … /* Mailbox command set used by 84833/84858 */ #define PHY848xx_CMD_SET_PAIR_SWAP … #define PHY848xx_CMD_GET_EEE_MODE … #define PHY848xx_CMD_SET_EEE_MODE … /* Mailbox status set used by 84833 only */ #define PHY84833_STATUS_CMD_RECEIVED … #define PHY84833_STATUS_CMD_IN_PROGRESS … #define PHY84833_STATUS_CMD_COMPLETE_PASS … #define PHY84833_STATUS_CMD_COMPLETE_ERROR … #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS … #define PHY84833_STATUS_CMD_SYSTEM_BOOT … #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS … #define PHY84833_STATUS_CMD_CLEAR_COMPLETE … #define PHY84833_STATUS_CMD_OPEN_OVERRIDE … /* Mailbox Process */ #define PHY84833_MB_PROCESS1 … #define PHY84833_MB_PROCESS2 … #define PHY84833_MB_PROCESS3 … /* Mailbox status set used by 84858 only */ #define PHY84858_STATUS_CMD_RECEIVED … #define PHY84858_STATUS_CMD_IN_PROGRESS … #define PHY84858_STATUS_CMD_COMPLETE_PASS … #define PHY84858_STATUS_CMD_COMPLETE_ERROR … #define PHY84858_STATUS_CMD_SYSTEM_BUSY … /* Warpcore clause 45 addressing */ #define MDIO_WC_DEVAD … #define MDIO_WC_REG_IEEE0BLK_MIICNTL … #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP … #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 … #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 … #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 … #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY … #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ … #define MDIO_WC_REG_PCS_STATUS2 … #define MDIO_WC_REG_PMD_KR_CONTROL … #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL … #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 … #define MDIO_WC_REG_XGXSBLK1_DESKEW … #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 … #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 … #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 … #define MDIO_WC_REG_TX0_ANA_CTRL0 … #define MDIO_WC_REG_TX1_ANA_CTRL0 … #define MDIO_WC_REG_TX2_ANA_CTRL0 … #define MDIO_WC_REG_TX3_ANA_CTRL0 … #define MDIO_WC_REG_TX0_TX_DRIVER … #define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET … #define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_MASK … #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET … #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK … #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET … #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK … #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET … #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK … #define MDIO_WC_REG_TX1_TX_DRIVER … #define MDIO_WC_REG_TX2_TX_DRIVER … #define MDIO_WC_REG_TX3_TX_DRIVER … #define MDIO_WC_REG_RX0_ANARXCONTROL1G … #define MDIO_WC_REG_RX2_ANARXCONTROL1G … #define MDIO_WC_REG_RX0_PCI_CTRL … #define MDIO_WC_REG_RX1_PCI_CTRL … #define MDIO_WC_REG_RX2_PCI_CTRL … #define MDIO_WC_REG_RX3_PCI_CTRL … #define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI … #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G … #define MDIO_WC_REG_XGXS_STATUS3 … #define MDIO_WC_REG_PAR_DET_10G_STATUS … #define MDIO_WC_REG_PAR_DET_10G_CTRL … #define MDIO_WC_REG_XGXS_X2_CONTROL2 … #define MDIO_WC_REG_XGXS_X2_CONTROL3 … #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 … #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 … #define MDIO_WC_REG_GP2_STATUS_GP_2_0 … #define MDIO_WC_REG_GP2_STATUS_GP_2_1 … #define MDIO_WC_REG_GP2_STATUS_GP_2_2 … #define MDIO_WC_REG_GP2_STATUS_GP_2_3 … #define MDIO_WC_REG_GP2_STATUS_GP_2_4 … #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL … #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL … #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP … #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP … #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP … #define MDIO_WC_REG_UC_INFO_B1_VERSION … #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE … #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET … #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT … #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR … #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC … #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI … #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G … #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET … #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET … #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET … #define MDIO_WC_REG_UC_INFO_B1_CRC … #define MDIO_WC_REG_DSC_SMC … #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 … #define MDIO_WC_REG_TX_FIR_TAP … #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET … #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK … #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET … #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK … #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET … #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK … #define MDIO_WC_REG_TX_FIR_TAP_ENABLE … #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP … #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL … #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL … #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL … #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL … #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL … #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 … #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 … #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 … #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 … #define MDIO_WC_REG_SERDESDIGITAL_MISC1 … #define MDIO_WC_REG_SERDESDIGITAL_MISC2 … #define MDIO_WC_REG_DIGITAL3_UP1 … #define MDIO_WC_REG_DIGITAL3_LP_UP1 … #define MDIO_WC_REG_DIGITAL4_MISC3 … #define MDIO_WC_REG_DIGITAL4_MISC5 … #define MDIO_WC_REG_DIGITAL5_MISC6 … #define MDIO_WC_REG_DIGITAL5_MISC7 … #define MDIO_WC_REG_DIGITAL5_LINK_STATUS … #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED … #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL … #define MDIO_WC_REG_CL49_USERB0_CTRL … #define MDIO_WC_REG_CL73_USERB0_CTRL … #define MDIO_WC_REG_CL73_USERB0_USTAT … #define MDIO_WC_REG_CL73_BAM_CTRL1 … #define MDIO_WC_REG_CL73_BAM_CTRL2 … #define MDIO_WC_REG_CL73_BAM_CTRL3 … #define MDIO_WC_REG_CL73_BAM_CODE_FIELD … #define MDIO_WC_REG_EEE_COMBO_CONTROL0 … #define MDIO_WC_REG_TX66_CONTROL … #define MDIO_WC_REG_RX66_CONTROL … #define MDIO_WC_REG_RX66_SCW0 … #define MDIO_WC_REG_RX66_SCW1 … #define MDIO_WC_REG_RX66_SCW2 … #define MDIO_WC_REG_RX66_SCW3 … #define MDIO_WC_REG_RX66_SCW0_MASK … #define MDIO_WC_REG_RX66_SCW1_MASK … #define MDIO_WC_REG_RX66_SCW2_MASK … #define MDIO_WC_REG_RX66_SCW3_MASK … #define MDIO_WC_REG_FX100_CTRL1 … #define MDIO_WC_REG_FX100_CTRL3 … #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 … #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 … #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 … #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 … #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 … #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 … #define MDIO_WC_REG_ETA_CL73_OUI1 … #define MDIO_WC_REG_ETA_CL73_OUI2 … #define MDIO_WC_REG_ETA_CL73_OUI3 … #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE … #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE … #define MDIO_WC_REG_MICROBLK_CMD … #define MDIO_WC_REG_MICROBLK_DL_STATUS … #define MDIO_WC_REG_MICROBLK_CMD3 … #define MDIO_WC_REG_AERBLK_AER … #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL … #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT … #define MDIO_WC0_XGXS_BLK2_LANE_RESET … #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT … #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT … #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 … #define DIGITAL5_ACTUAL_SPEED_TX_MASK … /* 54618se */ #define MDIO_REG_GPHY_PHYID_LSB … #define MDIO_REG_GPHY_ID_54618SE … #define MDIO_REG_GPHY_CL45_ADDR_REG … #define MDIO_REG_GPHY_CL45_DATA_REG … #define MDIO_REG_GPHY_EEE_RESOLVED … #define MDIO_REG_GPHY_EXP_ACCESS_GATE … #define MDIO_REG_GPHY_EXP_ACCESS … #define MDIO_REG_GPHY_EXP_ACCESS_TOP … #define MDIO_REG_GPHY_EXP_TOP_2K_BUF … #define MDIO_REG_GPHY_AUX_STATUS … #define MDIO_REG_INTR_STATUS … #define MDIO_REG_INTR_MASK … #define MDIO_REG_INTR_MASK_LINK_STATUS … #define MDIO_REG_GPHY_SHADOW … #define MDIO_REG_GPHY_SHADOW_LED_SEL1 … #define MDIO_REG_GPHY_SHADOW_LED_SEL2 … #define MDIO_REG_GPHY_SHADOW_WR_ENA … #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED … #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD … #define IGU_FUNC_BASE … #define IGU_ADDR_MSIX … #define IGU_ADDR_INT_ACK … #define IGU_ADDR_PROD_UPD … #define IGU_ADDR_ATTN_BITS_UPD … #define IGU_ADDR_ATTN_BITS_SET … #define IGU_ADDR_ATTN_BITS_CLR … #define IGU_ADDR_COALESCE_NOW … #define IGU_ADDR_SIMD_MASK … #define IGU_ADDR_SIMD_NOMASK … #define IGU_ADDR_MSI_CTL … #define IGU_ADDR_MSI_ADDR_LO … #define IGU_ADDR_MSI_ADDR_HI … #define IGU_ADDR_MSI_DATA … #define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup … #define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup … #define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup … #define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup … #define COMMAND_REG_INT_ACK … #define COMMAND_REG_PROD_UPD … #define COMMAND_REG_ATTN_BITS_UPD … #define COMMAND_REG_ATTN_BITS_SET … #define COMMAND_REG_ATTN_BITS_CLR … #define COMMAND_REG_COALESCE_NOW … #define COMMAND_REG_SIMD_MASK … #define COMMAND_REG_SIMD_NOMASK … #define IGU_MEM_BASE … #define IGU_MEM_MSIX_BASE … #define IGU_MEM_MSIX_UPPER … #define IGU_MEM_MSIX_RESERVED_UPPER … #define IGU_MEM_PBA_MSIX_BASE … #define IGU_MEM_PBA_MSIX_UPPER … #define IGU_CMD_BACKWARD_COMP_PROD_UPD … #define IGU_MEM_PBA_MSIX_RESERVED_UPPER … #define IGU_CMD_INT_ACK_BASE … #define IGU_CMD_INT_ACK_UPPER … #define IGU_CMD_INT_ACK_RESERVED_UPPER … #define IGU_CMD_E2_PROD_UPD_BASE … #define IGU_CMD_E2_PROD_UPD_UPPER … #define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER … #define IGU_CMD_ATTN_BIT_UPD_UPPER … #define IGU_CMD_ATTN_BIT_SET_UPPER … #define IGU_CMD_ATTN_BIT_CLR_UPPER … #define IGU_REG_SISR_MDPC_WMASK_UPPER … #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER … #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER … #define IGU_REG_SISR_MDPC_WOMASK_UPPER … #define IGU_REG_RESERVED_UPPER … /* Fields of IGU PF CONFIGURATION REGISTER */ #define IGU_PF_CONF_FUNC_EN … #define IGU_PF_CONF_MSI_MSIX_EN … #define IGU_PF_CONF_INT_LINE_EN … #define IGU_PF_CONF_ATTN_BIT_EN … #define IGU_PF_CONF_SINGLE_ISR_EN … #define IGU_PF_CONF_SIMD_MODE … /* Fields of IGU VF CONFIGURATION REGISTER */ #define IGU_VF_CONF_FUNC_EN … #define IGU_VF_CONF_MSI_MSIX_EN … #define IGU_VF_CONF_PARENT_MASK … #define IGU_VF_CONF_PARENT_SHIFT … #define IGU_VF_CONF_SINGLE_ISR_EN … #define IGU_BC_DSB_NUM_SEGS … #define IGU_BC_NDSB_NUM_SEGS … #define IGU_NORM_DSB_NUM_SEGS … #define IGU_NORM_NDSB_NUM_SEGS … #define IGU_BC_BASE_DSB_PROD … #define IGU_NORM_BASE_DSB_PROD … /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \ [5:2] = 0; [1:0] = PF number) */ #define IGU_FID_ENCODE_IS_PF … #define IGU_FID_ENCODE_IS_PF_SHIFT … #define IGU_FID_VF_NUM_MASK … #define IGU_FID_PF_NUM_MASK … #define IGU_REG_MAPPING_MEMORY_VALID … #define IGU_REG_MAPPING_MEMORY_VECTOR_MASK … #define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT … #define IGU_REG_MAPPING_MEMORY_FID_MASK … #define IGU_REG_MAPPING_MEMORY_FID_SHIFT … #define CDU_REGION_NUMBER_XCM_AG … #define CDU_REGION_NUMBER_UCM_AG … /* String-to-compress [31:8] = CID (all 24 bits) * String-to-compress [7:4] = Region * String-to-compress [3:0] = Type */ #define CDU_VALID_DATA(_cid, _region, _type) … #define CDU_CRC8(_cid, _region, _type) … #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) … #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) … #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) … /* IdleChk registers */ #define PXP_REG_HST_VF_DISABLED_ERROR_VALID … #define PXP_REG_HST_VF_DISABLED_ERROR_DATA … #define PXP_REG_HST_PER_VIOLATION_VALID … #define PXP_REG_HST_INCORRECT_ACCESS_VALID … #define PXP2_REG_RD_CPL_ERR_DETAILS … #define PXP2_REG_RD_CPL_ERR_DETAILS2 … #define PXP2_REG_RQ_GARB … #define PBF_REG_DISABLE_NEW_TASK_PROC_Q0 … #define PBF_REG_DISABLE_NEW_TASK_PROC_Q1 … #define PBF_REG_DISABLE_NEW_TASK_PROC_Q2 … #define PBF_REG_DISABLE_NEW_TASK_PROC_Q3 … #define PBF_REG_DISABLE_NEW_TASK_PROC_Q4 … #define PBF_REG_DISABLE_NEW_TASK_PROC_Q5 … #define PBF_REG_CREDIT_Q2 … #define PBF_REG_CREDIT_Q3 … #define PBF_REG_CREDIT_Q4 … #define PBF_REG_CREDIT_Q5 … #define PBF_REG_INIT_CRD_Q2 … #define PBF_REG_INIT_CRD_Q3 … #define PBF_REG_INIT_CRD_Q4 … #define PBF_REG_INIT_CRD_Q5 … #define PBF_REG_TASK_CNT_Q0 … #define PBF_REG_TASK_CNT_Q1 … #define PBF_REG_TASK_CNT_Q2 … #define PBF_REG_TASK_CNT_Q3 … #define PBF_REG_TASK_CNT_Q4 … #define PBF_REG_TASK_CNT_Q5 … #define PBF_REG_TASK_CNT_LB_Q … #define QM_REG_BYTECRD0 … #define QM_REG_BYTECRD1 … #define QM_REG_BYTECRD2 … #define QM_REG_BYTECRD3 … #define QM_REG_BYTECRD4 … #define QM_REG_BYTECRD5 … #define QM_REG_BYTECRD6 … #define QM_REG_BYTECRDCMDQ_0 … #define QM_REG_BYTECRDERRREG … #define MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID … #define QM_REG_VOQCREDIT_2 … #define QM_REG_VOQCREDIT_3 … #define QM_REG_VOQCREDIT_5 … #define QM_REG_VOQCREDIT_6 … #define QM_REG_VOQINITCREDIT_3 … #define QM_REG_VOQINITCREDIT_6 … #define QM_REG_FWVOQ0TOHWVOQ … #define QM_REG_FWVOQ1TOHWVOQ … #define QM_REG_FWVOQ2TOHWVOQ … #define QM_REG_FWVOQ3TOHWVOQ … #define QM_REG_FWVOQ4TOHWVOQ … #define QM_REG_FWVOQ5TOHWVOQ … #define QM_REG_FWVOQ6TOHWVOQ … #define QM_REG_FWVOQ7TOHWVOQ … #define NIG_REG_INGRESS_EOP_PORT0_EMPTY … #define NIG_REG_INGRESS_EOP_PORT1_EMPTY … #define NIG_REG_INGRESS_RMP0_DSCR_EMPTY … #define NIG_REG_INGRESS_RMP1_DSCR_EMPTY … #define NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY … #define NIG_REG_EGRESS_MNG0_FIFO_EMPTY … #define NIG_REG_EGRESS_MNG1_FIFO_EMPTY … #define NIG_REG_EGRESS_DEBUG_FIFO_EMPTY … #define NIG_REG_EGRESS_DELAY0_EMPTY … #define NIG_REG_EGRESS_DELAY1_EMPTY … #define NIG_REG_LLH0_FIFO_EMPTY … #define NIG_REG_LLH1_FIFO_EMPTY … #define NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY … #define NIG_REG_P0_TLLH_FIFO_EMPTY … #define NIG_REG_P0_HBUF_DSCR_EMPTY … #define NIG_REG_P1_HBUF_DSCR_EMPTY … #define NIG_REG_P0_RX_MACFIFO_EMPTY … #define NIG_REG_P0_TX_MACFIFO_EMPTY … #define NIG_REG_EGRESS_DELAY2_EMPTY … #define NIG_REG_EGRESS_DELAY3_EMPTY … #define NIG_REG_EGRESS_DELAY4_EMPTY … #define NIG_REG_EGRESS_DELAY5_EMPTY … /****************************************************************************** * Description: * Calculates crc 8 on a word value: polynomial 0-1-2-8 * Code was translated from Verilog. * Return: *****************************************************************************/ static inline u8 calc_crc8(u32 data, u8 crc) { … } #endif /* BNX2X_REG_H */
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