// SPDX-License-Identifier: GPL-2.0-only /* * Copyright 2010-2011 Calxeda, Inc. */ #include <linux/module.h> #include <linux/mod_devicetable.h> #include <linux/kernel.h> #include <linux/circ_buf.h> #include <linux/interrupt.h> #include <linux/etherdevice.h> #include <linux/platform_device.h> #include <linux/skbuff.h> #include <linux/ethtool.h> #include <linux/if.h> #include <linux/crc32.h> #include <linux/dma-mapping.h> #include <linux/slab.h> /* XGMAC Register definitions */ #define XGMAC_CONTROL … #define XGMAC_FRAME_FILTER … #define XGMAC_FLOW_CTRL … #define XGMAC_VLAN_TAG … #define XGMAC_VERSION … #define XGMAC_VLAN_INCL … #define XGMAC_LPI_CTRL … #define XGMAC_LPI_TIMER … #define XGMAC_TX_PACE … #define XGMAC_VLAN_HASH … #define XGMAC_DEBUG … #define XGMAC_INT_STAT … #define XGMAC_ADDR_HIGH(reg) … #define XGMAC_ADDR_LOW(reg) … #define XGMAC_HASH(n) … #define XGMAC_NUM_HASH … #define XGMAC_OMR … #define XGMAC_REMOTE_WAKE … #define XGMAC_PMT … #define XGMAC_MMC_CTRL … #define XGMAC_MMC_INTR_RX … #define XGMAC_MMC_INTR_TX … #define XGMAC_MMC_INTR_MASK_RX … #define XGMAC_MMC_INTR_MASK_TX … /* Hardware TX Statistics Counters */ #define XGMAC_MMC_TXOCTET_GB_LO … #define XGMAC_MMC_TXOCTET_GB_HI … #define XGMAC_MMC_TXFRAME_GB_LO … #define XGMAC_MMC_TXFRAME_GB_HI … #define XGMAC_MMC_TXBCFRAME_G … #define XGMAC_MMC_TXMCFRAME_G … #define XGMAC_MMC_TXUCFRAME_GB … #define XGMAC_MMC_TXMCFRAME_GB … #define XGMAC_MMC_TXBCFRAME_GB … #define XGMAC_MMC_TXUNDERFLOW … #define XGMAC_MMC_TXOCTET_G_LO … #define XGMAC_MMC_TXOCTET_G_HI … #define XGMAC_MMC_TXFRAME_G_LO … #define XGMAC_MMC_TXFRAME_G_HI … #define XGMAC_MMC_TXPAUSEFRAME … #define XGMAC_MMC_TXVLANFRAME … /* Hardware RX Statistics Counters */ #define XGMAC_MMC_RXFRAME_GB_LO … #define XGMAC_MMC_RXFRAME_GB_HI … #define XGMAC_MMC_RXOCTET_GB_LO … #define XGMAC_MMC_RXOCTET_GB_HI … #define XGMAC_MMC_RXOCTET_G_LO … #define XGMAC_MMC_RXOCTET_G_HI … #define XGMAC_MMC_RXBCFRAME_G … #define XGMAC_MMC_RXMCFRAME_G … #define XGMAC_MMC_RXCRCERR … #define XGMAC_MMC_RXRUNT … #define XGMAC_MMC_RXJABBER … #define XGMAC_MMC_RXUCFRAME_G … #define XGMAC_MMC_RXLENGTHERR … #define XGMAC_MMC_RXPAUSEFRAME … #define XGMAC_MMC_RXOVERFLOW … #define XGMAC_MMC_RXVLANFRAME … #define XGMAC_MMC_RXWATCHDOG … /* DMA Control and Status Registers */ #define XGMAC_DMA_BUS_MODE … #define XGMAC_DMA_TX_POLL … #define XGMAC_DMA_RX_POLL … #define XGMAC_DMA_RX_BASE_ADDR … #define XGMAC_DMA_TX_BASE_ADDR … #define XGMAC_DMA_STATUS … #define XGMAC_DMA_CONTROL … #define XGMAC_DMA_INTR_ENA … #define XGMAC_DMA_MISS_FRAME_CTR … #define XGMAC_DMA_RI_WDOG_TIMER … #define XGMAC_DMA_AXI_BUS … #define XGMAC_DMA_AXI_STATUS … #define XGMAC_DMA_HW_FEATURE … #define XGMAC_ADDR_AE … /* PMT Control and Status */ #define XGMAC_PMT_POINTER_RESET … #define XGMAC_PMT_GLBL_UNICAST … #define XGMAC_PMT_WAKEUP_RX_FRM … #define XGMAC_PMT_MAGIC_PKT … #define XGMAC_PMT_WAKEUP_FRM_EN … #define XGMAC_PMT_MAGIC_PKT_EN … #define XGMAC_PMT_POWERDOWN … #define XGMAC_CONTROL_SPD … #define XGMAC_CONTROL_SPD_MASK … #define XGMAC_CONTROL_SPD_1G … #define XGMAC_CONTROL_SPD_2_5G … #define XGMAC_CONTROL_SPD_10G … #define XGMAC_CONTROL_SARC … #define XGMAC_CONTROL_SARK_MASK … #define XGMAC_CONTROL_CAR … #define XGMAC_CONTROL_CAR_MASK … #define XGMAC_CONTROL_DP … #define XGMAC_CONTROL_WD … #define XGMAC_CONTROL_JD … #define XGMAC_CONTROL_JE … #define XGMAC_CONTROL_LM … #define XGMAC_CONTROL_IPC … #define XGMAC_CONTROL_ACS … #define XGMAC_CONTROL_DDIC … #define XGMAC_CONTROL_TE … #define XGMAC_CONTROL_RE … /* XGMAC Frame Filter defines */ #define XGMAC_FRAME_FILTER_PR … #define XGMAC_FRAME_FILTER_HUC … #define XGMAC_FRAME_FILTER_HMC … #define XGMAC_FRAME_FILTER_DAIF … #define XGMAC_FRAME_FILTER_PM … #define XGMAC_FRAME_FILTER_DBF … #define XGMAC_FRAME_FILTER_SAIF … #define XGMAC_FRAME_FILTER_SAF … #define XGMAC_FRAME_FILTER_HPF … #define XGMAC_FRAME_FILTER_VHF … #define XGMAC_FRAME_FILTER_VPF … #define XGMAC_FRAME_FILTER_RA … /* XGMAC FLOW CTRL defines */ #define XGMAC_FLOW_CTRL_PT_MASK … #define XGMAC_FLOW_CTRL_PT_SHIFT … #define XGMAC_FLOW_CTRL_DZQP … #define XGMAC_FLOW_CTRL_PLT … #define XGMAC_FLOW_CTRL_PLT_MASK … #define XGMAC_FLOW_CTRL_UP … #define XGMAC_FLOW_CTRL_RFE … #define XGMAC_FLOW_CTRL_TFE … #define XGMAC_FLOW_CTRL_FCB_BPA … /* XGMAC_INT_STAT reg */ #define XGMAC_INT_STAT_PMTIM … #define XGMAC_INT_STAT_PMT … #define XGMAC_INT_STAT_LPI … /* DMA Bus Mode register defines */ #define DMA_BUS_MODE_SFT_RESET … #define DMA_BUS_MODE_DSL_MASK … #define DMA_BUS_MODE_DSL_SHIFT … #define DMA_BUS_MODE_ATDS … /* Programmable burst length */ #define DMA_BUS_MODE_PBL_MASK … #define DMA_BUS_MODE_PBL_SHIFT … #define DMA_BUS_MODE_FB … #define DMA_BUS_MODE_RPBL_MASK … #define DMA_BUS_MODE_RPBL_SHIFT … #define DMA_BUS_MODE_USP … #define DMA_BUS_MODE_8PBL … #define DMA_BUS_MODE_AAL … /* DMA Bus Mode register defines */ #define DMA_BUS_PR_RATIO_MASK … #define DMA_BUS_PR_RATIO_SHIFT … #define DMA_BUS_FB … /* DMA Control register defines */ #define DMA_CONTROL_ST … #define DMA_CONTROL_SR … #define DMA_CONTROL_DFF … #define DMA_CONTROL_OSF … /* DMA Normal interrupt */ #define DMA_INTR_ENA_NIE … #define DMA_INTR_ENA_AIE … #define DMA_INTR_ENA_ERE … #define DMA_INTR_ENA_FBE … #define DMA_INTR_ENA_ETE … #define DMA_INTR_ENA_RWE … #define DMA_INTR_ENA_RSE … #define DMA_INTR_ENA_RUE … #define DMA_INTR_ENA_RIE … #define DMA_INTR_ENA_UNE … #define DMA_INTR_ENA_OVE … #define DMA_INTR_ENA_TJE … #define DMA_INTR_ENA_TUE … #define DMA_INTR_ENA_TSE … #define DMA_INTR_ENA_TIE … #define DMA_INTR_NORMAL … #define DMA_INTR_ABNORMAL … /* DMA default interrupt mask */ #define DMA_INTR_DEFAULT_MASK … /* DMA Status register defines */ #define DMA_STATUS_GMI … #define DMA_STATUS_GLI … #define DMA_STATUS_EB_MASK … #define DMA_STATUS_EB_TX_ABORT … #define DMA_STATUS_EB_RX_ABORT … #define DMA_STATUS_TS_MASK … #define DMA_STATUS_TS_SHIFT … #define DMA_STATUS_RS_MASK … #define DMA_STATUS_RS_SHIFT … #define DMA_STATUS_NIS … #define DMA_STATUS_AIS … #define DMA_STATUS_ERI … #define DMA_STATUS_FBI … #define DMA_STATUS_ETI … #define DMA_STATUS_RWT … #define DMA_STATUS_RPS … #define DMA_STATUS_RU … #define DMA_STATUS_RI … #define DMA_STATUS_UNF … #define DMA_STATUS_OVF … #define DMA_STATUS_TJT … #define DMA_STATUS_TU … #define DMA_STATUS_TPS … #define DMA_STATUS_TI … /* Common MAC defines */ #define MAC_ENABLE_TX … #define MAC_ENABLE_RX … /* XGMAC Operation Mode Register */ #define XGMAC_OMR_TSF … #define XGMAC_OMR_FTF … #define XGMAC_OMR_TTC … #define XGMAC_OMR_TTC_MASK … #define XGMAC_OMR_RFD … #define XGMAC_OMR_RFD_MASK … #define XGMAC_OMR_RFA … #define XGMAC_OMR_RFA_MASK … #define XGMAC_OMR_EFC … #define XGMAC_OMR_FEF … #define XGMAC_OMR_DT … #define XGMAC_OMR_RSF … #define XGMAC_OMR_RTC_256 … #define XGMAC_OMR_RTC_MASK … /* XGMAC HW Features Register */ #define DMA_HW_FEAT_TXCOESEL … #define XGMAC_MMC_CTRL_CNT_FRZ … /* XGMAC Descriptor Defines */ #define MAX_DESC_BUF_SZ … #define RXDESC_EXT_STATUS … #define RXDESC_CRC_ERR … #define RXDESC_RX_ERR … #define RXDESC_RX_WDOG … #define RXDESC_FRAME_TYPE … #define RXDESC_GIANT_FRAME … #define RXDESC_LAST_SEG … #define RXDESC_FIRST_SEG … #define RXDESC_VLAN_FRAME … #define RXDESC_OVERFLOW_ERR … #define RXDESC_LENGTH_ERR … #define RXDESC_SA_FILTER_FAIL … #define RXDESC_DESCRIPTOR_ERR … #define RXDESC_ERROR_SUMMARY … #define RXDESC_FRAME_LEN_OFFSET … #define RXDESC_FRAME_LEN_MASK … #define RXDESC_DA_FILTER_FAIL … #define RXDESC1_END_RING … #define RXDESC_IP_PAYLOAD_MASK … #define RXDESC_IP_PAYLOAD_UDP … #define RXDESC_IP_PAYLOAD_TCP … #define RXDESC_IP_PAYLOAD_ICMP … #define RXDESC_IP_HEADER_ERR … #define RXDESC_IP_PAYLOAD_ERR … #define RXDESC_IPV4_PACKET … #define RXDESC_IPV6_PACKET … #define TXDESC_UNDERFLOW_ERR … #define TXDESC_JABBER_TIMEOUT … #define TXDESC_LOCAL_FAULT … #define TXDESC_REMOTE_FAULT … #define TXDESC_VLAN_FRAME … #define TXDESC_FRAME_FLUSHED … #define TXDESC_IP_HEADER_ERR … #define TXDESC_PAYLOAD_CSUM_ERR … #define TXDESC_ERROR_SUMMARY … #define TXDESC_SA_CTRL_INSERT … #define TXDESC_SA_CTRL_REPLACE … #define TXDESC_2ND_ADDR_CHAINED … #define TXDESC_END_RING … #define TXDESC_CSUM_IP … #define TXDESC_CSUM_IP_PAYLD … #define TXDESC_CSUM_ALL … #define TXDESC_CRC_EN_REPLACE … #define TXDESC_CRC_EN_APPEND … #define TXDESC_DISABLE_PAD … #define TXDESC_FIRST_SEG … #define TXDESC_LAST_SEG … #define TXDESC_INTERRUPT … #define DESC_OWN … #define DESC_BUFFER1_SZ_MASK … #define DESC_BUFFER2_SZ_MASK … #define DESC_BUFFER2_SZ_OFFSET … struct xgmac_dma_desc { … }; struct xgmac_extra_stats { … }; struct xgmac_priv { … }; /* XGMAC Configuration Settings */ #define XGMAC_MAX_MTU … #define PAUSE_TIME … #define DMA_RX_RING_SZ … #define DMA_TX_RING_SZ … /* minimum number of free TX descriptors required to wake up TX process */ #define TX_THRESH … /* DMA descriptor ring helpers */ #define dma_ring_incr(n, s) … #define dma_ring_space(h, t, s) … #define dma_ring_cnt(h, t, s) … #define tx_dma_ring_space(p) … /* XGMAC Descriptor Access Helpers */ static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz) { … } static inline int desc_get_buf_len(struct xgmac_dma_desc *p) { … } static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size, int buf_sz) { … } static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size) { … } static inline int desc_get_owner(struct xgmac_dma_desc *p) { … } static inline void desc_set_rx_owner(struct xgmac_dma_desc *p) { … } static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags) { … } static inline void desc_clear_tx_owner(struct xgmac_dma_desc *p) { … } static inline int desc_get_tx_ls(struct xgmac_dma_desc *p) { … } static inline int desc_get_tx_fs(struct xgmac_dma_desc *p) { … } static inline u32 desc_get_buf_addr(struct xgmac_dma_desc *p) { … } static inline void desc_set_buf_addr(struct xgmac_dma_desc *p, u32 paddr, int len) { … } static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p, u32 paddr, int len) { … } static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p) { … } static void xgmac_dma_flush_tx_fifo(void __iomem *ioaddr) { … } static int desc_get_tx_status(struct xgmac_priv *priv, struct xgmac_dma_desc *p) { … } static int desc_get_rx_status(struct xgmac_priv *priv, struct xgmac_dma_desc *p) { … } static inline void xgmac_mac_enable(void __iomem *ioaddr) { … } static inline void xgmac_mac_disable(void __iomem *ioaddr) { … } static void xgmac_set_mac_addr(void __iomem *ioaddr, const unsigned char *addr, int num) { … } static void xgmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, int num) { … } static int xgmac_set_flow_ctrl(struct xgmac_priv *priv, int rx, int tx) { … } static void xgmac_rx_refill(struct xgmac_priv *priv) { … } /** * xgmac_dma_desc_rings_init - init the RX/TX descriptor rings * @dev: net device structure * Description: this function initializes the DMA RX/TX descriptors * and allocates the socket buffers. */ static int xgmac_dma_desc_rings_init(struct net_device *dev) { … } static void xgmac_free_rx_skbufs(struct xgmac_priv *priv) { … } static void xgmac_free_tx_skbufs(struct xgmac_priv *priv) { … } static void xgmac_free_dma_desc_rings(struct xgmac_priv *priv) { … } /** * xgmac_tx_complete: * @priv: private driver structure * Description: it reclaims resources after transmission completes. */ static void xgmac_tx_complete(struct xgmac_priv *priv) { … } static void xgmac_tx_timeout_work(struct work_struct *work) { … } static int xgmac_hw_init(struct net_device *dev) { … } /** * xgmac_open - open entry point of the driver * @dev : pointer to the device structure. * Description: * This function is the open entry point of the driver. * Return value: * 0 on success and an appropriate (-)ve integer as defined in errno.h * file on failure. */ static int xgmac_open(struct net_device *dev) { … } /** * xgmac_stop - close entry point of the driver * @dev : device pointer. * Description: * This is the stop entry point of the driver. */ static int xgmac_stop(struct net_device *dev) { … } /** * xgmac_xmit: * @skb : the socket buffer * @dev : device pointer * Description : Tx entry point of the driver. */ static netdev_tx_t xgmac_xmit(struct sk_buff *skb, struct net_device *dev) { … } static int xgmac_rx(struct xgmac_priv *priv, int limit) { … } /** * xgmac_poll - xgmac poll method (NAPI) * @napi : pointer to the napi structure. * @budget : maximum number of packets that the current CPU can receive from * all interfaces. * Description : * This function implements the reception process. * Also it runs the TX completion thread */ static int xgmac_poll(struct napi_struct *napi, int budget) { … } /** * xgmac_tx_timeout * @dev : Pointer to net device structure * @txqueue: index of the hung transmit queue * * Description: this function is called when a packet transmission fails to * complete within a reasonable tmrate. The driver will mark the error in the * netdev structure and arrange for the device to be reset to a sane state * in order to transmit a new packet. */ static void xgmac_tx_timeout(struct net_device *dev, unsigned int txqueue) { … } /** * xgmac_set_rx_mode - entry point for multicast addressing * @dev : pointer to the device structure * Description: * This function is a driver entry point which gets called by the kernel * whenever multicast addresses must be enabled/disabled. * Return value: * void. */ static void xgmac_set_rx_mode(struct net_device *dev) { … } /** * xgmac_change_mtu - entry point to change MTU size for the device. * @dev : device pointer. * @new_mtu : the new MTU size for the device. * Description: the Maximum Transfer Unit (MTU) is used by the network layer * to drive packet transmission. Ethernet has an MTU of 1500 octets * (ETH_DATA_LEN). This value can be changed with ifconfig. * Return value: * 0 on success and an appropriate (-)ve integer as defined in errno.h * file on failure. */ static int xgmac_change_mtu(struct net_device *dev, int new_mtu) { … } static irqreturn_t xgmac_pmt_interrupt(int irq, void *dev_id) { … } static irqreturn_t xgmac_interrupt(int irq, void *dev_id) { … } #ifdef CONFIG_NET_POLL_CONTROLLER /* Polling receive - used by NETCONSOLE and other diagnostic tools * to allow network I/O with interrupts disabled. */ static void xgmac_poll_controller(struct net_device *dev) { … } #endif static void xgmac_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *storage) { … } static int xgmac_set_mac_address(struct net_device *dev, void *p) { … } static int xgmac_set_features(struct net_device *dev, netdev_features_t features) { … } static const struct net_device_ops xgmac_netdev_ops = …; static int xgmac_ethtool_get_link_ksettings(struct net_device *dev, struct ethtool_link_ksettings *cmd) { … } static void xgmac_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) { … } static int xgmac_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) { … } struct xgmac_stats { … }; #define XGMAC_STAT(m) … #define XGMAC_HW_STAT(m, reg_offset) … static const struct xgmac_stats xgmac_gstrings_stats[] = …; #define XGMAC_STATS_LEN … static void xgmac_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *dummy, u64 *data) { … } static int xgmac_get_sset_count(struct net_device *netdev, int sset) { … } static void xgmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) { … } static void xgmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) { … } static int xgmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) { … } static const struct ethtool_ops xgmac_ethtool_ops = …; /** * xgmac_probe * @pdev: platform device pointer * Description: the driver is initialized through platform_device. */ static int xgmac_probe(struct platform_device *pdev) { … } /** * xgmac_remove * @pdev: platform device pointer * Description: this function resets the TX/RX processes, disables the MAC RX/TX * changes the link status, releases the DMA descriptor rings, * unregisters the MDIO bus and unmaps the allocated memory. */ static void xgmac_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static void xgmac_pmt(void __iomem *ioaddr, unsigned long mode) { … } static int xgmac_suspend(struct device *dev) { … } static int xgmac_resume(struct device *dev) { … } #endif /* CONFIG_PM_SLEEP */ static SIMPLE_DEV_PM_OPS(xgmac_pm_ops, xgmac_suspend, xgmac_resume); static const struct of_device_id xgmac_of_match[] = …; MODULE_DEVICE_TABLE(of, xgmac_of_match); static struct platform_driver xgmac_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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