linux/drivers/net/ethernet/cavium/thunder/nic_reg.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2015 Cavium, Inc.
 */

#ifndef NIC_REG_H
#define NIC_REG_H

#define NIC_PF_REG_COUNT
#define NIC_VF_REG_COUNT

/* Physical function register offsets */
#define NIC_PF_CFG
#define NIC_PF_STATUS
#define NIC_PF_INTR_TIMER_CFG
#define NIC_PF_BIST_STATUS
#define NIC_PF_SOFT_RESET
#define NIC_PF_TCP_TIMER
#define NIC_PF_BP_CFG
#define NIC_PF_RRM_CFG
#define NIC_PF_CQM_CFG
#define NIC_PF_CNM_CF
#define NIC_PF_CNM_STATUS
#define NIC_PF_CQ_AVG_CFG
#define NIC_PF_RRM_AVG_CFG
#define NIC_PF_INTF_0_1_SEND_CFG
#define NIC_PF_INTF_0_1_BP_CFG
#define NIC_PF_INTF_0_1_BP_DIS_0_1
#define NIC_PF_INTF_0_1_BP_SW_0_1
#define NIC_PF_RBDR_BP_STATE_0_3
#define NIC_PF_MAILBOX_INT
#define NIC_PF_MAILBOX_INT_W1S
#define NIC_PF_MAILBOX_ENA_W1C
#define NIC_PF_MAILBOX_ENA_W1S
#define NIC_PF_RX_ETYPE_0_7
#define NIC_PF_RX_GENEVE_DEF
#define UDP_GENEVE_PORT_NUM
#define NIC_PF_RX_GENEVE_PROT_DEF
#define IPV6_PROT
#define IPV4_PROT
#define ET_PROT
#define NIC_PF_RX_NVGRE_PROT_DEF
#define NIC_PF_RX_VXLAN_DEF_0_1
#define UDP_VXLAN_PORT_NUM
#define NIC_PF_RX_VXLAN_PROT_DEF
#define IPV6_PROT_DEF
#define IPV4_PROT_DEF
#define ET_PROT_DEF
#define NIC_PF_RX_CFG
#define NIC_PF_PKIND_0_15_CFG
#define NIC_PF_ECC0_FLIP0
#define NIC_PF_ECC1_FLIP0
#define NIC_PF_ECC2_FLIP0
#define NIC_PF_ECC3_FLIP0
#define NIC_PF_ECC0_FLIP1
#define NIC_PF_ECC1_FLIP1
#define NIC_PF_ECC2_FLIP1
#define NIC_PF_ECC3_FLIP1
#define NIC_PF_ECC0_CDIS
#define NIC_PF_ECC1_CDIS
#define NIC_PF_ECC2_CDIS
#define NIC_PF_ECC3_CDIS
#define NIC_PF_BIST0_STATUS
#define NIC_PF_BIST1_STATUS
#define NIC_PF_BIST2_STATUS
#define NIC_PF_BIST3_STATUS
#define NIC_PF_ECC0_SBE_INT
#define NIC_PF_ECC0_SBE_INT_W1S
#define NIC_PF_ECC0_SBE_ENA_W1C
#define NIC_PF_ECC0_SBE_ENA_W1S
#define NIC_PF_ECC0_DBE_INT
#define NIC_PF_ECC0_DBE_INT_W1S
#define NIC_PF_ECC0_DBE_ENA_W1C
#define NIC_PF_ECC0_DBE_ENA_W1S
#define NIC_PF_ECC1_SBE_INT
#define NIC_PF_ECC1_SBE_INT_W1S
#define NIC_PF_ECC1_SBE_ENA_W1C
#define NIC_PF_ECC1_SBE_ENA_W1S
#define NIC_PF_ECC1_DBE_INT
#define NIC_PF_ECC1_DBE_INT_W1S
#define NIC_PF_ECC1_DBE_ENA_W1C
#define NIC_PF_ECC1_DBE_ENA_W1S
#define NIC_PF_ECC2_SBE_INT
#define NIC_PF_ECC2_SBE_INT_W1S
#define NIC_PF_ECC2_SBE_ENA_W1C
#define NIC_PF_ECC2_SBE_ENA_W1S
#define NIC_PF_ECC2_DBE_INT
#define NIC_PF_ECC2_DBE_INT_W1S
#define NIC_PF_ECC2_DBE_ENA_W1C
#define NIC_PF_ECC2_DBE_ENA_W1S
#define NIC_PF_ECC3_SBE_INT
#define NIC_PF_ECC3_SBE_INT_W1S
#define NIC_PF_ECC3_SBE_ENA_W1C
#define NIC_PF_ECC3_SBE_ENA_W1S
#define NIC_PF_ECC3_DBE_INT
#define NIC_PF_ECC3_DBE_INT_W1S
#define NIC_PF_ECC3_DBE_ENA_W1C
#define NIC_PF_ECC3_DBE_ENA_W1S
#define NIC_PF_INTFX_SEND_CFG
#define NIC_PF_MCAM_0_191_ENA
#define NIC_PF_MCAM_0_191_M_0_5_DATA
#define NIC_PF_MCAM_CTRL
#define NIC_PF_CPI_0_2047_CFG
#define NIC_PF_MPI_0_2047_CFG
#define NIC_PF_RSSI_0_4097_RQ
#define NIC_PF_LMAC_0_7_CFG
#define NIC_PF_LMAC_0_7_CFG2
#define NIC_PF_LMAC_0_7_SW_XOFF
#define NIC_PF_LMAC_0_7_CREDIT
#define NIC_PF_CHAN_0_255_TX_CFG
#define NIC_PF_CHAN_0_255_RX_CFG
#define NIC_PF_CHAN_0_255_SW_XOFF
#define NIC_PF_CHAN_0_255_CREDIT
#define NIC_PF_CHAN_0_255_RX_BP_CFG
#define NIC_PF_SW_SYNC_RX
#define NIC_PF_SW_SYNC_RX_DONE
#define NIC_PF_TL2_0_63_CFG
#define NIC_PF_TL2_0_63_PRI
#define NIC_PF_TL2_LMAC
#define NIC_PF_TL2_0_63_SH_STATUS
#define NIC_PF_TL3A_0_63_CFG
#define NIC_PF_TL3_0_255_CFG
#define NIC_PF_TL3_0_255_CHAN
#define NIC_PF_TL3_0_255_PIR
#define NIC_PF_TL3_0_255_SW_XOFF
#define NIC_PF_TL3_0_255_CNM_RATE
#define NIC_PF_TL3_0_255_SH_STATUS
#define NIC_PF_TL4A_0_255_CFG
#define NIC_PF_TL4_0_1023_CFG
#define NIC_PF_TL4_0_1023_SW_XOFF
#define NIC_PF_TL4_0_1023_SH_STATUS
#define NIC_PF_TL4A_0_1023_CNM_RATE
#define NIC_PF_TL4A_0_1023_CNM_STATUS
#define NIC_PF_VF_0_127_MAILBOX_0_1
#define NIC_PF_VNIC_0_127_TX_STAT_0_4
#define NIC_PF_VNIC_0_127_RX_STAT_0_13
#define NIC_PF_QSET_0_127_LOCK_0_15
#define NIC_PF_QSET_0_127_CFG
#define NIC_PF_QSET_0_127_RQ_0_7_CFG
#define NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG
#define NIC_PF_QSET_0_127_RQ_0_7_BP_CFG
#define NIC_PF_QSET_0_127_RQ_0_7_STAT_0_1
#define NIC_PF_QSET_0_127_SQ_0_7_CFG
#define NIC_PF_QSET_0_127_SQ_0_7_CFG2
#define NIC_PF_QSET_0_127_SQ_0_7_STAT_0_1

#define NIC_PF_MSIX_VEC_0_18_ADDR
#define NIC_PF_MSIX_VEC_0_CTL
#define NIC_PF_MSIX_PBA_0

/* Virtual function register offsets */
#define NIC_VNIC_CFG
#define NIC_VF_PF_MAILBOX_0_1
#define NIC_VF_INT
#define NIC_VF_INT_W1S
#define NIC_VF_ENA_W1C
#define NIC_VF_ENA_W1S

#define NIC_VNIC_RSS_CFG
#define NIC_VNIC_RSS_KEY_0_4
#define NIC_VNIC_TX_STAT_0_4
#define NIC_VNIC_RX_STAT_0_13
#define NIC_QSET_RQ_GEN_CFG

#define NIC_QSET_CQ_0_7_CFG
#define NIC_QSET_CQ_0_7_CFG2
#define NIC_QSET_CQ_0_7_THRESH
#define NIC_QSET_CQ_0_7_BASE
#define NIC_QSET_CQ_0_7_HEAD
#define NIC_QSET_CQ_0_7_TAIL
#define NIC_QSET_CQ_0_7_DOOR
#define NIC_QSET_CQ_0_7_STATUS
#define NIC_QSET_CQ_0_7_STATUS2
#define NIC_QSET_CQ_0_7_DEBUG

#define NIC_QSET_RQ_0_7_CFG
#define NIC_QSET_RQ_0_7_STAT_0_1

#define NIC_QSET_SQ_0_7_CFG
#define NIC_QSET_SQ_0_7_THRESH
#define NIC_QSET_SQ_0_7_BASE
#define NIC_QSET_SQ_0_7_HEAD
#define NIC_QSET_SQ_0_7_TAIL
#define NIC_QSET_SQ_0_7_DOOR
#define NIC_QSET_SQ_0_7_STATUS
#define NIC_QSET_SQ_0_7_DEBUG
#define NIC_QSET_SQ_0_7_STAT_0_1

#define NIC_QSET_RBDR_0_1_CFG
#define NIC_QSET_RBDR_0_1_THRESH
#define NIC_QSET_RBDR_0_1_BASE
#define NIC_QSET_RBDR_0_1_HEAD
#define NIC_QSET_RBDR_0_1_TAIL
#define NIC_QSET_RBDR_0_1_DOOR
#define NIC_QSET_RBDR_0_1_STATUS0
#define NIC_QSET_RBDR_0_1_STATUS1
#define NIC_QSET_RBDR_0_1_PREFETCH_STATUS

#define NIC_VF_MSIX_VECTOR_0_19_ADDR
#define NIC_VF_MSIX_VECTOR_0_19_CTL
#define NIC_VF_MSIX_PBA

/* Offsets within registers */
#define NIC_MSIX_VEC_SHIFT
#define NIC_Q_NUM_SHIFT
#define NIC_QS_ID_SHIFT
#define NIC_VF_NUM_SHIFT

/* Port kind configuration register */
struct pkind_cfg {};

#endif /* NIC_REG_H */