/********************************************************************** * Author: Cavium, Inc. * * Contact: [email protected] * Please include "LiquidIO" in the subject. * * Copyright (c) 2003-2016 Cavium, Inc. * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as * published by the Free Software Foundation. * * This file is distributed in the hope that it will be useful, but * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or * NONINFRINGEMENT. See the GNU General Public License for more details. ***********************************************************************/ /*! \file liquidio_common.h * \brief Common: Structures and macros used in PCI-NIC package by core and * host driver. */ #ifndef __LIQUIDIO_COMMON_H__ #define __LIQUIDIO_COMMON_H__ #include "octeon_config.h" #define LIQUIDIO_BASE_MAJOR_VERSION … #define LIQUIDIO_BASE_MINOR_VERSION … #define LIQUIDIO_BASE_MICRO_VERSION … #define LIQUIDIO_BASE_VERSION … struct lio_version { … }; #define CONTROL_IQ … /** Tag types used by Octeon cores in its work. */ enum octeon_tag_type { … }; /* pre-defined host->NIC tag values */ #define LIO_CONTROL … #define LIO_DATA(i) … /* Opcodes used by host driver/apps to perform operations on the core. * These are used to identify the major subsystem that the operation * is for. */ #define OPCODE_CORE … #define OPCODE_NIC … /* Subcodes are used by host driver/apps to identify the sub-operation * for the core. They only need to by unique for a given subsystem. */ #define OPCODE_SUBCODE(op, sub) … /** OPCODE_CORE subcodes. For future use. */ /** OPCODE_NIC subcodes */ /* This subcode is sent by core PCI driver to indicate cores are ready. */ #define OPCODE_NIC_CORE_DRV_ACTIVE … #define OPCODE_NIC_NW_DATA … #define OPCODE_NIC_CMD … #define OPCODE_NIC_INFO … #define OPCODE_NIC_PORT_STATS … #define OPCODE_NIC_MDIO45 … #define OPCODE_NIC_TIMESTAMP … #define OPCODE_NIC_INTRMOD_CFG … #define OPCODE_NIC_IF_CFG … #define OPCODE_NIC_VF_DRV_NOTICE … #define OPCODE_NIC_INTRMOD_PARAMS … #define OPCODE_NIC_QCOUNT_UPDATE … #define OPCODE_NIC_SET_TRUSTED_VF … #define OPCODE_NIC_SYNC_OCTEON_TIME … #define VF_DRV_LOADED … #define VF_DRV_REMOVED … #define VF_DRV_MACADDR_CHANGED … #define OPCODE_NIC_VF_REP_PKT … #define OPCODE_NIC_VF_REP_CMD … #define OPCODE_NIC_UBOOT_CTL … #define CORE_DRV_TEST_SCATTER_OP … /* Application codes advertised by the core driver initialization packet. */ #define CVM_DRV_APP_START … #define CVM_DRV_NO_APP … #define CVM_DRV_APP_COUNT … #define CVM_DRV_BASE_APP … #define CVM_DRV_NIC_APP … #define CVM_DRV_INVALID_APP … #define CVM_DRV_APP_END … #define BYTES_PER_DHLEN_UNIT … #define MAX_REG_CNT … #define INTRNAMSIZ … #define IRQ_NAME_OFF(i) … #define MAX_IOQ_INTERRUPTS_PER_PF … #define MAX_IOQ_INTERRUPTS_PER_VF … #define SCR2_BIT_FW_LOADED … /* App specific capabilities from firmware to pf driver */ #define LIQUIDIO_TIME_SYNC_CAP … #define LIQUIDIO_SWITCHDEV_CAP … #define LIQUIDIO_SPOOFCHK_CAP … /* error status return from firmware */ #define OCTEON_REQUEST_NO_PERMISSION … static inline u32 incr_index(u32 index, u32 count, u32 max) { … } #define OCT_BOARD_NAME … #define OCT_SERIAL_LEN … /* Structure used by core driver to send indication that the Octeon * application is ready. */ struct octeon_core_setup { … }; /*--------------------------- SCATTER GATHER ENTRY -----------------------*/ /* The Scatter-Gather List Entry. The scatter or gather component used with * a Octeon input instruction has this format. */ struct octeon_sg_entry { … }; #define OCT_SG_ENTRY_SIZE … /* \brief Add size to gather list * @param sg_entry scatter/gather entry * @param size size to add * @param pos position to add it. */ static inline void add_sg_size(struct octeon_sg_entry *sg_entry, u16 size, u32 pos) { … } /*------------------------- End Scatter/Gather ---------------------------*/ #define OCTNET_FRM_LENGTH_SIZE … #define OCTNET_FRM_PTP_HEADER_SIZE … #define OCTNET_FRM_HEADER_SIZE … #define OCTNET_MIN_FRM_SIZE … #define OCTNET_MAX_FRM_SIZE … #define OCTNET_DEFAULT_MTU … #define OCTNET_DEFAULT_FRM_SIZE … /** NIC Commands are sent using this Octeon Input Queue */ #define OCTNET_CMD_Q … /* NIC Command types */ #define OCTNET_CMD_CHANGE_MTU … #define OCTNET_CMD_CHANGE_MACADDR … #define OCTNET_CMD_CHANGE_DEVFLAGS … #define OCTNET_CMD_RX_CTL … #define OCTNET_CMD_SET_MULTI_LIST … #define OCTNET_CMD_CLEAR_STATS … /* command for setting the speed, duplex & autoneg */ #define OCTNET_CMD_SET_SETTINGS … #define OCTNET_CMD_SET_FLOW_CTL … #define OCTNET_CMD_MDIO_READ_WRITE … #define OCTNET_CMD_GPIO_ACCESS … #define OCTNET_CMD_LRO_ENABLE … #define OCTNET_CMD_LRO_DISABLE … #define OCTNET_CMD_SET_RSS … #define OCTNET_CMD_WRITE_SA … #define OCTNET_CMD_DELETE_SA … #define OCTNET_CMD_UPDATE_SA … #define OCTNET_CMD_TNL_RX_CSUM_CTL … #define OCTNET_CMD_TNL_TX_CSUM_CTL … #define OCTNET_CMD_IPSECV2_AH_ESP_CTL … #define OCTNET_CMD_VERBOSE_ENABLE … #define OCTNET_CMD_VERBOSE_DISABLE … #define OCTNET_CMD_VLAN_FILTER_CTL … #define OCTNET_CMD_ADD_VLAN_FILTER … #define OCTNET_CMD_DEL_VLAN_FILTER … #define OCTNET_CMD_VXLAN_PORT_CONFIG … #define OCTNET_CMD_ID_ACTIVE … #define OCTNET_CMD_SET_UC_LIST … #define OCTNET_CMD_SET_VF_LINKSTATE … #define OCTNET_CMD_QUEUE_COUNT_CTL … #define OCTNET_CMD_GROUP1 … #define OCTNET_CMD_SET_VF_SPOOFCHK … #define OCTNET_GROUP1_LAST_CMD … #define OCTNET_CMD_VXLAN_PORT_ADD … #define OCTNET_CMD_VXLAN_PORT_DEL … #define OCTNET_CMD_RXCSUM_ENABLE … #define OCTNET_CMD_RXCSUM_DISABLE … #define OCTNET_CMD_TXCSUM_ENABLE … #define OCTNET_CMD_TXCSUM_DISABLE … #define OCTNET_CMD_VLAN_FILTER_ENABLE … #define OCTNET_CMD_VLAN_FILTER_DISABLE … #define OCTNET_CMD_FAIL … #define SEAPI_CMD_FEC_SET … #define SEAPI_CMD_FEC_SET_DISABLE … #define SEAPI_CMD_FEC_SET_RS … #define SEAPI_CMD_FEC_GET … #define SEAPI_CMD_SPEED_SET … #define SEAPI_CMD_SPEED_GET … #define OPCODE_NIC_VF_PORT_STATS … #define LIO_CMD_WAIT_TM … /* RX(packets coming from wire) Checksum verification flags */ /* TCP/UDP csum */ #define CNNIC_L4SUM_VERIFIED … #define CNNIC_IPSUM_VERIFIED … #define CNNIC_TUN_CSUM_VERIFIED … #define CNNIC_CSUM_VERIFIED … /*LROIPV4 and LROIPV6 Flags*/ #define OCTNIC_LROIPV4 … #define OCTNIC_LROIPV6 … /* Interface flags communicated between host driver and core app. */ enum octnet_ifflags { … }; /* wqe * --------------- 0 * | wqe word0-3 | * --------------- 32 * | PCI IH | * --------------- 40 * | RPTR | * --------------- 48 * | PCI IRH | * --------------- 56 * | OCT_NET_CMD | * --------------- 64 * | Addtl 8-BData | * | | * --------------- */ octnet_cmd; #define OCTNET_CMD_SIZE … /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */ #define LIO_SOFTCMDRESP_IH2 … #define LIO_SOFTCMDRESP_IH3 … #define LIO_PCICMD_O2 … #define LIO_PCICMD_O3 … /* Instruction Header(DPI) - for OCTEON-III models */ struct octeon_instr_ih3 { … }; /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */ /** BIG ENDIAN format. */ struct octeon_instr_pki_ih3 { … }; /** Instruction Header */ struct octeon_instr_ih2 { … }; /** Input Request Header */ struct octeon_instr_irh { … }; /** Return Data Parameters */ struct octeon_instr_rdp { … }; /** Receive Header */ octeon_rh; #define OCT_RH_SIZE … octnic_packet_params; /** Status of a RGMII Link on Octeon as seen by core driver. */ oct_link_status; enum lio_phy_type { … }; /** The txpciq info passed to host from the firmware */ oct_txpciq; /** The rxpciq info passed to host from the firmware */ oct_rxpciq; /** Information for a OCTEON ethernet interface shared between core & host. */ struct oct_link_info { … }; #define OCT_LINK_INFO_SIZE … struct liquidio_if_cfg_info { … }; /** Stats for each NIC port in RX direction. */ struct nic_rx_stats { … }; /** Stats for each NIC port in RX direction. */ struct nic_tx_stats { … }; struct oct_link_stats { … }; static inline int opcode_slow_path(union octeon_rh *rh) { … } #define LIO68XX_LED_CTRL_ADDR … #define LIO68XX_LED_CTRL_CFGON … #define LIO68XX_LED_CTRL_CFGOFF … #define LIO68XX_LED_BEACON_ADDR … #define LIO68XX_LED_BEACON_CFGON … #define LIO68XX_LED_BEACON_CFGOFF … #define VITESSE_PHY_GPIO_DRIVEON … #define VITESSE_PHY_GPIO_CFG … #define VITESSE_PHY_GPIO_DRIVEOFF … #define VITESSE_PHY_GPIO_HIGH … #define VITESSE_PHY_GPIO_LOW … #define LED_IDENTIFICATION_ON … #define LED_IDENTIFICATION_OFF … #define LIO23XX_COPPERHEAD_LED_GPIO … struct oct_mdio_cmd { … }; #define OCT_LINK_STATS_SIZE … struct oct_intrmod_cfg { … }; #define BASE_QUEUE_NOT_REQUESTED … oct_nic_if_cfg; struct lio_trusted_vf { … }; struct lio_time { … }; struct lio_vf_rep_stats { … }; enum lio_vf_rep_req_type { … }; enum { … }; #define LIO_IF_NAME_SIZE … struct lio_vf_rep_req { … }; struct lio_vf_rep_resp { … }; #endif
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