/********************************************************************** * Author: Cavium, Inc. * * Contact: [email protected] * Please include "LiquidIO" in the subject. * * Copyright (c) 2003-2016 Cavium, Inc. * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as * published by the Free Software Foundation. * * This file is distributed in the hope that it will be useful, but * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or * NONINFRINGEMENT. See the GNU General Public License for more details. ***********************************************************************/ /*! \file octeon_device.h * \brief Host Driver: This file defines the octeon device structure. */ #ifndef _OCTEON_DEVICE_H_ #define _OCTEON_DEVICE_H_ #include <linux/interrupt.h> #include <net/devlink.h> /** PCI VendorId Device Id */ #define OCTEON_CN68XX_PCIID … #define OCTEON_CN66XX_PCIID … #define OCTEON_CN23XX_PCIID_PF … /** Driver identifies chips by these Ids, created by clubbing together * DeviceId+RevisionId; Where Revision Id is not used to distinguish * between chips, a value of 0 is used for revision id. */ #define OCTEON_CN68XX … #define OCTEON_CN66XX … #define OCTEON_CN23XX_PF_VID … #define OCTEON_CN23XX_VF_VID … /**RevisionId for the chips */ #define OCTEON_CN23XX_REV_1_0 … #define OCTEON_CN23XX_REV_1_1 … #define OCTEON_CN23XX_REV_2_0 … /**SubsystemId for the chips */ #define OCTEON_CN2350_10GB_SUBSYS_ID_1 … #define OCTEON_CN2350_10GB_SUBSYS_ID_2 … #define OCTEON_CN2360_10GB_SUBSYS_ID … #define OCTEON_CN2350_25GB_SUBSYS_ID … #define OCTEON_CN2360_25GB_SUBSYS_ID … /** Endian-swap modes supported by Octeon. */ enum octeon_pci_swap_mode { … }; enum lio_fw_state { … }; enum { … }; #define OCTEON_INPUT_INTR … #define OCTEON_OUTPUT_INTR … #define OCTEON_MBOX_INTR … #define OCTEON_ALL_INTR … /*--------------- PCI BAR1 index registers -------------*/ /* BAR1 Mask */ #define PCI_BAR1_ENABLE_CA … #define PCI_BAR1_ENDIAN_MODE … #define PCI_BAR1_ENTRY_VALID … #define PCI_BAR1_MASK … /** Octeon Device state. * Each octeon device goes through each of these states * as it is initialized. */ #define OCT_DEV_BEGIN_STATE … #define OCT_DEV_PCI_ENABLE_DONE … #define OCT_DEV_PCI_MAP_DONE … #define OCT_DEV_DISPATCH_INIT_DONE … #define OCT_DEV_INSTR_QUEUE_INIT_DONE … #define OCT_DEV_SC_BUFF_POOL_INIT_DONE … #define OCT_DEV_RESP_LIST_INIT_DONE … #define OCT_DEV_DROQ_INIT_DONE … #define OCT_DEV_MBOX_SETUP_DONE … #define OCT_DEV_MSIX_ALLOC_VECTOR_DONE … #define OCT_DEV_INTR_SET_DONE … #define OCT_DEV_IO_QUEUES_DONE … #define OCT_DEV_CONSOLE_INIT_DONE … #define OCT_DEV_HOST_OK … #define OCT_DEV_CORE_OK … #define OCT_DEV_RUNNING … #define OCT_DEV_IN_RESET … #define OCT_DEV_STATE_INVALID … #define OCT_DEV_STATES … /** Octeon Device interrupts * These interrupt bits are set in int_status filed of * octeon_device structure */ #define OCT_DEV_INTR_DMA0_FORCE … #define OCT_DEV_INTR_DMA1_FORCE … #define OCT_DEV_INTR_PKT_DATA … #define LIO_RESET_SECS … /*---------------------------DISPATCH LIST-------------------------------*/ /** The dispatch list entry. * The driver keeps a record of functions registered for each * response header opcode in this structure. Since the opcode is * hashed to index into the driver's list, more than one opcode * can hash to the same entry, in which case the list field points * to a linked list with the other entries. */ struct octeon_dispatch { … }; /** The dispatch list structure. */ struct octeon_dispatch_list { … }; /*----------------------- THE OCTEON DEVICE ---------------------------*/ #define OCT_MEM_REGIONS … /** PCI address space mapping information. * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of * Octeon gets mapped to different physical address spaces in * the kernel. */ struct octeon_mmio { … }; #define MAX_OCTEON_MAPS … struct octeon_io_enable { … }; struct octeon_reg_list { … }; #define OCTEON_CONSOLE_MAX_READ_BYTES … octeon_console_print_fn; struct octeon_console { … }; struct octeon_board_info { … }; struct octeon_fn_list { … }; /* Must be multiple of 8, changing breaks ABI */ #define CVMX_BOOTMEM_NAME_LEN … /* Structure for named memory blocks * Number of descriptors * available can be changed without affecting compatibility, * but name length changes require a bump in the bootmem * descriptor version * Note: This structure must be naturally 64 bit aligned, as a single * memory image will be used by both 32 and 64 bit programs. */ struct cvmx_bootmem_named_block_desc { … }; struct oct_fw_info { … }; #define OCT_FW_VER(maj, min, rev) … /* wrappers around work structs */ struct cavium_wk { … }; struct cavium_wq { … }; struct octdev_props { … }; #define LIO_FLAG_MSIX_ENABLED … #define MSIX_PO_INT … #define MSIX_PI_INT … #define MSIX_MBOX_INT … struct octeon_pf_vf_hs_word { … }; struct octeon_sriov_info { … }; struct octeon_ioq_vector { … }; struct lio_vf_rep_list { … }; struct lio_devlink_priv { … }; /** The Octeon device. * Each Octeon device has this structure to represent all its * components. */ struct octeon_device { … }; #define OCT_DRV_ONLINE … #define OCT_DRV_OFFLINE … #define OCTEON_CN6XXX(oct) … #define OCTEON_CN23XX_PF(oct) … #define OCTEON_CN23XX_VF(oct) … #define CHIP_CONF(oct, TYPE) … #define MAX_IO_PENDING_PKT_COUNT … /*------------------ Function Prototypes ----------------------*/ /** Initialize device list memory */ void octeon_init_device_list(int conf_type); /** Free memory for Input and Output queue structures for a octeon device */ void octeon_free_device_mem(struct octeon_device *oct); /* Look up a free entry in the octeon_device table and allocate resources * for the octeon_device structure for an octeon device. Called at init * time. */ struct octeon_device *octeon_allocate_device(u32 pci_id, u32 priv_size); /** Register a device's bus location at initialization time. * @param octeon_dev - pointer to the octeon device structure. * @param bus - PCIe bus # * @param dev - PCIe device # * @param func - PCIe function # * @param is_pf - TRUE for PF, FALSE for VF * @return reference count of device's adapter */ int octeon_register_device(struct octeon_device *oct, int bus, int dev, int func, int is_pf); /** Deregister a device at de-initialization time. * @param octeon_dev - pointer to the octeon device structure. * @return reference count of device's adapter */ int octeon_deregister_device(struct octeon_device *oct); /** Initialize the driver's dispatch list which is a mix of a hash table * and a linked list. This is done at driver load time. * @param octeon_dev - pointer to the octeon device structure. * @return 0 on success, else -ve error value */ int octeon_init_dispatch_list(struct octeon_device *octeon_dev); /** Delete the driver's dispatch list and all registered entries. * This is done at driver unload time. * @param octeon_dev - pointer to the octeon device structure. */ void octeon_delete_dispatch_list(struct octeon_device *octeon_dev); /** Initialize the core device fields with the info returned by the FW. * @param recv_info - Receive info structure * @param buf - Receive buffer */ int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf); /** Gets the dispatch function registered to receive packets with a * given opcode/subcode. * @param octeon_dev - the octeon device pointer. * @param opcode - the opcode for which the dispatch function * is to checked. * @param subcode - the subcode for which the dispatch function * is to checked. * * @return Success: octeon_dispatch_fn_t (dispatch function pointer) * @return Failure: NULL * * Looks up the dispatch list to get the dispatch function for a * given opcode. */ octeon_dispatch_fn_t octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode, u16 subcode); /** Get the octeon device pointer. * @param octeon_id - The id for which the octeon device pointer is required. * @return Success: Octeon device pointer. * @return Failure: NULL. */ struct octeon_device *lio_get_device(u32 octeon_id); /** Get the octeon id assigned to the octeon device passed as argument. * This function is exported to other modules. * @param dev - octeon device pointer passed as a void *. * @return octeon device id */ int lio_get_device_id(void *dev); /** Read windowed register. * @param oct - pointer to the Octeon device. * @param addr - Address of the register to read. * * This routine is called to read from the indirectly accessed * Octeon registers that are visible through a PCI BAR0 mapped window * register. * @return - 64 bit value read from the register. */ u64 lio_pci_readq(struct octeon_device *oct, u64 addr); /** Write windowed register. * @param oct - pointer to the Octeon device. * @param val - Value to write * @param addr - Address of the register to write * * This routine is called to write to the indirectly accessed * Octeon registers that are visible through a PCI BAR0 mapped window * register. * @return Nothing. */ void lio_pci_writeq(struct octeon_device *oct, u64 val, u64 addr); /* Routines for reading and writing CSRs */ #define octeon_write_csr(oct_dev, reg_off, value) … #define octeon_write_csr64(oct_dev, reg_off, val64) … #define octeon_read_csr(oct_dev, reg_off) … #define octeon_read_csr64(oct_dev, reg_off) … /** * Checks if memory access is okay * * @param oct which octeon to send to * @return Zero on success, negative on failure. */ int octeon_mem_access_ok(struct octeon_device *oct); /** * Waits for DDR initialization. * * @param oct which octeon to send to * @param timeout_in_ms pointer to how long to wait until DDR is initialized * in ms. * If contents are 0, it waits until contents are non-zero * before starting to check. * @return Zero on success, negative on failure. */ int octeon_wait_for_ddr_init(struct octeon_device *oct, u32 *timeout_in_ms); /** * Wait for u-boot to boot and be waiting for a command. * * @param wait_time_hundredths * Maximum time to wait * * @return Zero on success, negative on failure. */ int octeon_wait_for_bootloader(struct octeon_device *oct, u32 wait_time_hundredths); /** * Initialize console access * * @param oct which octeon initialize * @return Zero on success, negative on failure. */ int octeon_init_consoles(struct octeon_device *oct); /** * Adds access to a console to the device. * * @param oct: which octeon to add to * @param console_num: which console * @param dbg_enb: ptr to debug enablement string, one of: * * NULL for no debug output (i.e. disabled) * * empty string enables debug output (via default method) * * specific string to enable debug console output * * @return Zero on success, negative on failure. */ int octeon_add_console(struct octeon_device *oct, u32 console_num, char *dbg_enb); /** write or read from a console */ int octeon_console_write(struct octeon_device *oct, u32 console_num, char *buffer, u32 write_request_size, u32 flags); int octeon_console_write_avail(struct octeon_device *oct, u32 console_num); int octeon_console_read_avail(struct octeon_device *oct, u32 console_num); /** Removes all attached consoles. */ void octeon_remove_consoles(struct octeon_device *oct); /** * Send a string to u-boot on console 0 as a command. * * @param oct which octeon to send to * @param cmd_str String to send * @param wait_hundredths Time to wait for u-boot to accept the command. * * @return Zero on success, negative on failure. */ int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str, u32 wait_hundredths); /** Parses, validates, and downloads firmware, then boots associated cores. * @param oct which octeon to download firmware to * @param data - The complete firmware file image * @param size - The size of the data * * @return 0 if success. * -EINVAL if file is incompatible or badly formatted. * -ENODEV if no handler was found for the application type or an * invalid octeon id was passed. */ int octeon_download_firmware(struct octeon_device *oct, const u8 *data, size_t size); char *lio_get_state_string(atomic_t *state_ptr); /** Sets up instruction queues for the device * @param oct which octeon to setup * * @return 0 if success. 1 if fails */ int octeon_setup_instr_queues(struct octeon_device *oct); /** Sets up output queues for the device * @param oct which octeon to setup * * @return 0 if success. 1 if fails */ int octeon_setup_output_queues(struct octeon_device *oct); int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no); int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no); /** Turns off the input and output queues for the device * @param oct which octeon to disable */ int octeon_set_io_queues_off(struct octeon_device *oct); /** Turns on or off the given output queue for the device * @param oct which octeon to change * @param q_no which queue * @param enable 1 to enable, 0 to disable */ void octeon_set_droq_pkt_op(struct octeon_device *oct, u32 q_no, u32 enable); /** Retrieve the config for the device * @param oct which octeon * @param card_type type of card * * @returns pointer to configuration */ void *oct_get_config_info(struct octeon_device *oct, u16 card_type); /** Gets the octeon device configuration * @return - pointer to the octeon configuration struture */ struct octeon_config *octeon_get_conf(struct octeon_device *oct); void octeon_free_ioq_vector(struct octeon_device *oct); int octeon_allocate_ioq_vector(struct octeon_device *oct, u32 num_ioqs); void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq); /* LiquidIO driver pivate flags */ enum { … }; #define OCT_PRIV_FLAG_DEFAULT … static inline u32 lio_get_priv_flag(struct octeon_device *octdev, u32 flag) { … } static inline void lio_set_priv_flag(struct octeon_device *octdev, u32 flag, u32 val) { … } #endif
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