/********************************************************************** * Author: Cavium, Inc. * * Contact: [email protected] * Please include "LiquidIO" in the subject. * * Copyright (c) 2003-2016 Cavium, Inc. * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as * published by the Free Software Foundation. * * This file is distributed in the hope that it will be useful, but * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or * NONINFRINGEMENT. See the GNU General Public License for more details. ***********************************************************************/ /*! \file cn66xx_regs.h * \brief Host Driver: Register Address and Register Mask values for * Octeon CN66XX devices. */ #ifndef __CN66XX_REGS_H__ #define __CN66XX_REGS_H__ #define CN6XXX_XPANSION_BAR … #define CN6XXX_MSI_CAP … #define CN6XXX_MSI_ADDR_LO … #define CN6XXX_MSI_ADDR_HI … #define CN6XXX_MSI_DATA … #define CN6XXX_PCIE_CAP … #define CN6XXX_PCIE_DEVCAP … #define CN6XXX_PCIE_DEVCTL … #define CN6XXX_PCIE_LINKCAP … #define CN6XXX_PCIE_LINKCTL … #define CN6XXX_PCIE_SLOTCAP … #define CN6XXX_PCIE_SLOTCTL … #define CN6XXX_PCIE_ENH_CAP … #define CN6XXX_PCIE_UNCORR_ERR_STATUS … #define CN6XXX_PCIE_UNCORR_ERR_MASK … #define CN6XXX_PCIE_UNCORR_ERR … #define CN6XXX_PCIE_CORR_ERR_STATUS … #define CN6XXX_PCIE_CORR_ERR_MASK … #define CN6XXX_PCIE_ADV_ERR_CAP … #define CN6XXX_PCIE_ACK_REPLAY_TIMER … #define CN6XXX_PCIE_OTHER_MSG … #define CN6XXX_PCIE_PORT_FORCE_LINK … #define CN6XXX_PCIE_ACK_FREQ … #define CN6XXX_PCIE_PORT_LINK_CTL … #define CN6XXX_PCIE_LANE_SKEW … #define CN6XXX_PCIE_SYM_NUM … #define CN6XXX_PCIE_FLTMSK … /* ############## BAR0 Registers ################ */ #define CN6XXX_SLI_CTL_PORT0 … #define CN6XXX_SLI_CTL_PORT1 … #define CN6XXX_SLI_WINDOW_CTL … #define CN6XXX_SLI_DBG_DATA … #define CN6XXX_SLI_SCRATCH1 … #define CN6XXX_SLI_SCRATCH2 … #define CN6XXX_SLI_CTL_STATUS … #define CN6XXX_WIN_WR_ADDR_LO … #define CN6XXX_WIN_WR_ADDR_HI … #define CN6XXX_WIN_WR_ADDR64 … #define CN6XXX_WIN_RD_ADDR_LO … #define CN6XXX_WIN_RD_ADDR_HI … #define CN6XXX_WIN_RD_ADDR64 … #define CN6XXX_WIN_WR_DATA_LO … #define CN6XXX_WIN_WR_DATA_HI … #define CN6XXX_WIN_WR_DATA64 … #define CN6XXX_WIN_RD_DATA_LO … #define CN6XXX_WIN_RD_DATA_HI … #define CN6XXX_WIN_RD_DATA64 … #define CN6XXX_WIN_WR_MASK_LO … #define CN6XXX_WIN_WR_MASK_HI … #define CN6XXX_WIN_WR_MASK_REG … /* 1 register (32-bit) to enable Input queues */ #define CN6XXX_SLI_PKT_INSTR_ENB … /* 1 register (32-bit) to enable Output queues */ #define CN6XXX_SLI_PKT_OUT_ENB … /* 1 register (32-bit) to determine whether Output queues are in reset. */ #define CN6XXX_SLI_PORT_IN_RST_OQ … /* 1 register (32-bit) to determine whether Input queues are in reset. */ #define CN6XXX_SLI_PORT_IN_RST_IQ … /*###################### REQUEST QUEUE #########################*/ /* 1 register (32-bit) - instr. size of each input queue. */ #define CN6XXX_SLI_PKT_INSTR_SIZE … /* 32 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */ #define CN6XXX_SLI_IQ_INSTR_COUNT_START … /* 32 registers for Input Queue Start Addr - SLI_PKT0_INSTR_BADDR */ #define CN6XXX_SLI_IQ_BASE_ADDR_START64 … /* 32 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */ #define CN6XXX_SLI_IQ_DOORBELL_START … /* 32 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */ #define CN6XXX_SLI_IQ_SIZE_START … /* 32 registers for Instruction Header Options - SLI_PKT0_INSTR_HEADER */ #define CN6XXX_SLI_IQ_PKT_INSTR_HDR_START64 … /* 1 register (64-bit) - Back Pressure for each input queue - SLI_PKT0_IN_BP */ #define CN66XX_SLI_INPUT_BP_START64 … /* Each Input Queue register is at a 16-byte Offset in BAR0 */ #define CN6XXX_IQ_OFFSET … /* 1 register (32-bit) - ES, RO, NS, Arbitration for Input Queue Data & * gather list fetches. SLI_PKT_INPUT_CONTROL. */ #define CN6XXX_SLI_PKT_INPUT_CONTROL … /* 1 register (64-bit) - Number of instructions to read at one time * - 2 bits for each input ring. SLI_PKT_INSTR_RD_SIZE. */ #define CN6XXX_SLI_PKT_INSTR_RD_SIZE … /* 1 register (64-bit) - Assign Input ring to MAC port * - 2 bits for each input ring. SLI_PKT_IN_PCIE_PORT. */ #define CN6XXX_SLI_IN_PCIE_PORT … /*------- Request Queue Macros ---------*/ #define CN6XXX_SLI_IQ_BASE_ADDR64(iq) … #define CN6XXX_SLI_IQ_SIZE(iq) … #define CN6XXX_SLI_IQ_PKT_INSTR_HDR64(iq) … #define CN6XXX_SLI_IQ_DOORBELL(iq) … #define CN6XXX_SLI_IQ_INSTR_COUNT(iq) … #define CN66XX_SLI_IQ_BP64(iq) … /*------------------ Masks ----------------*/ #define CN6XXX_INPUT_CTL_ROUND_ROBIN_ARB … #define CN6XXX_INPUT_CTL_DATA_NS … #define CN6XXX_INPUT_CTL_DATA_ES_64B_SWAP … #define CN6XXX_INPUT_CTL_DATA_RO … #define CN6XXX_INPUT_CTL_USE_CSR … #define CN6XXX_INPUT_CTL_GATHER_NS … #define CN6XXX_INPUT_CTL_GATHER_ES_64B_SWAP … #define CN6XXX_INPUT_CTL_GATHER_RO … #ifdef __BIG_ENDIAN_BITFIELD #define CN6XXX_INPUT_CTL_MASK … #else #define CN6XXX_INPUT_CTL_MASK … #endif /*############################ OUTPUT QUEUE #########################*/ /* 32 registers for Output queue buffer and info size - SLI_PKT0_OUT_SIZE */ #define CN6XXX_SLI_OQ0_BUFF_INFO_SIZE … /* 32 registers for Output Queue Start Addr - SLI_PKT0_SLIST_BADDR */ #define CN6XXX_SLI_OQ_BASE_ADDR_START64 … /* 32 registers for Output Queue Packet Credits - SLI_PKT0_SLIST_BAOFF_DBELL */ #define CN6XXX_SLI_OQ_PKT_CREDITS_START … /* 32 registers for Output Queue size - SLI_PKT0_SLIST_FIFO_RSIZE */ #define CN6XXX_SLI_OQ_SIZE_START … /* 32 registers for Output Queue Packet Count - SLI_PKT0_CNTS */ #define CN6XXX_SLI_OQ_PKT_SENT_START … /* Each Output Queue register is at a 16-byte Offset in BAR0 */ #define CN6XXX_OQ_OFFSET … /* 1 register (32-bit) - 1 bit for each output queue * - Relaxed Ordering setting for reading Output Queues descriptors * - SLI_PKT_SLIST_ROR */ #define CN6XXX_SLI_PKT_SLIST_ROR … /* 1 register (32-bit) - 1 bit for each output queue * - No Snoop mode for reading Output Queues descriptors * - SLI_PKT_SLIST_NS */ #define CN6XXX_SLI_PKT_SLIST_NS … /* 1 register (64-bit) - 2 bits for each output queue * - Endian-Swap mode for reading Output Queue descriptors * - SLI_PKT_SLIST_ES */ #define CN6XXX_SLI_PKT_SLIST_ES64 … /* 1 register (32-bit) - 1 bit for each output queue * - InfoPtr mode for Output Queues. * - SLI_PKT_IPTR */ #define CN6XXX_SLI_PKT_IPTR … /* 1 register (32-bit) - 1 bit for each output queue * - DPTR format selector for Output queues. * - SLI_PKT_DPADDR */ #define CN6XXX_SLI_PKT_DPADDR … /* 1 register (32-bit) - 1 bit for each output queue * - Relaxed Ordering setting for reading Output Queues data * - SLI_PKT_DATA_OUT_ROR */ #define CN6XXX_SLI_PKT_DATA_OUT_ROR … /* 1 register (32-bit) - 1 bit for each output queue * - No Snoop mode for reading Output Queues data * - SLI_PKT_DATA_OUT_NS */ #define CN6XXX_SLI_PKT_DATA_OUT_NS … /* 1 register (64-bit) - 2 bits for each output queue * - Endian-Swap mode for reading Output Queue data * - SLI_PKT_DATA_OUT_ES */ #define CN6XXX_SLI_PKT_DATA_OUT_ES64 … /* 1 register (32-bit) - 1 bit for each output queue * - Controls whether SLI_PKTn_CNTS is incremented for bytes or for packets. * - SLI_PKT_OUT_BMODE */ #define CN6XXX_SLI_PKT_OUT_BMODE … /* 1 register (64-bit) - 2 bits for each output queue * - Assign PCIE port for Output queues * - SLI_PKT_PCIE_PORT. */ #define CN6XXX_SLI_PKT_PCIE_PORT64 … /* 1 (64-bit) register for Output Queue Packet Count Interrupt Threshold * & Time Threshold. The same setting applies to all 32 queues. * The register is defined as a 64-bit registers, but we use the * 32-bit offsets to define distinct addresses. */ #define CN6XXX_SLI_OQ_INT_LEVEL_PKTS … #define CN6XXX_SLI_OQ_INT_LEVEL_TIME … /* 1 (64-bit register) for Output Queue backpressure across all rings. */ #define CN6XXX_SLI_OQ_WMARK … /* 1 register to control output queue global backpressure & ring enable. */ #define CN6XXX_SLI_PKT_CTL … /*------- Output Queue Macros ---------*/ #define CN6XXX_SLI_OQ_BASE_ADDR64(oq) … #define CN6XXX_SLI_OQ_SIZE(oq) … #define CN6XXX_SLI_OQ_BUFF_INFO_SIZE(oq) … #define CN6XXX_SLI_OQ_PKTS_SENT(oq) … #define CN6XXX_SLI_OQ_PKTS_CREDIT(oq) … /*######################### DMA Counters #########################*/ /* 2 registers (64-bit) - DMA Count - 1 for each DMA counter 0/1. */ #define CN6XXX_DMA_CNT_START … /* 2 registers (64-bit) - DMA Timer 0/1, contains DMA timer values * SLI_DMA_0_TIM */ #define CN6XXX_DMA_TIM_START … /* 2 registers (64-bit) - DMA count & Time Interrupt threshold - * SLI_DMA_0_INT_LEVEL */ #define CN6XXX_DMA_INT_LEVEL_START … /* Each DMA register is at a 16-byte Offset in BAR0 */ #define CN6XXX_DMA_OFFSET … /*---------- DMA Counter Macros ---------*/ #define CN6XXX_DMA_CNT(dq) … #define CN6XXX_DMA_INT_LEVEL(dq) … #define CN6XXX_DMA_PKT_INT_LEVEL(dq) … #define CN6XXX_DMA_TIME_INT_LEVEL(dq) … #define CN6XXX_DMA_TIM(dq) … /*######################## INTERRUPTS #########################*/ /* 1 register (64-bit) for Interrupt Summary */ #define CN6XXX_SLI_INT_SUM64 … /* 1 register (64-bit) for Interrupt Enable */ #define CN6XXX_SLI_INT_ENB64_PORT0 … #define CN6XXX_SLI_INT_ENB64_PORT1 … /* 1 register (32-bit) to enable Output Queue Packet/Byte Count Interrupt */ #define CN6XXX_SLI_PKT_CNT_INT_ENB … /* 1 register (32-bit) to enable Output Queue Packet Timer Interrupt */ #define CN6XXX_SLI_PKT_TIME_INT_ENB … /* 1 register (32-bit) to indicate which Output Queue reached pkt threshold */ #define CN6XXX_SLI_PKT_CNT_INT … /* 1 register (32-bit) to indicate which Output Queue reached time threshold */ #define CN6XXX_SLI_PKT_TIME_INT … /*------------------ Interrupt Masks ----------------*/ #define CN6XXX_INTR_RML_TIMEOUT_ERR … #define CN6XXX_INTR_BAR0_RW_TIMEOUT_ERR … #define CN6XXX_INTR_IO2BIG_ERR … #define CN6XXX_INTR_PKT_COUNT … #define CN6XXX_INTR_PKT_TIME … #define CN6XXX_INTR_M0UPB0_ERR … #define CN6XXX_INTR_M0UPWI_ERR … #define CN6XXX_INTR_M0UNB0_ERR … #define CN6XXX_INTR_M0UNWI_ERR … #define CN6XXX_INTR_M1UPB0_ERR … #define CN6XXX_INTR_M1UPWI_ERR … #define CN6XXX_INTR_M1UNB0_ERR … #define CN6XXX_INTR_M1UNWI_ERR … #define CN6XXX_INTR_MIO_INT0 … #define CN6XXX_INTR_MIO_INT1 … #define CN6XXX_INTR_MAC_INT0 … #define CN6XXX_INTR_MAC_INT1 … #define CN6XXX_INTR_DMA0_FORCE … #define CN6XXX_INTR_DMA1_FORCE … #define CN6XXX_INTR_DMA0_COUNT … #define CN6XXX_INTR_DMA1_COUNT … #define CN6XXX_INTR_DMA0_TIME … #define CN6XXX_INTR_DMA1_TIME … #define CN6XXX_INTR_INSTR_DB_OF_ERR … #define CN6XXX_INTR_SLIST_DB_OF_ERR … #define CN6XXX_INTR_POUT_ERR … #define CN6XXX_INTR_PIN_BP_ERR … #define CN6XXX_INTR_PGL_ERR … #define CN6XXX_INTR_PDI_ERR … #define CN6XXX_INTR_POP_ERR … #define CN6XXX_INTR_PINS_ERR … #define CN6XXX_INTR_SPRT0_ERR … #define CN6XXX_INTR_SPRT1_ERR … #define CN6XXX_INTR_ILL_PAD_ERR … #define CN6XXX_INTR_DMA0_DATA … #define CN6XXX_INTR_DMA1_DATA … #define CN6XXX_INTR_DMA_DATA … #define CN6XXX_INTR_PKT_DATA … /* Sum of interrupts for all PCI-Express Data Interrupts */ #define CN6XXX_INTR_PCIE_DATA … #define CN6XXX_INTR_MIO … #define CN6XXX_INTR_MAC … /* Sum of interrupts for error events */ #define CN6XXX_INTR_ERR … /* Programmed Mask for Interrupt Sum */ #define CN6XXX_INTR_MASK … #define CN6XXX_SLI_S2M_PORT0_CTL … #define CN6XXX_SLI_S2M_PORT1_CTL … #define CN6XXX_SLI_S2M_PORTX_CTL(port) … #define CN6XXX_SLI_INT_ENB64(port) … #define CN6XXX_SLI_MAC_NUMBER … /* CN6XXX BAR1 Index registers. */ #define CN6XXX_PEM_BAR1_INDEX000 … #define CN6XXX_PEM_OFFSET … #define CN6XXX_BAR1_INDEX_START … #define CN6XXX_PCI_BAR1_OFFSET … #define CN6XXX_BAR1_REG(idx, port) … /*############################ DPI #########################*/ #define CN6XXX_DPI_CTL … #define CN6XXX_DPI_DMA_CONTROL … #define CN6XXX_DPI_REQ_GBL_ENB … #define CN6XXX_DPI_REQ_ERR_RSP … #define CN6XXX_DPI_REQ_ERR_RST … #define CN6XXX_DPI_DMA_ENG0_ENB … #define CN6XXX_DPI_DMA_ENG_ENB(q_no) … #define CN6XXX_DPI_DMA_ENG0_BUF … #define CN6XXX_DPI_DMA_ENG_BUF(q_no) … #define CN6XXX_DPI_SLI_PRT0_CFG … #define CN6XXX_DPI_SLI_PRT1_CFG … #define CN6XXX_DPI_SLI_PRTX_CFG(port) … #define CN6XXX_DPI_DMA_COMMIT_MODE … #define CN6XXX_DPI_DMA_PKT_HP … #define CN6XXX_DPI_DMA_PKT_EN … #define CN6XXX_DPI_DMA_O_ES … #define CN6XXX_DPI_DMA_O_MODE … #define CN6XXX_DPI_DMA_CTL_MASK … /*############################ CIU #########################*/ #define CN6XXX_CIU_SOFT_BIST … #define CN6XXX_CIU_SOFT_RST … /*############################ MIO #########################*/ #define CN6XXX_MIO_PTP_CLOCK_CFG … #define CN6XXX_MIO_PTP_CLOCK_LO … #define CN6XXX_MIO_PTP_CLOCK_HI … #define CN6XXX_MIO_PTP_CLOCK_COMP … #define CN6XXX_MIO_PTP_TIMESTAMP … #define CN6XXX_MIO_PTP_EVT_CNT … #define CN6XXX_MIO_PTP_CKOUT_THRESH_LO … #define CN6XXX_MIO_PTP_CKOUT_THRESH_HI … #define CN6XXX_MIO_PTP_CKOUT_HI_INCR … #define CN6XXX_MIO_PTP_CKOUT_LO_INCR … #define CN6XXX_MIO_PTP_PPS_THRESH_LO … #define CN6XXX_MIO_PTP_PPS_THRESH_HI … #define CN6XXX_MIO_PTP_PPS_HI_INCR … #define CN6XXX_MIO_PTP_PPS_LO_INCR … #define CN6XXX_MIO_QLM4_CFG … #define CN6XXX_MIO_RST_BOOT … #define CN6XXX_MIO_QLM_CFG_MASK … /*############################ LMC #########################*/ #define CN6XXX_LMC0_RESET_CTL … #define CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK … #endif
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