/********************************************************************** * Author: Cavium, Inc. * * Contact: [email protected] * Please include "LiquidIO" in the subject. * * Copyright (c) 2003-2016 Cavium, Inc. * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as * published by the Free Software Foundation. * * This file is distributed in the hope that it will be useful, but * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or * NONINFRINGEMENT. See the GNU General Public License for more details. ***********************************************************************/ /*! \file cn23xx_regs.h * \brief Host Driver: Register Address and Register Mask values for * Octeon CN23XX devices. */ #ifndef __CN23XX_PF_REGS_H__ #define __CN23XX_PF_REGS_H__ #define CN23XX_CONFIG_VENDOR_ID … #define CN23XX_CONFIG_DEVICE_ID … #define CN23XX_CONFIG_XPANSION_BAR … #define CN23XX_CONFIG_MSIX_CAP … #define CN23XX_CONFIG_MSIX_LMSI … #define CN23XX_CONFIG_MSIX_UMSI … #define CN23XX_CONFIG_MSIX_MSIMD … #define CN23XX_CONFIG_MSIX_MSIMM … #define CN23XX_CONFIG_MSIX_MSIMP … #define CN23XX_CONFIG_PCIE_CAP … #define CN23XX_CONFIG_PCIE_DEVCAP … #define CN23XX_CONFIG_PCIE_DEVCTL … #define CN23XX_CONFIG_PCIE_LINKCAP … #define CN23XX_CONFIG_PCIE_LINKCTL … #define CN23XX_CONFIG_PCIE_SLOTCAP … #define CN23XX_CONFIG_PCIE_SLOTCTL … #define CN23XX_CONFIG_PCIE_DEVCTL2 … #define CN23XX_CONFIG_PCIE_LINKCTL2 … #define CN23XX_CONFIG_PCIE_UNCORRECT_ERR_MASK … #define CN23XX_CONFIG_PCIE_CORRECT_ERR_STATUS … #define CN23XX_CONFIG_PCIE_DEVCTL_MASK … #define CN23XX_PCIE_SRIOV_FDL … #define CN23XX_PCIE_SRIOV_FDL_BIT_POS … #define CN23XX_PCIE_SRIOV_FDL_MASK … #define CN23XX_CONFIG_PCIE_FLTMSK … #define CN23XX_CONFIG_SRIOV_VFDEVID … #define CN23XX_CONFIG_SRIOV_BAR_START … #define CN23XX_CONFIG_SRIOV_BARX(i) … #define CN23XX_CONFIG_SRIOV_BAR_PF … #define CN23XX_CONFIG_SRIOV_BAR_64BIT … #define CN23XX_CONFIG_SRIOV_BAR_IO … /* ############## BAR0 Registers ################ */ #define CN23XX_SLI_CTL_PORT_START … #define CN23XX_PORT_OFFSET … #define CN23XX_SLI_CTL_PORT(p) … /* 2 scatch registers (64-bit) */ #define CN23XX_SLI_WINDOW_CTL … #define CN23XX_SLI_SCRATCH1 … #define CN23XX_SLI_SCRATCH2 … #define CN23XX_SLI_WINDOW_CTL_DEFAULT … /* 1 registers (64-bit) - SLI_CTL_STATUS */ #define CN23XX_SLI_CTL_STATUS … /* SLI Packet Input Jabber Register (64 bit register) * <31:0> for Byte count for limiting sizes of packet sizes * that are allowed for sli packet inbound packets. * the default value is 0xFA00(=64000). */ #define CN23XX_SLI_PKT_IN_JABBER … /* The input jabber is used to determine the TSO max size. * Due to H/W limitation, this needs to be reduced to 60000 * in order to use H/W TSO and avoid the WQE malformation * PKO_BUG_24989_WQE_LEN */ #define CN23XX_DEFAULT_INPUT_JABBER … #define CN23XX_WIN_WR_ADDR_LO … #define CN23XX_WIN_WR_ADDR_HI … #define CN23XX_WIN_WR_ADDR64 … #define CN23XX_WIN_RD_ADDR_LO … #define CN23XX_WIN_RD_ADDR_HI … #define CN23XX_WIN_RD_ADDR64 … #define CN23XX_WIN_WR_DATA_LO … #define CN23XX_WIN_WR_DATA_HI … #define CN23XX_WIN_WR_DATA64 … #define CN23XX_WIN_RD_DATA_LO … #define CN23XX_WIN_RD_DATA_HI … #define CN23XX_WIN_RD_DATA64 … #define CN23XX_WIN_WR_MASK_LO … #define CN23XX_WIN_WR_MASK_HI … #define CN23XX_WIN_WR_MASK_REG … #define CN23XX_SLI_MAC_CREDIT_CNT … /* 4 registers (64-bit) for mapping IOQs to MACs(PEMs)- * SLI_PKT_MAC(0..3)_PF(0..1)_RINFO */ #define CN23XX_SLI_PKT_MAC_RINFO_START64 … /*1 register (64-bit) to determine whether IOQs are in reset. */ #define CN23XX_SLI_PKT_IOQ_RING_RST … /* Each Input Queue register is at a 16-byte Offset in BAR0 */ #define CN23XX_IQ_OFFSET … #define CN23XX_MAC_RINFO_OFFSET … #define CN23XX_PF_RINFO_OFFSET … #define CN23XX_SLI_PKT_MAC_RINFO64(mac, pf) … /** mask for total rings, setting TRS to base */ #define CN23XX_PKT_MAC_CTL_RINFO_TRS … /** mask for starting ring number: setting SRN <6:0> = 0x7F */ #define CN23XX_PKT_MAC_CTL_RINFO_SRN … /* Starting bit of the TRS field in CN23XX_SLI_PKT_MAC_RINFO64 register */ #define CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS … /* Starting bit of SRN field in CN23XX_SLI_PKT_MAC_RINFO64 register */ #define CN23XX_PKT_MAC_CTL_RINFO_SRN_BIT_POS … /* Starting bit of RPVF field in CN23XX_SLI_PKT_MAC_RINFO64 register */ #define CN23XX_PKT_MAC_CTL_RINFO_RPVF_BIT_POS … /* Starting bit of NVFS field in CN23XX_SLI_PKT_MAC_RINFO64 register */ #define CN23XX_PKT_MAC_CTL_RINFO_NVFS_BIT_POS … /*###################### REQUEST QUEUE #########################*/ /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */ #define CN23XX_SLI_IQ_INSTR_COUNT_START64 … /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */ #define CN23XX_SLI_IQ_BASE_ADDR_START64 … /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */ #define CN23XX_SLI_IQ_DOORBELL_START … /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */ #define CN23XX_SLI_IQ_SIZE_START … /* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data & * gather list fetches. SLI_PKT(0..63)_INPUT_CONTROL. */ #define CN23XX_SLI_IQ_PKT_CONTROL_START64 … /*------- Request Queue Macros ---------*/ #define CN23XX_SLI_IQ_PKT_CONTROL64(iq) … #define CN23XX_SLI_IQ_BASE_ADDR64(iq) … #define CN23XX_SLI_IQ_SIZE(iq) … #define CN23XX_SLI_IQ_DOORBELL(iq) … #define CN23XX_SLI_IQ_INSTR_COUNT64(iq) … /*------------------ Masks ----------------*/ #define CN23XX_PKT_INPUT_CTL_VF_NUM … #define CN23XX_PKT_INPUT_CTL_MAC_NUM … /* Number of instructions to be read in one MAC read request. * setting to Max value(4) */ #define CN23XX_PKT_INPUT_CTL_RDSIZE … #define CN23XX_PKT_INPUT_CTL_IS_64B … #define CN23XX_PKT_INPUT_CTL_RST … #define CN23XX_PKT_INPUT_CTL_QUIET … #define CN23XX_PKT_INPUT_CTL_RING_ENB … #define CN23XX_PKT_INPUT_CTL_DATA_NS … #define CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP … #define CN23XX_PKT_INPUT_CTL_DATA_RO … #define CN23XX_PKT_INPUT_CTL_USE_CSR … #define CN23XX_PKT_INPUT_CTL_GATHER_NS … #define CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP … #define CN23XX_PKT_INPUT_CTL_GATHER_RO … /** Rings per Virtual Function **/ #define CN23XX_PKT_INPUT_CTL_RPVF_MASK … #define CN23XX_PKT_INPUT_CTL_RPVF_POS … /** These bits[47:44] select the Physical function number within the MAC */ #define CN23XX_PKT_INPUT_CTL_PF_NUM_MASK … #define CN23XX_PKT_INPUT_CTL_PF_NUM_POS … /** These bits[43:32] select the function number within the PF */ #define CN23XX_PKT_INPUT_CTL_VF_NUM_MASK … #define CN23XX_PKT_INPUT_CTL_VF_NUM_POS … #define CN23XX_PKT_INPUT_CTL_MAC_NUM_MASK … #define CN23XX_PKT_INPUT_CTL_MAC_NUM_POS … #define CN23XX_PKT_IN_DONE_WMARK_MASK … #define CN23XX_PKT_IN_DONE_WMARK_BIT_POS … #define CN23XX_PKT_IN_DONE_CNT_MASK … #ifdef __LITTLE_ENDIAN_BITFIELD #define CN23XX_PKT_INPUT_CTL_MASK … #else #define CN23XX_PKT_INPUT_CTL_MASK … #endif /** Masks for SLI_PKT_IN_DONE(0..63)_CNTS Register */ #define CN23XX_IN_DONE_CNTS_PI_INT … #define CN23XX_IN_DONE_CNTS_CINT_ENB … /*############################ OUTPUT QUEUE #########################*/ /* 64 registers for Output queue control - SLI_PKT(0..63)_OUTPUT_CONTROL */ #define CN23XX_SLI_OQ_PKT_CONTROL_START … /* 64 registers for Output queue buffer and info size - SLI_PKT0_OUT_SIZE */ #define CN23XX_SLI_OQ0_BUFF_INFO_SIZE … /* 64 registers for Output Queue Start Addr - SLI_PKT0_SLIST_BADDR */ #define CN23XX_SLI_OQ_BASE_ADDR_START64 … /* 64 registers for Output Queue Packet Credits - SLI_PKT0_SLIST_BAOFF_DBELL */ #define CN23XX_SLI_OQ_PKT_CREDITS_START … /* 64 registers for Output Queue size - SLI_PKT0_SLIST_FIFO_RSIZE */ #define CN23XX_SLI_OQ_SIZE_START … /* 64 registers for Output Queue Packet Count - SLI_PKT0_CNTS */ #define CN23XX_SLI_OQ_PKT_SENT_START … /* 64 registers for Output Queue INT Levels - SLI_PKT0_INT_LEVELS */ #define CN23XX_SLI_OQ_PKT_INT_LEVELS_START64 … /* Each Output Queue register is at a 16-byte Offset in BAR0 */ #define CN23XX_OQ_OFFSET … /* 1 (64-bit register) for Output Queue backpressure across all rings. */ #define CN23XX_SLI_OQ_WMARK … /* Global pkt control register */ #define CN23XX_SLI_GBL_CONTROL … /* Backpressure enable register for PF0 */ #define CN23XX_SLI_OUT_BP_EN_W1S … /* Backpressure enable register for PF1 */ #define CN23XX_SLI_OUT_BP_EN2_W1S … /* Backpressure disable register for PF0 */ #define CN23XX_SLI_OUT_BP_EN_W1C … /* Backpressure disable register for PF1 */ #define CN23XX_SLI_OUT_BP_EN2_W1C … /*------- Output Queue Macros ---------*/ #define CN23XX_SLI_OQ_PKT_CONTROL(oq) … #define CN23XX_SLI_OQ_BASE_ADDR64(oq) … #define CN23XX_SLI_OQ_SIZE(oq) … #define CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq) … #define CN23XX_SLI_OQ_PKTS_SENT(oq) … #define CN23XX_SLI_OQ_PKTS_CREDIT(oq) … #define CN23XX_SLI_OQ_PKT_INT_LEVELS(oq) … /*Macro's for accessing CNT and TIME separately from INT_LEVELS*/ #define CN23XX_SLI_OQ_PKT_INT_LEVELS_CNT(oq) … #define CN23XX_SLI_OQ_PKT_INT_LEVELS_TIME(oq) … /*------------------ Masks ----------------*/ #define CN23XX_PKT_OUTPUT_CTL_TENB … #define CN23XX_PKT_OUTPUT_CTL_CENB … #define CN23XX_PKT_OUTPUT_CTL_IPTR … #define CN23XX_PKT_OUTPUT_CTL_ES … #define CN23XX_PKT_OUTPUT_CTL_NSR … #define CN23XX_PKT_OUTPUT_CTL_ROR … #define CN23XX_PKT_OUTPUT_CTL_DPTR … #define CN23XX_PKT_OUTPUT_CTL_BMODE … #define CN23XX_PKT_OUTPUT_CTL_ES_P … #define CN23XX_PKT_OUTPUT_CTL_NSR_P … #define CN23XX_PKT_OUTPUT_CTL_ROR_P … #define CN23XX_PKT_OUTPUT_CTL_RING_ENB … /*######################### Mailbox Reg Macros ########################*/ #define CN23XX_SLI_PKT_MBOX_INT_START … #define CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START … #define CN23XX_SLI_MAC_PF_MBOX_INT_START … #define CN23XX_SLI_MBOX_OFFSET … #define CN23XX_SLI_MBOX_SIG_IDX_OFFSET … #define CN23XX_SLI_PKT_MBOX_INT(q) … #define CN23XX_SLI_PKT_PF_VF_MBOX_SIG(q, idx) … #define CN23XX_SLI_MAC_PF_MBOX_INT(mac, pf) … /*######################### DMA Counters #########################*/ /* 2 registers (64-bit) - DMA Count - 1 for each DMA counter 0/1. */ #define CN23XX_DMA_CNT_START … /* 2 registers (64-bit) - DMA Timer 0/1, contains DMA timer values */ /* SLI_DMA_0_TIM */ #define CN23XX_DMA_TIM_START … /* 2 registers (64-bit) - DMA count & Time Interrupt threshold - * SLI_DMA_0_INT_LEVEL */ #define CN23XX_DMA_INT_LEVEL_START … /* Each DMA register is at a 16-byte Offset in BAR0 */ #define CN23XX_DMA_OFFSET … /*---------- DMA Counter Macros ---------*/ #define CN23XX_DMA_CNT(dq) … #define CN23XX_DMA_INT_LEVEL(dq) … #define CN23XX_DMA_PKT_INT_LEVEL(dq) … #define CN23XX_DMA_TIME_INT_LEVEL(dq) … #define CN23XX_DMA_TIM(dq) … /*######################## MSIX TABLE #########################*/ #define CN23XX_MSIX_TABLE_ADDR_START … #define CN23XX_MSIX_TABLE_DATA_START … #define CN23XX_MSIX_TABLE_SIZE … #define CN23XX_MSIX_TABLE_ENTRIES … #define CN23XX_MSIX_ENTRY_VECTOR_CTL … #define CN23XX_MSIX_TABLE_ADDR(idx) … #define CN23XX_MSIX_TABLE_DATA(idx) … /*######################## INTERRUPTS #########################*/ #define CN23XX_MAC_INT_OFFSET … #define CN23XX_PF_INT_OFFSET … /* 1 register (64-bit) for Interrupt Summary */ #define CN23XX_SLI_INT_SUM64 … /* 4 registers (64-bit) for Interrupt Enable for each Port */ #define CN23XX_SLI_INT_ENB64 … #define CN23XX_SLI_MAC_PF_INT_SUM64(mac, pf) … #define CN23XX_SLI_MAC_PF_INT_ENB64(mac, pf) … /* 1 register (64-bit) to indicate which Output Queue reached pkt threshold */ #define CN23XX_SLI_PKT_CNT_INT … /* 1 register (64-bit) to indicate which Output Queue reached time threshold */ #define CN23XX_SLI_PKT_TIME_INT … /*------------------ Interrupt Masks ----------------*/ #define CN23XX_INTR_PO_INT … #define CN23XX_INTR_PI_INT … #define CN23XX_INTR_MBOX_INT … #define CN23XX_INTR_RESEND … #define CN23XX_INTR_CINT_ENB … #define CN23XX_INTR_MBOX_ENB … #define CN23XX_INTR_RML_TIMEOUT_ERR … #define CN23XX_INTR_MIO_INT … #define CN23XX_INTR_RESERVED1 … #define CN23XX_INTR_PKT_COUNT … #define CN23XX_INTR_PKT_TIME … #define CN23XX_INTR_RESERVED2 … #define CN23XX_INTR_M0UPB0_ERR … #define CN23XX_INTR_M0UPWI_ERR … #define CN23XX_INTR_M0UNB0_ERR … #define CN23XX_INTR_M0UNWI_ERR … #define CN23XX_INTR_RESERVED3 … #define CN23XX_INTR_DMA0_FORCE … #define CN23XX_INTR_DMA1_FORCE … #define CN23XX_INTR_DMA0_COUNT … #define CN23XX_INTR_DMA1_COUNT … #define CN23XX_INTR_DMA0_TIME … #define CN23XX_INTR_DMA1_TIME … #define CN23XX_INTR_RESERVED4 … #define CN23XX_INTR_VF_MBOX … #define CN23XX_INTR_DMAVF_ERR … #define CN23XX_INTR_DMAPF_ERR … #define CN23XX_INTR_PKTVF_ERR … #define CN23XX_INTR_PKTPF_ERR … #define CN23XX_INTR_PPVF_ERR … #define CN23XX_INTR_PPPF_ERR … #define CN23XX_INTR_DMA0_DATA … #define CN23XX_INTR_DMA1_DATA … #define CN23XX_INTR_DMA_DATA … /* By fault only TIME based */ #define CN23XX_INTR_PKT_DATA … /* For both COUNT and TIME based */ /* #define CN23XX_INTR_PKT_DATA \ * (CN23XX_INTR_PKT_COUNT | CN23XX_INTR_PKT_TIME) */ /* Sum of interrupts for all PCI-Express Data Interrupts */ #define CN23XX_INTR_PCIE_DATA … /* Sum of interrupts for error events */ #define CN23XX_INTR_ERR … /* Programmed Mask for Interrupt Sum */ #define CN23XX_INTR_MASK … /* 4 Registers (64 - bit) */ #define CN23XX_SLI_S2M_PORT_CTL_START … #define CN23XX_SLI_S2M_PORTX_CTL(port) … #define CN23XX_SLI_MAC_NUMBER … /** PEM(0..3)_BAR1_INDEX(0..15)address is defined as * addr = (0x00011800C0000100 |port <<24 |idx <<3 ) * Here, port is PEM(0..3) & idx is INDEX(0..15) */ #define CN23XX_PEM_BAR1_INDEX_START … #define CN23XX_PEM_OFFSET … #define CN23XX_BAR1_INDEX_OFFSET … #define CN23XX_PEM_BAR1_INDEX_REG(port, idx) … /*############################ DPI #########################*/ /* 1 register (64-bit) - provides DMA Enable */ #define CN23XX_DPI_CTL … /* 1 register (64-bit) - Controls the DMA IO Operation */ #define CN23XX_DPI_DMA_CONTROL … /* 1 register (64-bit) - Provides DMA Instr'n Queue Enable */ #define CN23XX_DPI_REQ_GBL_ENB … /* 1 register (64-bit) - DPI_REQ_ERR_RSP * Indicates which Instr'n Queue received error response from the IO sub-system */ #define CN23XX_DPI_REQ_ERR_RSP … /* 1 register (64-bit) - DPI_REQ_ERR_RST * Indicates which Instr'n Queue dropped an Instr'n */ #define CN23XX_DPI_REQ_ERR_RST … /* 6 register (64-bit) - DPI_DMA_ENG(0..5)_EN * Provides DMA Engine Queue Enable */ #define CN23XX_DPI_DMA_ENG0_ENB … #define CN23XX_DPI_DMA_ENG_ENB(eng) … /* 8 register (64-bit) - DPI_DMA(0..7)_REQQ_CTL * Provides control bits for transaction on 8 Queues */ #define CN23XX_DPI_DMA_REQQ0_CTL … #define CN23XX_DPI_DMA_REQQ_CTL(q_no) … /* 6 register (64-bit) - DPI_ENG(0..5)_BUF * Provides DMA Engine FIFO (Queue) Size */ #define CN23XX_DPI_DMA_ENG0_BUF … #define CN23XX_DPI_DMA_ENG_BUF(eng) … /* 4 Registers (64-bit) */ #define CN23XX_DPI_SLI_PRT_CFG_START … #define CN23XX_DPI_SLI_PRTX_CFG(port) … /* Masks for DPI_DMA_CONTROL Register */ #define CN23XX_DPI_DMA_COMMIT_MODE … #define CN23XX_DPI_DMA_PKT_EN … #define CN23XX_DPI_DMA_ENB … /* Set the DMA Control, to update packet count not byte count sent by DMA, * when we use Interrupt Coalescing (CA mode) */ #define CN23XX_DPI_DMA_O_ADD1 … /*selecting 64-bit Byte Swap Mode */ #define CN23XX_DPI_DMA_O_ES … #define CN23XX_DPI_DMA_O_MODE … #define CN23XX_DPI_DMA_CTL_MASK … /*############################ RST #########################*/ #define CN23XX_RST_BOOT … #define CN23XX_RST_SOFT_RST … #define CN23XX_LMC0_RESET_CTL … #define CN23XX_LMC0_RESET_CTL_DDR3RST_MASK … #endif
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