/********************************************************************** * Author: Cavium, Inc. * * Contact: [email protected] * Please include "LiquidIO" in the subject. * * Copyright (c) 2003-2016 Cavium, Inc. * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as * published by the Free Software Foundation. * * This file is distributed in the hope that it will be useful, but * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or * NONINFRINGEMENT. See the GNU General Public License for more details. ***********************************************************************/ /*! \file cn23xx_vf_regs.h * \brief Host Driver: Register Address and Register Mask values for * Octeon CN23XX vf functions. */ #ifndef __CN23XX_VF_REGS_H__ #define __CN23XX_VF_REGS_H__ #define CN23XX_CONFIG_XPANSION_BAR … #define CN23XX_CONFIG_PCIE_CAP … #define CN23XX_CONFIG_PCIE_DEVCAP … #define CN23XX_CONFIG_PCIE_DEVCTL … #define CN23XX_CONFIG_PCIE_LINKCAP … #define CN23XX_CONFIG_PCIE_LINKCTL … #define CN23XX_CONFIG_PCIE_SLOTCAP … #define CN23XX_CONFIG_PCIE_SLOTCTL … #define CN23XX_CONFIG_PCIE_FLTMSK … /* The input jabber is used to determine the TSO max size. * Due to H/W limitation, this needs to be reduced to 60000 * in order to use H/W TSO and avoid the WQE malformation * PKO_BUG_24989_WQE_LEN */ #define CN23XX_DEFAULT_INPUT_JABBER … /* ############## BAR0 Registers ################ */ /* Each Input Queue register is at a 16-byte Offset in BAR0 */ #define CN23XX_VF_IQ_OFFSET … /*###################### REQUEST QUEUE #########################*/ /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */ #define CN23XX_VF_SLI_IQ_INSTR_COUNT_START64 … /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */ #define CN23XX_VF_SLI_IQ_BASE_ADDR_START64 … /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */ #define CN23XX_VF_SLI_IQ_DOORBELL_START … /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */ #define CN23XX_VF_SLI_IQ_SIZE_START … /* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data & * gather list fetches. SLI_PKT(0..63)_INPUT_CONTROL. */ #define CN23XX_VF_SLI_IQ_PKT_CONTROL_START64 … /*------- Request Queue Macros ---------*/ #define CN23XX_VF_SLI_IQ_PKT_CONTROL64(iq) … #define CN23XX_VF_SLI_IQ_BASE_ADDR64(iq) … #define CN23XX_VF_SLI_IQ_SIZE(iq) … #define CN23XX_VF_SLI_IQ_DOORBELL(iq) … #define CN23XX_VF_SLI_IQ_INSTR_COUNT64(iq) … /*------------------ Masks ----------------*/ #define CN23XX_PKT_INPUT_CTL_VF_NUM … #define CN23XX_PKT_INPUT_CTL_MAC_NUM … /* Number of instructions to be read in one MAC read request. * setting to Max value(4) */ #define CN23XX_PKT_INPUT_CTL_RDSIZE … #define CN23XX_PKT_INPUT_CTL_IS_64B … #define CN23XX_PKT_INPUT_CTL_RST … #define CN23XX_PKT_INPUT_CTL_QUIET … #define CN23XX_PKT_INPUT_CTL_RING_ENB … #define CN23XX_PKT_INPUT_CTL_DATA_NS … #define CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP … #define CN23XX_PKT_INPUT_CTL_DATA_RO … #define CN23XX_PKT_INPUT_CTL_USE_CSR … #define CN23XX_PKT_INPUT_CTL_GATHER_NS … #define CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP … #define CN23XX_PKT_INPUT_CTL_GATHER_RO … /** Rings per Virtual Function [RO] **/ #define CN23XX_PKT_INPUT_CTL_RPVF_MASK … #define CN23XX_PKT_INPUT_CTL_RPVF_POS … /* These bits[47:44][RO] give the Physical function number info within the MAC*/ #define CN23XX_PKT_INPUT_CTL_PF_NUM_MASK … #define CN23XX_PKT_INPUT_CTL_PF_NUM_POS … /** These bits[43:32][RO] give the virtual function number info within the PF*/ #define CN23XX_PKT_INPUT_CTL_VF_NUM_MASK … #define CN23XX_PKT_INPUT_CTL_VF_NUM_POS … #define CN23XX_PKT_INPUT_CTL_MAC_NUM_MASK … #define CN23XX_PKT_INPUT_CTL_MAC_NUM_POS … #define CN23XX_PKT_IN_DONE_WMARK_MASK … #define CN23XX_PKT_IN_DONE_WMARK_BIT_POS … #define CN23XX_PKT_IN_DONE_CNT_MASK … #ifdef __LITTLE_ENDIAN_BITFIELD #define CN23XX_PKT_INPUT_CTL_MASK … #else #define CN23XX_PKT_INPUT_CTL_MASK … #endif /** Masks for SLI_PKT_IN_DONE(0..63)_CNTS Register */ #define CN23XX_IN_DONE_CNTS_PI_INT … #define CN23XX_IN_DONE_CNTS_CINT_ENB … /*############################ OUTPUT QUEUE #########################*/ /* 64 registers for Output queue control - SLI_PKT(0..63)_OUTPUT_CONTROL */ #define CN23XX_VF_SLI_OQ_PKT_CONTROL_START … /* 64 registers for Output queue buffer and info size - SLI_PKT0_OUT_SIZE */ #define CN23XX_VF_SLI_OQ0_BUFF_INFO_SIZE … /* 64 registers for Output Queue Start Addr - SLI_PKT0_SLIST_BADDR */ #define CN23XX_VF_SLI_OQ_BASE_ADDR_START64 … /* 64 registers for Output Queue Packet Credits - SLI_PKT0_SLIST_BAOFF_DBELL */ #define CN23XX_VF_SLI_OQ_PKT_CREDITS_START … /* 64 registers for Output Queue size - SLI_PKT0_SLIST_FIFO_RSIZE */ #define CN23XX_VF_SLI_OQ_SIZE_START … /* 64 registers for Output Queue Packet Count - SLI_PKT0_CNTS */ #define CN23XX_VF_SLI_OQ_PKT_SENT_START … /* 64 registers for Output Queue INT Levels - SLI_PKT0_INT_LEVELS */ #define CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_START64 … /* Each Output Queue register is at a 16-byte Offset in BAR0 */ #define CN23XX_VF_OQ_OFFSET … /*------- Output Queue Macros ---------*/ #define CN23XX_VF_SLI_OQ_PKT_CONTROL(oq) … #define CN23XX_VF_SLI_OQ_BASE_ADDR64(oq) … #define CN23XX_VF_SLI_OQ_SIZE(oq) … #define CN23XX_VF_SLI_OQ_BUFF_INFO_SIZE(oq) … #define CN23XX_VF_SLI_OQ_PKTS_SENT(oq) … #define CN23XX_VF_SLI_OQ_PKTS_CREDIT(oq) … #define CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(oq) … /* Macro's for accessing CNT and TIME separately from INT_LEVELS */ #define CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_CNT(oq) … #define CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_TIME(oq) … /*------------------ Masks ----------------*/ #define CN23XX_PKT_OUTPUT_CTL_TENB … #define CN23XX_PKT_OUTPUT_CTL_CENB … #define CN23XX_PKT_OUTPUT_CTL_IPTR … #define CN23XX_PKT_OUTPUT_CTL_ES … #define CN23XX_PKT_OUTPUT_CTL_NSR … #define CN23XX_PKT_OUTPUT_CTL_ROR … #define CN23XX_PKT_OUTPUT_CTL_DPTR … #define CN23XX_PKT_OUTPUT_CTL_BMODE … #define CN23XX_PKT_OUTPUT_CTL_ES_P … #define CN23XX_PKT_OUTPUT_CTL_NSR_P … #define CN23XX_PKT_OUTPUT_CTL_ROR_P … #define CN23XX_PKT_OUTPUT_CTL_RING_ENB … /*######################### Mailbox Reg Macros ########################*/ #define CN23XX_VF_SLI_PKT_MBOX_INT_START … #define CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START … #define CN23XX_SLI_MBOX_OFFSET … #define CN23XX_SLI_MBOX_SIG_IDX_OFFSET … #define CN23XX_VF_SLI_PKT_MBOX_INT(q) … #define CN23XX_SLI_PKT_PF_VF_MBOX_SIG(q, idx) … /*######################## INTERRUPTS #########################*/ #define CN23XX_VF_SLI_INT_SUM_START … #define CN23XX_VF_SLI_INT_SUM(q) … /*------------------ Interrupt Masks ----------------*/ #define CN23XX_INTR_PO_INT … #define CN23XX_INTR_PI_INT … #define CN23XX_INTR_MBOX_INT … #define CN23XX_INTR_RESEND … #define CN23XX_INTR_CINT_ENB … #define CN23XX_INTR_MBOX_ENB … /*############################ MIO #########################*/ #define CN23XX_MIO_PTP_CLOCK_CFG … #define CN23XX_MIO_PTP_CLOCK_LO … #define CN23XX_MIO_PTP_CLOCK_HI … #define CN23XX_MIO_PTP_CLOCK_COMP … #define CN23XX_MIO_PTP_TIMESTAMP … #define CN23XX_MIO_PTP_EVT_CNT … #define CN23XX_MIO_PTP_CKOUT_THRESH_LO … #define CN23XX_MIO_PTP_CKOUT_THRESH_HI … #define CN23XX_MIO_PTP_CKOUT_HI_INCR … #define CN23XX_MIO_PTP_CKOUT_LO_INCR … #define CN23XX_MIO_PTP_PPS_THRESH_LO … #define CN23XX_MIO_PTP_PPS_THRESH_HI … #define CN23XX_MIO_PTP_PPS_HI_INCR … #define CN23XX_MIO_PTP_PPS_LO_INCR … /*############################ RST #########################*/ #define CN23XX_RST_BOOT … /*######################## MSIX TABLE #########################*/ #define CN23XX_MSIX_TABLE_ADDR_START … #define CN23XX_MSIX_TABLE_DATA_START … #define CN23XX_MSIX_TABLE_SIZE … #define CN23XX_MSIX_TABLE_ENTRIES … #define CN23XX_MSIX_ENTRY_VECTOR_CTL … #define CN23XX_MSIX_TABLE_ADDR(idx) … #define CN23XX_MSIX_TABLE_DATA(idx) … #endif
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