linux/drivers/pwm/pwm-tegra.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * drivers/pwm/pwm-tegra.c
 *
 * Tegra pulse-width-modulation controller driver
 *
 * Copyright (c) 2010-2020, NVIDIA Corporation.
 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <[email protected]>
 *
 * Overview of Tegra Pulse Width Modulator Register:
 * 1. 13-bit: Frequency division (SCALE)
 * 2. 8-bit : Pulse division (DUTY)
 * 3. 1-bit : Enable bit
 *
 * The PWM clock frequency is divided by 256 before subdividing it based
 * on the programmable frequency division value to generate the required
 * frequency for PWM output. The maximum output frequency that can be
 * achieved is (max rate of source clock) / 256.
 * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
 * 408 MHz/256 = 1.6 MHz.
 * This 1.6 MHz frequency can further be divided using SCALE value in PWM.
 *
 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
 * To achieve 100% duty cycle, program Bit [24] of this register to
 * 1’b1. In which case the other bits [23:16] are set to don't care.
 *
 * Limitations:
 * -	When PWM is disabled, the output is driven to inactive.
 * -	It does not allow the current PWM period to complete and
 *	stops abruptly.
 *
 * -	If the register is reconfigured while PWM is running,
 *	it does not complete the currently running period.
 *
 * -	If the user input duty is beyond acceptible limits,
 *	-EINVAL is returned.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pm_opp.h>
#include <linux/pwm.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/reset.h>

#include <soc/tegra/common.h>

#define PWM_ENABLE …
#define PWM_DUTY_WIDTH …
#define PWM_DUTY_SHIFT …
#define PWM_SCALE_WIDTH …
#define PWM_SCALE_SHIFT …

struct tegra_pwm_soc { … };

struct tegra_pwm_chip { … };

static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
{ … }

static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset)
{ … }

static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value)
{ … }

static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			    int duty_ns, int period_ns)
{ … }

static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{ … }

static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{ … }

static int tegra_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   const struct pwm_state *state)
{ … }

static const struct pwm_ops tegra_pwm_ops = …;

static int tegra_pwm_probe(struct platform_device *pdev)
{ … }

static void tegra_pwm_remove(struct platform_device *pdev)
{ … }

static int __maybe_unused tegra_pwm_runtime_suspend(struct device *dev)
{ … }

static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev)
{ … }

static const struct tegra_pwm_soc tegra20_pwm_soc = …;

static const struct tegra_pwm_soc tegra186_pwm_soc = …;

static const struct tegra_pwm_soc tegra194_pwm_soc = …;

static const struct of_device_id tegra_pwm_of_match[] = …;
MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);

static const struct dev_pm_ops tegra_pwm_pm_ops = …;

static struct platform_driver tegra_pwm_driver = …;

module_platform_driver(…) …;

MODULE_LICENSE(…) …;
MODULE_AUTHOR(…) …;
MODULE_DESCRIPTION(…) …;
MODULE_ALIAS(…) …;