/* Copyright, 1988-1992, Russell Nelson, Crynwr Software This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, version 1. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #define PP_ChipID … /* offset 2h -> Model/Product Number */ /* offset 3h -> Chip Revision Number */ #define PP_ISAIOB … #define PP_CS8900_ISAINT … #define PP_CS8920_ISAINT … #define PP_CS8900_ISADMA … #define PP_CS8920_ISADMA … #define PP_ISASOF … #define PP_DmaFrameCnt … #define PP_DmaByteCnt … #define PP_CS8900_ISAMemB … #define PP_CS8920_ISAMemB … #define PP_ISABootBase … #define PP_ISABootMask … /* EEPROM data and command registers */ #define PP_EECMD … #define PP_EEData … #define PP_DebugReg … #define PP_RxCFG … #define PP_RxCTL … #define PP_TxCFG … #define PP_TxCMD … #define PP_BufCFG … #define PP_LineCTL … #define PP_SelfCTL … #define PP_BusCTL … #define PP_TestCTL … #define PP_AutoNegCTL … #define PP_ISQ … #define PP_RxEvent … #define PP_TxEvent … #define PP_BufEvent … #define PP_RxMiss … #define PP_TxCol … #define PP_LineST … #define PP_SelfST … #define PP_BusST … #define PP_TDR … #define PP_AutoNegST … #define PP_TxCommand … #define PP_TxLength … #define PP_LAF … #define PP_IA … #define PP_RxStatus … #define PP_RxLength … #define PP_RxFrame … #define PP_TxFrame … /* Primary I/O Base Address. If no I/O base is supplied by the user, then this */ /* can be used as the default I/O base to access the PacketPage Area. */ #define DEFAULTIOBASE … #define FIRST_IO … #define LAST_IO … #define ADD_MASK … #define ADD_SIG … /* On Macs, we only need use the ISA I/O stuff until we do MEMORY_ON */ #ifdef CONFIG_MAC #define LCSLOTBASE … #define MMIOBASE … #endif #define CHIP_EISA_ID_SIG … #define CHIP_EISA_ID_SIG_STR … #ifdef IBMEIPKT #define EISA_ID_SIG … #define PART_NO_SIG … #define MONGOOSE_BIT … #else #define EISA_ID_SIG … #define PART_NO_SIG … #define MONGOOSE_BIT … #endif #define PRODUCT_ID_ADD … /* Mask to find out the types of registers */ #define REG_TYPE_MASK … /* Eeprom Commands */ #define ERSE_WR_ENBL … #define ERSE_WR_DISABLE … /* Defines Control/Config register quintuplet numbers */ #define RX_BUF_CFG … #define RX_CONTROL … #define TX_CFG … #define TX_COMMAND … #define BUF_CFG … #define LINE_CONTROL … #define SELF_CONTROL … #define BUS_CONTROL … #define TEST_CONTROL … /* Defines Status/Count registers quintuplet numbers */ #define RX_EVENT … #define TX_EVENT … #define BUF_EVENT … #define RX_MISS_COUNT … #define TX_COL_COUNT … #define LINE_STATUS … #define SELF_STATUS … #define BUS_STATUS … #define TDR … /* PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write */ #define SKIP_1 … #define RX_STREAM_ENBL … #define RX_OK_ENBL … #define RX_DMA_ONLY … #define AUTO_RX_DMA … #define BUFFER_CRC … #define RX_CRC_ERROR_ENBL … #define RX_RUNT_ENBL … #define RX_EXTRA_DATA_ENBL … /* PP_RxCTL - Receive Control bit definition - Read/write */ #define RX_IA_HASH_ACCEPT … #define RX_PROM_ACCEPT … #define RX_OK_ACCEPT … #define RX_MULTCAST_ACCEPT … #define RX_IA_ACCEPT … #define RX_BROADCAST_ACCEPT … #define RX_BAD_CRC_ACCEPT … #define RX_RUNT_ACCEPT … #define RX_EXTRA_DATA_ACCEPT … #define RX_ALL_ACCEPT … /* Default receive mode - individually addressed, broadcast, and error free */ #define DEF_RX_ACCEPT … /* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */ #define TX_LOST_CRS_ENBL … #define TX_SQE_ERROR_ENBL … #define TX_OK_ENBL … #define TX_LATE_COL_ENBL … #define TX_JBR_ENBL … #define TX_ANY_COL_ENBL … #define TX_16_COL_ENBL … /* PP_TxCMD - Transmit Command bit definition - Read-only */ #define TX_START_4_BYTES … #define TX_START_64_BYTES … #define TX_START_128_BYTES … #define TX_START_ALL_BYTES … #define TX_FORCE … #define TX_ONE_COL … #define TX_TWO_PART_DEFF_DISABLE … #define TX_NO_CRC … #define TX_RUNT … /* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */ #define GENERATE_SW_INTERRUPT … #define RX_DMA_ENBL … #define READY_FOR_TX_ENBL … #define TX_UNDERRUN_ENBL … #define RX_MISS_ENBL … #define RX_128_BYTE_ENBL … #define TX_COL_COUNT_OVRFLOW_ENBL … #define RX_MISS_COUNT_OVRFLOW_ENBL … #define RX_DEST_MATCH_ENBL … /* PP_LineCTL - Line Control bit definition - Read/write */ #define SERIAL_RX_ON … #define SERIAL_TX_ON … #define AUI_ONLY … #define AUTO_AUI_10BASET … #define MODIFIED_BACKOFF … #define NO_AUTO_POLARITY … #define TWO_PART_DEFDIS … #define LOW_RX_SQUELCH … /* PP_SelfCTL - Software Self Control bit definition - Read/write */ #define POWER_ON_RESET … #define SW_STOP … #define SLEEP_ON … #define AUTO_WAKEUP … #define HCB0_ENBL … #define HCB1_ENBL … #define HCB0 … #define HCB1 … /* PP_BusCTL - ISA Bus Control bit definition - Read/write */ #define RESET_RX_DMA … #define MEMORY_ON … #define DMA_BURST_MODE … #define IO_CHANNEL_READY_ON … #define RX_DMA_SIZE_64K … #define ENABLE_IRQ … /* PP_TestCTL - Test Control bit definition - Read/write */ #define LINK_OFF … #define ENDEC_LOOPBACK … #define AUI_LOOPBACK … #define BACKOFF_OFF … #define FDX_8900 … #define FAST_TEST … /* PP_RxEvent - Receive Event Bit definition - Read-only */ #define RX_IA_HASHED … #define RX_DRIBBLE … #define RX_OK … #define RX_HASHED … #define RX_IA … #define RX_BROADCAST … #define RX_CRC_ERROR … #define RX_RUNT … #define RX_EXTRA_DATA … #define HASH_INDEX_MASK … /* PP_TxEvent - Transmit Event Bit definition - Read-only */ #define TX_LOST_CRS … #define TX_SQE_ERROR … #define TX_OK … #define TX_LATE_COL … #define TX_JBR … #define TX_16_COL … #define TX_SEND_OK_BITS … #define TX_COL_COUNT_MASK … /* PP_BufEvent - Buffer Event Bit definition - Read-only */ #define SW_INTERRUPT … #define RX_DMA … #define READY_FOR_TX … #define TX_UNDERRUN … #define RX_MISS … #define RX_128_BYTE … #define TX_COL_OVRFLW … #define RX_MISS_OVRFLW … #define RX_DEST_MATCH … /* PP_LineST - Ethernet Line Status bit definition - Read-only */ #define LINK_OK … #define AUI_ON … #define TENBASET_ON … #define POLARITY_OK … #define CRS_OK … /* PP_SelfST - Chip Software Status bit definition */ #define ACTIVE_33V … #define INIT_DONE … #define SI_BUSY … #define EEPROM_PRESENT … #define EEPROM_OK … #define EL_PRESENT … #define EE_SIZE_64 … /* PP_BusST - ISA Bus Status bit definition */ #define TX_BID_ERROR … #define READY_FOR_TX_NOW … /* PP_AutoNegCTL - Auto Negotiation Control bit definition */ #define RE_NEG_NOW … #define ALLOW_FDX … #define AUTO_NEG_ENABLE … #define NLP_ENABLE … #define FORCE_FDX … #define AUTO_NEG_BITS … #define AUTO_NEG_MASK … /* PP_AutoNegST - Auto Negotiation Status bit definition */ #define AUTO_NEG_BUSY … #define FLP_LINK … #define FLP_LINK_GOOD … #define LINK_FAULT … #define HDX_ACTIVE … #define FDX_ACTIVE … /* The following block defines the ISQ event types */ #define ISQ_RECEIVER_EVENT … #define ISQ_TRANSMITTER_EVENT … #define ISQ_BUFFER_EVENT … #define ISQ_RX_MISS_EVENT … #define ISQ_TX_COL_EVENT … #define ISQ_EVENT_MASK … #define ISQ_HIST … #define AUTOINCREMENT … #define TXRXBUFSIZE … #define RXDMABUFSIZE … #define RXDMASIZE … #define TXRX_LENGTH_MASK … /* rx options bits */ #define RCV_WITH_RXON … #define RCV_COUNTS … #define RCV_PONG … #define RCV_DONG … #define RCV_POLLING … #define RCV_ISQ … #define RCV_AUTO_DMA … #define RCV_DMA … #define RCV_DMA_ALL … #define RCV_FIXED_DATA … #define RCV_IO … #define RCV_MEMORY … #define RAM_SIZE … #define PKT_START … #define RX_FRAME_PORT … #define TX_FRAME_PORT … #define TX_CMD_PORT … #define TX_NOW … #define TX_AFTER_381 … #define TX_AFTER_ALL … #define TX_LEN_PORT … #define ISQ_PORT … #define ADD_PORT … #define DATA_PORT … #define EEPROM_WRITE_EN … #define EEPROM_WRITE_DIS … #define EEPROM_WRITE_CMD … #define EEPROM_READ_CMD … /* Receive Header */ /* Description of header of each packet in receive area of memory */ #define RBUF_EVENT_LOW … #define RBUF_EVENT_HIGH … #define RBUF_LEN_LOW … #define RBUF_LEN_HI … #define RBUF_HEAD_LEN … #define CHIP_READ … #define DMA_READ … /* for bios scan */ /* */ #ifdef CSDEBUG /* use these values for debugging bios scan */ #define BIOS_START_SEG … #define BIOS_OFFSET_INC … #else #define BIOS_START_SEG … #define BIOS_OFFSET_INC … #endif #define BIOS_LAST_OFFSET … /* Byte offsets into the EEPROM configuration buffer */ #define ISA_CNF_OFFSET … #define TX_CTL_OFFSET … #define AUTO_NEG_CNF_OFFSET … /* the assumption here is that the bits in the eeprom are generally */ /* in the same position as those in the autonegctl register. */ /* Of course the IMM bit is not in that register so it must be */ /* masked out */ #define EE_FORCE_FDX … #define EE_NLP_ENABLE … #define EE_AUTO_NEG_ENABLE … #define EE_ALLOW_FDX … #define EE_AUTO_NEG_CNF_MASK … #define IMM_BIT … #define ADAPTER_CNF_OFFSET … #define A_CNF_10B_T … #define A_CNF_AUI … #define A_CNF_10B_2 … #define A_CNF_MEDIA_TYPE … #define A_CNF_MEDIA_AUTO … #define A_CNF_MEDIA_10B_T … #define A_CNF_MEDIA_AUI … #define A_CNF_MEDIA_10B_2 … #define A_CNF_DC_DC_POLARITY … #define A_CNF_NO_AUTO_POLARITY … #define A_CNF_LOW_RX_SQUELCH … #define A_CNF_EXTND_10B_2 … #define PACKET_PAGE_OFFSET … /* Bit definitions for the ISA configuration word from the EEPROM */ #define INT_NO_MASK … #define DMA_NO_MASK … #define ISA_DMA_SIZE … #define ISA_AUTO_RxDMA … #define ISA_RxDMA … #define DMA_BURST … #define STREAM_TRANSFER … #define ANY_ISA_DMA … /* DMA controller registers */ #define DMA_BASE … #define DMA_BASE_2 … #define DMA_STAT … #define DMA_MASK … #define DMA_MODE … #define DMA_RESETFF … /* DMA data */ #define DMA_DISABLE … #define DMA_ENABLE … /* Demand transfers, incr. address, auto init, writes, ch. n */ #define DMA_RX_MODE … /* Demand transfers, incr. address, auto init, reads, ch. n */ #define DMA_TX_MODE … #define DMA_SIZE … #define CS8900 … #define CS8920 … #define CS8920M … #define REVISON_BITS … #define EEVER_NUMBER … #define CHKSUM_LEN … #define CHKSUM_VAL … #define START_EEPROM_DATA … #define IRQ_MAP_EEPROM_DATA … #define IRQ_MAP_LEN … #define PNP_IRQ_FRMT … #define CS8900_IRQ_MAP … #define CS8920_NO_INTS … #define PNP_ADD_PORT … #define PNP_WRITE_PORT … #define GET_PNP_ISA_STRUCT … #define PNP_ISA_STRUCT_LEN … #define PNP_CSN_CNT_OFF … #define PNP_RD_PORT_OFF … #define PNP_FUNCTION_OK … #define PNP_WAKE … #define PNP_RSRC_DATA … #define PNP_RSRC_READY … #define PNP_STATUS … #define PNP_ACTIVATE … #define PNP_CNF_IO_H … #define PNP_CNF_IO_L … #define PNP_CNF_INT … #define PNP_CNF_DMA … #define PNP_CNF_MEM …
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