/* SPDX-License-Identifier: GPL-2.0 */ /* Register definitions for Gemini GMAC Ethernet device driver * * Copyright (C) 2006 Storlink, Corp. * Copyright (C) 2008-2009 Paulius Zaleckas <[email protected]> * Copyright (C) 2010 Michał Mirosław <[email protected]> * Copytight (C) 2017 Linus Walleij <[email protected]> */ #ifndef _GEMINI_ETHERNET_H #define _GEMINI_ETHERNET_H #include <linux/bitops.h> /* Base Registers */ #define TOE_NONTOE_QUE_HDR_BASE … #define TOE_TOE_QUE_HDR_BASE … /* Queue ID */ #define TOE_SW_FREE_QID … #define TOE_HW_FREE_QID … #define TOE_GMAC0_SW_TXQ0_QID … #define TOE_GMAC0_SW_TXQ1_QID … #define TOE_GMAC0_SW_TXQ2_QID … #define TOE_GMAC0_SW_TXQ3_QID … #define TOE_GMAC0_SW_TXQ4_QID … #define TOE_GMAC0_SW_TXQ5_QID … #define TOE_GMAC0_HW_TXQ0_QID … #define TOE_GMAC0_HW_TXQ1_QID … #define TOE_GMAC0_HW_TXQ2_QID … #define TOE_GMAC0_HW_TXQ3_QID … #define TOE_GMAC1_SW_TXQ0_QID … #define TOE_GMAC1_SW_TXQ1_QID … #define TOE_GMAC1_SW_TXQ2_QID … #define TOE_GMAC1_SW_TXQ3_QID … #define TOE_GMAC1_SW_TXQ4_QID … #define TOE_GMAC1_SW_TXQ5_QID … #define TOE_GMAC1_HW_TXQ0_QID … #define TOE_GMAC1_HW_TXQ1_QID … #define TOE_GMAC1_HW_TXQ2_QID … #define TOE_GMAC1_HW_TXQ3_QID … #define TOE_GMAC0_DEFAULT_QID … #define TOE_GMAC1_DEFAULT_QID … #define TOE_CLASSIFICATION_QID(x) … #define TOE_TOE_QID(x) … /* TOE DMA Queue Size should be 2^n, n = 6...12 * TOE DMA Queues are the following queue types: * SW Free Queue, HW Free Queue, * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5 * The base address and descriptor number are configured at * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004) */ #define GET_WPTR(addr) … #define GET_RPTR(addr) … #define SET_WPTR(addr, data) … #define SET_RPTR(addr, data) … #define __RWPTR_NEXT(x, mask) … #define __RWPTR_PREV(x, mask) … #define __RWPTR_DISTANCE(r, w, mask) … #define __RWPTR_MASK(order) … #define RWPTR_NEXT(x, order) … #define RWPTR_PREV(x, order) … #define RWPTR_DISTANCE(r, w, order) … /* Global registers */ #define GLOBAL_TOE_VERSION_REG … #define GLOBAL_SW_FREEQ_BASE_SIZE_REG … #define GLOBAL_HW_FREEQ_BASE_SIZE_REG … #define GLOBAL_DMA_SKB_SIZE_REG … #define GLOBAL_SWFQ_RWPTR_REG … #define GLOBAL_HWFQ_RWPTR_REG … #define GLOBAL_INTERRUPT_STATUS_0_REG … #define GLOBAL_INTERRUPT_ENABLE_0_REG … #define GLOBAL_INTERRUPT_SELECT_0_REG … #define GLOBAL_INTERRUPT_STATUS_1_REG … #define GLOBAL_INTERRUPT_ENABLE_1_REG … #define GLOBAL_INTERRUPT_SELECT_1_REG … #define GLOBAL_INTERRUPT_STATUS_2_REG … #define GLOBAL_INTERRUPT_ENABLE_2_REG … #define GLOBAL_INTERRUPT_SELECT_2_REG … #define GLOBAL_INTERRUPT_STATUS_3_REG … #define GLOBAL_INTERRUPT_ENABLE_3_REG … #define GLOBAL_INTERRUPT_SELECT_3_REG … #define GLOBAL_INTERRUPT_STATUS_4_REG … #define GLOBAL_INTERRUPT_ENABLE_4_REG … #define GLOBAL_INTERRUPT_SELECT_4_REG … #define GLOBAL_HASH_TABLE_BASE_REG … #define GLOBAL_QUEUE_THRESHOLD_REG … /* GMAC 0/1 DMA/TOE register */ #define GMAC_DMA_CTRL_REG … #define GMAC_TX_WEIGHTING_CTRL_0_REG … #define GMAC_TX_WEIGHTING_CTRL_1_REG … #define GMAC_SW_TX_QUEUE0_PTR_REG … #define GMAC_SW_TX_QUEUE1_PTR_REG … #define GMAC_SW_TX_QUEUE2_PTR_REG … #define GMAC_SW_TX_QUEUE3_PTR_REG … #define GMAC_SW_TX_QUEUE4_PTR_REG … #define GMAC_SW_TX_QUEUE5_PTR_REG … #define GMAC_SW_TX_QUEUE_PTR_REG(i) … #define GMAC_HW_TX_QUEUE0_PTR_REG … #define GMAC_HW_TX_QUEUE1_PTR_REG … #define GMAC_HW_TX_QUEUE2_PTR_REG … #define GMAC_HW_TX_QUEUE3_PTR_REG … #define GMAC_HW_TX_QUEUE_PTR_REG(i) … #define GMAC_DMA_TX_FIRST_DESC_REG … #define GMAC_DMA_TX_CURR_DESC_REG … #define GMAC_DMA_TX_DESC_WORD0_REG … #define GMAC_DMA_TX_DESC_WORD1_REG … #define GMAC_DMA_TX_DESC_WORD2_REG … #define GMAC_DMA_TX_DESC_WORD3_REG … #define GMAC_SW_TX_QUEUE_BASE_REG … #define GMAC_HW_TX_QUEUE_BASE_REG … #define GMAC_DMA_RX_FIRST_DESC_REG … #define GMAC_DMA_RX_CURR_DESC_REG … #define GMAC_DMA_RX_DESC_WORD0_REG … #define GMAC_DMA_RX_DESC_WORD1_REG … #define GMAC_DMA_RX_DESC_WORD2_REG … #define GMAC_DMA_RX_DESC_WORD3_REG … #define GMAC_HASH_ENGINE_REG0 … #define GMAC_HASH_ENGINE_REG1 … /* matching rule 0 Control register 0 */ #define GMAC_MR0CR0 … #define GMAC_MR0CR1 … #define GMAC_MR0CR2 … #define GMAC_MR1CR0 … #define GMAC_MR1CR1 … #define GMAC_MR1CR2 … #define GMAC_MR2CR0 … #define GMAC_MR2CR1 … #define GMAC_MR2CR2 … #define GMAC_MR3CR0 … #define GMAC_MR3CR1 … #define GMAC_MR3CR2 … /* Support Protocol Register 0 */ #define GMAC_SPR0 … #define GMAC_SPR1 … #define GMAC_SPR2 … #define GMAC_SPR3 … #define GMAC_SPR4 … #define GMAC_SPR5 … #define GMAC_SPR6 … #define GMAC_SPR7 … /* GMAC Hash/Rx/Tx AHB Weighting register */ #define GMAC_AHB_WEIGHT_REG … /* TOE GMAC 0/1 register */ #define GMAC_STA_ADD0 … #define GMAC_STA_ADD1 … #define GMAC_STA_ADD2 … #define GMAC_RX_FLTR … #define GMAC_MCAST_FIL0 … #define GMAC_MCAST_FIL1 … #define GMAC_CONFIG0 … #define GMAC_CONFIG1 … #define GMAC_CONFIG2 … #define GMAC_CONFIG3 … #define GMAC_RESERVED … #define GMAC_STATUS … #define GMAC_IN_DISCARDS … #define GMAC_IN_ERRORS … #define GMAC_IN_MCAST … #define GMAC_IN_BCAST … #define GMAC_IN_MAC1 … #define GMAC_IN_MAC2 … #define RX_STATS_NUM … /* DMA Queues description Ring Base Address/Size Register (offset 0x0004) */ dma_q_base_size; #define DMA_Q_BASE_MASK … /* DMA SKB Buffer register (offset 0x0008) */ dma_skb_size; /* DMA SW Free Queue Read/Write Pointer Register (offset 0x000c) */ dma_rwptr; /* Interrupt Status Register 0 (offset 0x0020) * Interrupt Mask Register 0 (offset 0x0024) * Interrupt Select Register 0 (offset 0x0028) */ #define GMAC1_TXDERR_INT_BIT … #define GMAC1_TXPERR_INT_BIT … #define GMAC0_TXDERR_INT_BIT … #define GMAC0_TXPERR_INT_BIT … #define GMAC1_RXDERR_INT_BIT … #define GMAC1_RXPERR_INT_BIT … #define GMAC0_RXDERR_INT_BIT … #define GMAC0_RXPERR_INT_BIT … #define GMAC1_SWTQ15_FIN_INT_BIT … #define GMAC1_SWTQ14_FIN_INT_BIT … #define GMAC1_SWTQ13_FIN_INT_BIT … #define GMAC1_SWTQ12_FIN_INT_BIT … #define GMAC1_SWTQ11_FIN_INT_BIT … #define GMAC1_SWTQ10_FIN_INT_BIT … #define GMAC0_SWTQ05_FIN_INT_BIT … #define GMAC0_SWTQ04_FIN_INT_BIT … #define GMAC0_SWTQ03_FIN_INT_BIT … #define GMAC0_SWTQ02_FIN_INT_BIT … #define GMAC0_SWTQ01_FIN_INT_BIT … #define GMAC0_SWTQ00_FIN_INT_BIT … #define GMAC1_SWTQ15_EOF_INT_BIT … #define GMAC1_SWTQ14_EOF_INT_BIT … #define GMAC1_SWTQ13_EOF_INT_BIT … #define GMAC1_SWTQ12_EOF_INT_BIT … #define GMAC1_SWTQ11_EOF_INT_BIT … #define GMAC1_SWTQ10_EOF_INT_BIT … #define GMAC0_SWTQ05_EOF_INT_BIT … #define GMAC0_SWTQ04_EOF_INT_BIT … #define GMAC0_SWTQ03_EOF_INT_BIT … #define GMAC0_SWTQ02_EOF_INT_BIT … #define GMAC0_SWTQ01_EOF_INT_BIT … #define GMAC0_SWTQ00_EOF_INT_BIT … /* Interrupt Status Register 1 (offset 0x0030) * Interrupt Mask Register 1 (offset 0x0034) * Interrupt Select Register 1 (offset 0x0038) */ #define TOE_IQ3_FULL_INT_BIT … #define TOE_IQ2_FULL_INT_BIT … #define TOE_IQ1_FULL_INT_BIT … #define TOE_IQ0_FULL_INT_BIT … #define TOE_IQ3_INT_BIT … #define TOE_IQ2_INT_BIT … #define TOE_IQ1_INT_BIT … #define TOE_IQ0_INT_BIT … #define GMAC1_HWTQ13_EOF_INT_BIT … #define GMAC1_HWTQ12_EOF_INT_BIT … #define GMAC1_HWTQ11_EOF_INT_BIT … #define GMAC1_HWTQ10_EOF_INT_BIT … #define GMAC0_HWTQ03_EOF_INT_BIT … #define GMAC0_HWTQ02_EOF_INT_BIT … #define GMAC0_HWTQ01_EOF_INT_BIT … #define GMAC0_HWTQ00_EOF_INT_BIT … #define CLASS_RX_INT_BIT(x) … #define DEFAULT_Q1_INT_BIT … #define DEFAULT_Q0_INT_BIT … #define TOE_IQ_INT_BITS … #define TOE_IQ_FULL_BITS … #define TOE_IQ_ALL_BITS … #define TOE_CLASS_RX_INT_BITS … /* Interrupt Status Register 2 (offset 0x0040) * Interrupt Mask Register 2 (offset 0x0044) * Interrupt Select Register 2 (offset 0x0048) */ #define TOE_QL_FULL_INT_BIT(x) … /* Interrupt Status Register 3 (offset 0x0050) * Interrupt Mask Register 3 (offset 0x0054) * Interrupt Select Register 3 (offset 0x0058) */ #define TOE_QH_FULL_INT_BIT(x) … /* Interrupt Status Register 4 (offset 0x0060) * Interrupt Mask Register 4 (offset 0x0064) * Interrupt Select Register 4 (offset 0x0068) */ #define GMAC1_RESERVED_INT_BIT … #define GMAC1_MIB_INT_BIT … #define GMAC1_RX_PAUSE_ON_INT_BIT … #define GMAC1_TX_PAUSE_ON_INT_BIT … #define GMAC1_RX_PAUSE_OFF_INT_BIT … #define GMAC1_TX_PAUSE_OFF_INT_BIT … #define GMAC1_RX_OVERRUN_INT_BIT … #define GMAC1_STATUS_CHANGE_INT_BIT … #define GMAC0_RESERVED_INT_BIT … #define GMAC0_MIB_INT_BIT … #define GMAC0_RX_PAUSE_ON_INT_BIT … #define GMAC0_TX_PAUSE_ON_INT_BIT … #define GMAC0_RX_PAUSE_OFF_INT_BIT … #define GMAC0_TX_PAUSE_OFF_INT_BIT … #define GMAC0_RX_OVERRUN_INT_BIT … #define GMAC0_STATUS_CHANGE_INT_BIT … #define CLASS_RX_FULL_INT_BIT(x) … #define HWFQ_EMPTY_INT_BIT … #define SWFQ_EMPTY_INT_BIT … #define GMAC0_INT_BITS … #define GMAC1_INT_BITS … #define CLASS_RX_FULL_INT_BITS … /* GLOBAL_QUEUE_THRESHOLD_REG (offset 0x0070) */ queue_threshold; /* GMAC DMA Control Register * GMAC0 offset 0x8000 * GMAC1 offset 0xC000 */ gmac_dma_ctrl; /* GMAC Tx Weighting Control Register 0 * GMAC0 offset 0x8004 * GMAC1 offset 0xC004 */ gmac_tx_wcr0; /* GMAC Tx Weighting Control Register 1 * GMAC0 offset 0x8008 * GMAC1 offset 0xC008 */ gmac_tx_wcr1; /* GMAC DMA Tx Description Word 0 Register * GMAC0 offset 0x8040 * GMAC1 offset 0xC040 */ gmac_txdesc_0; /* GMAC DMA Tx Description Word 1 Register * GMAC0 offset 0x8044 * GMAC1 offset 0xC044 */ gmac_txdesc_1; #define TSS_IP_FIXED_LEN_BIT … #define TSS_BYPASS_BIT … #define TSS_UDP_CHKSUM_BIT … #define TSS_TCP_CHKSUM_BIT … #define TSS_IPV6_ENABLE_BIT … #define TSS_IP_CHKSUM_BIT … #define TSS_MTU_ENABLE_BIT … #define TSS_CHECKUM_ENABLE … /* GMAC DMA Tx Description Word 2 Register * GMAC0 offset 0x8048 * GMAC1 offset 0xC048 */ gmac_txdesc_2; /* GMAC DMA Tx Description Word 3 Register * GMAC0 offset 0x804C * GMAC1 offset 0xC04C */ gmac_txdesc_3; #define SOF_EOF_BIT_MASK … #define SOF_BIT … #define EOF_BIT … #define EOFIE_BIT … #define MTU_SIZE_BIT_MASK … /* GMAC Tx Descriptor */ struct gmac_txdesc { … }; /* GMAC DMA Rx Description Word 0 Register * GMAC0 offset 0x8060 * GMAC1 offset 0xC060 */ gmac_rxdesc_0; #define GMAC_RXDESC_0_T_derr … #define GMAC_RXDESC_0_T_perr … #define GMAC_RXDESC_0_T_chksum_status(x) … #define GMAC_RXDESC_0_T_status(x) … #define GMAC_RXDESC_0_T_desc_count(x) … #define RX_CHKSUM_IP_UDP_TCP_OK … #define RX_CHKSUM_IP_OK_ONLY … #define RX_CHKSUM_NONE … #define RX_CHKSUM_IP_ERR_UNKNOWN … #define RX_CHKSUM_IP_ERR … #define RX_CHKSUM_TCP_UDP_ERR … #define RX_CHKSUM_NUM … #define RX_STATUS_GOOD_FRAME … #define RX_STATUS_TOO_LONG_GOOD_CRC … #define RX_STATUS_RUNT_FRAME … #define RX_STATUS_SFD_NOT_FOUND … #define RX_STATUS_CRC_ERROR … #define RX_STATUS_TOO_LONG_BAD_CRC … #define RX_STATUS_ALIGNMENT_ERROR … #define RX_STATUS_TOO_LONG_BAD_ALIGN … #define RX_STATUS_RX_ERR … #define RX_STATUS_DA_FILTERED … #define RX_STATUS_BUFFER_FULL … #define RX_STATUS_NUM … #define RX_ERROR_LENGTH(s) … #define RX_ERROR_OVER(s) … #define RX_ERROR_CRC(s) … #define RX_ERROR_FRAME(s) … #define RX_ERROR_FIFO(s) … /* GMAC DMA Rx Description Word 1 Register * GMAC0 offset 0x8064 * GMAC1 offset 0xC064 */ gmac_rxdesc_1; /* GMAC DMA Rx Description Word 2 Register * GMAC0 offset 0x8068 * GMAC1 offset 0xC068 */ gmac_rxdesc_2; #define RX_INSERT_NONE … #define RX_INSERT_1_BYTE … #define RX_INSERT_2_BYTE … #define RX_INSERT_3_BYTE … /* GMAC DMA Rx Description Word 3 Register * GMAC0 offset 0x806C * GMAC1 offset 0xC06C */ gmac_rxdesc_3; /* GMAC Rx Descriptor, this is simply fitted over the queue registers */ struct gmac_rxdesc { … }; /* GMAC Matching Rule Control Register 0 * GMAC0 offset 0x8078 * GMAC1 offset 0xC078 */ #define MR_L2_BIT … #define MR_L3_BIT … #define MR_L4_BIT … #define MR_L7_BIT … #define MR_PORT_BIT … #define MR_PRIORITY_BIT … #define MR_DA_BIT … #define MR_SA_BIT … #define MR_ETHER_TYPE_BIT … #define MR_VLAN_BIT … #define MR_PPPOE_BIT … #define MR_IP_VER_BIT … #define MR_IP_HDR_LEN_BIT … #define MR_FLOW_LABLE_BIT … #define MR_TOS_TRAFFIC_BIT … #define MR_SPR_BIT(x) … #define MR_SPR_BITS … /* GMAC_AHB_WEIGHT registers * GMAC0 offset 0x80C8 * GMAC1 offset 0xC0C8 */ gmac_ahb_weight; /* GMAC RX FLTR * GMAC0 Offset 0xA00C * GMAC1 Offset 0xE00C */ gmac_rx_fltr; /* GMAC Configuration 0 * GMAC0 Offset 0xA018 * GMAC1 Offset 0xE018 */ gmac_config0; #define CONFIG0_TX_RX_DISABLE … #define CONFIG0_RX_CHKSUM … #define CONFIG0_FLOW_RX … #define CONFIG0_FLOW_TX … #define CONFIG0_FLOW_TX_RX … #define CONFIG0_FLOW_CTL … #define CONFIG0_MAXLEN_SHIFT … #define CONFIG0_MAXLEN_MASK … #define CONFIG0_MAXLEN_1536 … #define CONFIG0_MAXLEN_1518 … #define CONFIG0_MAXLEN_1522 … #define CONFIG0_MAXLEN_1548 … #define CONFIG0_MAXLEN_9k … #define CONFIG0_MAXLEN_10k … #define CONFIG0_MAXLEN_1518__6 … #define CONFIG0_MAXLEN_1518__7 … /* GMAC Configuration 1 * GMAC0 Offset 0xA01C * GMAC1 Offset 0xE01C */ gmac_config1; #define GMAC_FLOWCTRL_SET_MAX … #define GMAC_FLOWCTRL_SET_MIN … #define GMAC_FLOWCTRL_RELEASE_MAX … #define GMAC_FLOWCTRL_RELEASE_MIN … /* GMAC Configuration 2 * GMAC0 Offset 0xA020 * GMAC1 Offset 0xE020 */ gmac_config2; /* GMAC Configuration 3 * GMAC0 Offset 0xA024 * GMAC1 Offset 0xE024 */ gmac_config3; /* GMAC STATUS * GMAC0 Offset 0xA02C * GMAC1 Offset 0xE02C */ gmac_status; #define GMAC_SPEED_10 … #define GMAC_SPEED_100 … #define GMAC_SPEED_1000 … #define GMAC_PHY_MII … #define GMAC_PHY_GMII … #define GMAC_PHY_RGMII_100_10 … #define GMAC_PHY_RGMII_1000 … /* Queue Header * (1) TOE Queue Header * (2) Non-TOE Queue Header * (3) Interrupt Queue Header * * memory Layout * TOE Queue Header * 0x60003000 +---------------------------+ 0x0000 * | TOE Queue 0 Header | * | 8 * 4 Bytes | * +---------------------------+ 0x0020 * | TOE Queue 1 Header | * | 8 * 4 Bytes | * +---------------------------+ 0x0040 * | ...... | * | | * +---------------------------+ * * Non TOE Queue Header * 0x60002000 +---------------------------+ 0x0000 * | Default Queue 0 Header | * | 2 * 4 Bytes | * +---------------------------+ 0x0008 * | Default Queue 1 Header | * | 2 * 4 Bytes | * +---------------------------+ 0x0010 * | Classification Queue 0 | * | 2 * 4 Bytes | * +---------------------------+ * | Classification Queue 1 | * | 2 * 4 Bytes | * +---------------------------+ (n * 8 + 0x10) * | ... | * | 2 * 4 Bytes | * +---------------------------+ (13 * 8 + 0x10) * | Classification Queue 13 | * | 2 * 4 Bytes | * +---------------------------+ 0x80 * | Interrupt Queue 0 | * | 2 * 4 Bytes | * +---------------------------+ * | Interrupt Queue 1 | * | 2 * 4 Bytes | * +---------------------------+ * | Interrupt Queue 2 | * | 2 * 4 Bytes | * +---------------------------+ * | Interrupt Queue 3 | * | 2 * 4 Bytes | * +---------------------------+ * */ #define TOE_QUEUE_HDR_ADDR(n) … #define TOE_Q_HDR_AREA_END … #define TOE_DEFAULT_Q_HDR_BASE(x) … #define TOE_CLASS_Q_HDR_BASE … #define TOE_INTR_Q_HDR_BASE … #define INTERRUPT_QUEUE_HDR_ADDR(n) … #define NONTOE_Q_HDR_AREA_END … /* NONTOE Queue Header Word 0 */ nontoe_qhdr0; #define NONTOE_QHDR0_BASE_MASK … /* NONTOE Queue Header Word 1 */ nontoe_qhdr1; /* Non-TOE Queue Header */ struct nontoe_qhdr { … }; #endif /* _GEMINI_ETHERNET_H */
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