/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2005-2016 Broadcom. * All rights reserved. * * Contact Information: * [email protected] * * Emulex * 3333 Susan Street * Costa Mesa, CA 92626 */ /********* Mailbox door bell *************/ /* Used for driver communication with the FW. * The software must write this register twice to post any command. First, * it writes the register with hi=1 and the upper bits of the physical address * for the MAILBOX structure. Software must poll the ready bit until this * is acknowledged. Then, sotware writes the register with hi=0 with the lower * bits in the address. It must poll the ready bit until the command is * complete. Upon completion, the MAILBOX will contain a valid completion * queue entry. */ #define MPU_MAILBOX_DB_OFFSET … #define MPU_MAILBOX_DB_RDY_MASK … #define MPU_MAILBOX_DB_HI_MASK … #define MPU_EP_CONTROL … /********** MPU semphore: used for SH & BE *************/ #define SLIPORT_SOFTRESET_OFFSET … #define SLIPORT_SEMAPHORE_OFFSET_BEx … #define SLIPORT_SEMAPHORE_OFFSET_SH … #define POST_STAGE_MASK … #define POST_ERR_MASK … #define POST_ERR_SHIFT … #define POST_ERR_RECOVERY_CODE_MASK … /* Soft Reset register masks */ #define SLIPORT_SOFTRESET_SR_MASK … /* MPU semphore POST stage values */ #define POST_STAGE_AWAITING_HOST_RDY … #define POST_STAGE_HOST_RDY … #define POST_STAGE_BE_RESET … #define POST_STAGE_ARMFW_RDY … #define POST_STAGE_RECOVERABLE_ERR … /* FW has detected a UE and is dumping FAT log data */ #define POST_STAGE_FAT_LOG_START … #define POST_STAGE_ARMFW_UE … /* Lancer SLIPORT registers */ #define SLIPORT_STATUS_OFFSET … #define SLIPORT_CONTROL_OFFSET … #define SLIPORT_ERROR1_OFFSET … #define SLIPORT_ERROR2_OFFSET … #define PHYSDEV_CONTROL_OFFSET … #define SLIPORT_STATUS_ERR_MASK … #define SLIPORT_STATUS_DIP_MASK … #define SLIPORT_STATUS_RN_MASK … #define SLIPORT_STATUS_RDY_MASK … #define SLI_PORT_CONTROL_IP_MASK … #define PHYSDEV_CONTROL_FW_RESET_MASK … #define PHYSDEV_CONTROL_DD_MASK … #define PHYSDEV_CONTROL_INP_MASK … #define SLIPORT_ERROR_NO_RESOURCE1 … #define SLIPORT_ERROR_NO_RESOURCE2 … #define SLIPORT_ERROR_FW_RESET1 … #define SLIPORT_ERROR_FW_RESET2 … /********* Memory BAR register ************/ #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET … /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt * Disable" may still globally block interrupts in addition to individual * interrupt masks; a mechanism for the device driver to block all interrupts * atomically without having to arbitrate for the PCI Interrupt Disable bit * with the OS. */ #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK … /********* PCI Function Capability *********/ #define BE_FUNCTION_CAPS_RSS … #define BE_FUNCTION_CAPS_SUPER_NIC … /********* Power management (WOL) **********/ #define PCICFG_PM_CONTROL_OFFSET … #define PCICFG_PM_CONTROL_MASK … /********* Online Control Registers *******/ #define PCICFG_ONLINE0 … #define PCICFG_ONLINE1 … /********* UE Status and Mask Registers ***/ #define PCICFG_UE_STATUS_LOW … #define PCICFG_UE_STATUS_HIGH … #define PCICFG_UE_STATUS_LOW_MASK … #define PCICFG_UE_STATUS_HI_MASK … /******** SLI_INTF ***********************/ #define SLI_INTF_REG_OFFSET … #define SLI_INTF_VALID_MASK … #define SLI_INTF_VALID … #define SLI_INTF_HINT2_MASK … #define SLI_INTF_HINT2_SHIFT … #define SLI_INTF_HINT1_MASK … #define SLI_INTF_HINT1_SHIFT … #define SLI_INTF_FAMILY_MASK … #define SLI_INTF_FAMILY_SHIFT … #define SLI_INTF_IF_TYPE_MASK … #define SLI_INTF_IF_TYPE_SHIFT … #define SLI_INTF_REV_MASK … #define SLI_INTF_REV_SHIFT … #define SLI_INTF_FT_MASK … #define SLI_INTF_TYPE_2 … #define SLI_INTF_TYPE_3 … /********* ISR0 Register offset **********/ #define CEV_ISR0_OFFSET … #define CEV_ISR_SIZE … /********* Event Q door bell *************/ #define DB_EQ_OFFSET … #define DB_EQ_RING_ID_MASK … #define DB_EQ_RING_ID_EXT_MASK … #define DB_EQ_RING_ID_EXT_MASK_SHIFT … /* Clear the interrupt for this eq */ #define DB_EQ_CLR_SHIFT … /* Must be 1 */ #define DB_EQ_EVNT_SHIFT … /* Number of event entries processed */ #define DB_EQ_NUM_POPPED_SHIFT … /* Rearm bit */ #define DB_EQ_REARM_SHIFT … /* Rearm to interrupt delay encoding */ #define DB_EQ_R2I_DLY_SHIFT … /* Rearm to interrupt (R2I) delay multiplier encoding represents 3 different * values configured in CEV_REARM2IRPT_DLY_MULT_CSR register. This value is * programmed by host driver while ringing an EQ doorbell(EQ_DB) if a delay * between rearming the EQ and next interrupt on this EQ is desired. */ #define R2I_DLY_ENC_0 … #define R2I_DLY_ENC_1 … #define R2I_DLY_ENC_2 … #define R2I_DLY_ENC_3 … /********* Compl Q door bell *************/ #define DB_CQ_OFFSET … #define DB_CQ_RING_ID_MASK … #define DB_CQ_RING_ID_EXT_MASK … #define DB_CQ_RING_ID_EXT_MASK_SHIFT … /* Number of event entries processed */ #define DB_CQ_NUM_POPPED_SHIFT … /* Rearm bit */ #define DB_CQ_REARM_SHIFT … /********** TX ULP door bell *************/ #define DB_TXULP1_OFFSET … #define DB_TXULP_RING_ID_MASK … /* Number of tx entries posted */ #define DB_TXULP_NUM_POSTED_SHIFT … #define DB_TXULP_NUM_POSTED_MASK … /********** RQ(erx) door bell ************/ #define DB_RQ_OFFSET … #define DB_RQ_RING_ID_MASK … /* Number of rx frags posted */ #define DB_RQ_NUM_POSTED_SHIFT … /********** MCC door bell ************/ #define DB_MCCQ_OFFSET … #define DB_MCCQ_RING_ID_MASK … /* Number of entries posted */ #define DB_MCCQ_NUM_POSTED_SHIFT … /********** SRIOV VF PCICFG OFFSET ********/ #define SRIOV_VF_PCICFG_OFFSET … /********** FAT TABLE ********/ #define RETRIEVE_FAT … #define QUERY_FAT … /************* Rx Packet Type Encoding **************/ #define BE_UNICAST_PACKET … #define BE_MULTICAST_PACKET … #define BE_BROADCAST_PACKET … #define BE_RSVD_PACKET … /* * BE descriptors: host memory data structures whose formats * are hardwired in BE silicon. */ /* Event Queue Descriptor */ #define EQ_ENTRY_VALID_MASK … #define EQ_ENTRY_RES_ID_MASK … #define EQ_ENTRY_RES_ID_SHIFT … struct be_eq_entry { … }; /* TX Queue Descriptor */ #define ETH_WRB_FRAG_LEN_MASK … struct be_eth_wrb { … } __packed; /* Pseudo amap definition for eth_hdr_wrb in which each bit of the * actual structure is defined as a byte : used to calculate * offset/shift/mask of each field */ struct amap_eth_hdr_wrb { … } __packed; #define TX_HDR_WRB_COMPL … #define TX_HDR_WRB_EVT … #define TX_HDR_WRB_NUM_SHIFT … #define TX_HDR_WRB_NUM_MASK … struct be_eth_hdr_wrb { … }; /********* Tx Compl Status Encoding *********/ #define BE_TX_COMP_HDR_PARSE_ERR … #define BE_TX_COMP_NDMA_ERR … #define BE_TX_COMP_ACL_ERR … #define LANCER_TX_COMP_LSO_ERR … #define LANCER_TX_COMP_HSW_DROP_MAC_ERR … #define LANCER_TX_COMP_HSW_DROP_VLAN_ERR … #define LANCER_TX_COMP_QINQ_ERR … #define LANCER_TX_COMP_SGE_ERR … #define LANCER_TX_COMP_PARITY_ERR … #define LANCER_TX_COMP_DMA_ERR … /* TX Compl Queue Descriptor */ /* Pseudo amap definition for eth_tx_compl in which each bit of the * actual structure is defined as a byte: used to calculate * offset/shift/mask of each field */ struct amap_eth_tx_compl { … } __packed; struct be_eth_tx_compl { … }; /* RX Queue Descriptor */ struct be_eth_rx_d { … }; /* RX Compl Queue Descriptor */ /* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which * each bit of the actual structure is defined as a byte: used to calculate * offset/shift/mask of each field */ struct amap_eth_rx_compl_v0 { … } __packed; /* Pseudo amap definition for BE3 native mode eth_rx_compl in which * each bit of the actual structure is defined as a byte: used to calculate * offset/shift/mask of each field */ struct amap_eth_rx_compl_v1 { … } __packed; struct be_eth_rx_compl { … };
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