/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ /* Copyright 2017-2019 NXP */ #include <linux/bitops.h> #define ENETC_MM_VERIFY_SLEEP_US … #define ENETC_MM_VERIFY_RETRIES … /* ENETC device IDs */ #define ENETC_DEV_ID_PF … #define ENETC_DEV_ID_VF … #define ENETC_DEV_ID_PTP … /* ENETC register block BAR */ #define ENETC_BAR_REGS … /** SI regs, offset: 0h */ #define ENETC_SIMR … #define ENETC_SIMR_EN … #define ENETC_SIMR_RSSE … #define ENETC_SICTR0 … #define ENETC_SICTR1 … #define ENETC_SIPCAPR0 … #define ENETC_SIPCAPR0_PSFP … #define ENETC_SIPCAPR0_RSS … #define ENETC_SIPCAPR0_QBV … #define ENETC_SIPCAPR0_QBU … #define ENETC_SIPCAPR1 … #define ENETC_SITGTGR … #define ENETC_SIRBGCR … /* cache attribute registers for transactions initiated by ENETC */ #define ENETC_SICAR0 … #define ENETC_SICAR1 … #define ENETC_SICAR2 … /* rd snoop, no alloc * wr snoop, no alloc, partial cache line update for BDs and full cache line * update for data */ #define ENETC_SICAR_RD_COHERENT … #define ENETC_SICAR_WR_COHERENT … #define ENETC_SICAR_MSI … #define ENETC_SIPMAR0 … #define ENETC_SIPMAR1 … /* VF-PF Message passing */ #define ENETC_DEFAULT_MSG_SIZE … /* msg size encoding: default and max msg value of 1024B encoded as 0 */ static inline u32 enetc_vsi_set_msize(u32 size) { … } #define ENETC_PSIMSGRR … #define ENETC_PSIMSGRR_MR_MASK … #define ENETC_PSIMSGRR_MR(n) … #define ENETC_PSIVMSGRCVAR0(n) … #define ENETC_PSIVMSGRCVAR1(n) … #define ENETC_VSIMSGSR … #define ENETC_VSIMSGSR_MB … #define ENETC_VSIMSGSR_MS … #define ENETC_VSIMSGSNDAR0 … #define ENETC_VSIMSGSNDAR1 … #define ENETC_SIMSGSR_SET_MC(val) … #define ENETC_SIMSGSR_GET_MC(val) … /* SI statistics */ #define ENETC_SIROCT … #define ENETC_SIRFRM … #define ENETC_SIRUCA … #define ENETC_SIRMCA … #define ENETC_SITOCT … #define ENETC_SITFRM … #define ENETC_SITUCA … #define ENETC_SITMCA … #define ENETC_RBDCR(n) … /* Control BDR regs */ #define ENETC_SICBDRMR … #define ENETC_SICBDRSR … #define ENETC_SICBDRBAR0 … #define ENETC_SICBDRBAR1 … #define ENETC_SICBDRPIR … #define ENETC_SICBDRCIR … #define ENETC_SICBDRLENR … #define ENETC_SICAPR0 … #define ENETC_SICAPR1 … #define ENETC_PSIIER … #define ENETC_PSIIER_MR_MASK … #define ENETC_PSIIDR … #define ENETC_SITXIDR … #define ENETC_SIRXIDR … #define ENETC_SIMSIVR … #define ENETC_SIMSITRV(n) … #define ENETC_SIMSIRRV(n) … #define ENETC_SIUEFDCR … #define ENETC_SIRFSCAPR … #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) … #define ENETC_SIRSSCAPR … #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) … /** SI BDR sub-blocks, n = 0..7 */ enum enetc_bdr_type { … }; #define ENETC_BDR_OFF(i) … #define ENETC_BDR(t, i, r) … /* RX BDR reg offsets */ #define ENETC_RBMR … #define ENETC_RBMR_BDS … #define ENETC_RBMR_CM … #define ENETC_RBMR_VTE … #define ENETC_RBMR_EN … #define ENETC_RBSR … #define ENETC_RBBSR … #define ENETC_RBCIR … #define ENETC_RBBAR0 … #define ENETC_RBBAR1 … #define ENETC_RBPIR … #define ENETC_RBLENR … #define ENETC_RBIER … #define ENETC_RBIER_RXTIE … #define ENETC_RBIDR … #define ENETC_RBICR0 … #define ENETC_RBICR0_ICEN … #define ENETC_RBICR0_ICPT_MASK … #define ENETC_RBICR0_SET_ICPT(n) … #define ENETC_RBICR1 … /* TX BDR reg offsets */ #define ENETC_TBMR … #define ENETC_TBSR_BUSY … #define ENETC_TBMR_VIH … #define ENETC_TBMR_PRIO_MASK … #define ENETC_TBMR_SET_PRIO(val) … #define ENETC_TBMR_EN … #define ENETC_TBSR … #define ENETC_TBBAR0 … #define ENETC_TBBAR1 … #define ENETC_TBPIR … #define ENETC_TBCIR … #define ENETC_TBCIR_IDX_MASK … #define ENETC_TBLENR … #define ENETC_TBIER … #define ENETC_TBIER_TXTIE … #define ENETC_TBIDR … #define ENETC_TBICR0 … #define ENETC_TBICR0_ICEN … #define ENETC_TBICR0_ICPT_MASK … #define ENETC_TBICR0_SET_ICPT(n) … #define ENETC_TBICR1 … #define ENETC_RTBLENR_LEN(n) … /* Port regs, offset: 1_0000h */ #define ENETC_PORT_BASE … #define ENETC_PMR … #define ENETC_PMR_EN … #define ENETC_PMR_PSPEED_MASK … #define ENETC_PMR_PSPEED_10M … #define ENETC_PMR_PSPEED_100M … #define ENETC_PMR_PSPEED_1000M … #define ENETC_PMR_PSPEED_2500M … #define ENETC_PSR … #define ENETC_PSIPMR … #define ENETC_PSIPMR_SET_UP(n) … #define ENETC_PSIPMR_SET_MP(n) … #define ENETC_PSIPVMR … #define ENETC_VLAN_PROMISC_MAP_ALL … #define ENETC_PSIPVMR_SET_VP(simap) … #define ENETC_PSIPVMR_SET_VUTA(simap) … #define ENETC_PSIPMAR0(n) … #define ENETC_PSIPMAR1(n) … #define ENETC_PVCLCTR … #define ENETC_PCVLANR1 … #define ENETC_PCVLANR2 … #define ENETC_VLAN_TYPE_C … #define ENETC_VLAN_TYPE_S … #define ENETC_PVCLCTR_OVTPIDL(bmp) … #define ENETC_PSIVLANR(n) … #define ENETC_PSIVLAN_EN … #define ENETC_PSIVLAN_SET_QOS(val) … #define ENETC_PPAUONTR … #define ENETC_PPAUOFFTR … #define ENETC_PTXMBAR … #define ENETC_PCAPR0 … #define ENETC_PCAPR0_RXBDR(val) … #define ENETC_PCAPR0_TXBDR(val) … #define ENETC_PCAPR1 … #define ENETC_PSICFGR0(n) … #define ENETC_PSICFGR0_SET_TXBDR(val) … #define ENETC_PSICFGR0_SET_RXBDR(val) … #define ENETC_PSICFGR0_VTE … #define ENETC_PSICFGR0_SIVIE … #define ENETC_PSICFGR0_ASE … #define ENETC_PSICFGR0_SIVC(bmp) … #define ENETC_PTCCBSR0(n) … #define ENETC_CBSE … #define ENETC_CBS_BW_MASK … #define ENETC_PTCCBSR1(n) … #define ENETC_RSSHASH_KEY_SIZE … #define ENETC_PRSSCAPR … #define ENETC_PRSSCAPR_GET_NUM_RSS(val) … #define ENETC_PRSSK(n) … #define ENETC_PSIVLANFMR … #define ENETC_PSIVLANFMR_VS … #define ENETC_PRFSMR … #define ENETC_PRFSMR_RFSE … #define ENETC_PRFSCAPR … #define ENETC_PRFSCAPR_GET_NUM_RFS(val) … #define ENETC_PSIRFSCFGR(n) … #define ENETC_PFPMR … #define ENETC_PFPMR_PMACE … #define ENETC_EMDIO_BASE … #define ENETC_PSIUMHFR0(n, err) … #define ENETC_PSIUMHFR1(n) … #define ENETC_PSIMMHFR0(n, err) … #define ENETC_PSIMMHFR1(n) … #define ENETC_PSIVHFR0(n) … #define ENETC_PSIVHFR1(n) … #define ENETC_MMCSR … #define ENETC_MMCSR_LINK_FAIL … #define ENETC_MMCSR_VT_MASK … #define ENETC_MMCSR_VT(x) … #define ENETC_MMCSR_GET_VT(x) … #define ENETC_MMCSR_TXSTS_MASK … #define ENETC_MMCSR_GET_TXSTS(x) … #define ENETC_MMCSR_VSTS_MASK … #define ENETC_MMCSR_GET_VSTS(x) … #define ENETC_MMCSR_VDIS … #define ENETC_MMCSR_ME … #define ENETC_MMCSR_RAFS_MASK … #define ENETC_MMCSR_RAFS(x) … #define ENETC_MMCSR_GET_RAFS(x) … #define ENETC_MMCSR_LAFS_MASK … #define ENETC_MMCSR_GET_LAFS(x) … #define ENETC_MMCSR_LPA … #define ENETC_MMCSR_LPE … #define ENETC_MMCSR_LPS … #define ENETC_MMFAECR … #define ENETC_MMFSECR … #define ENETC_MMFAOCR … #define ENETC_MMFCRXR … #define ENETC_MMFCTXR … #define ENETC_MMHCR … #define ENETC_PTCMSDUR(n) … #define ENETC_PMAC_OFFSET … #define ENETC_PM0_CMD_CFG … #define ENETC_PM0_TX_EN … #define ENETC_PM0_RX_EN … #define ENETC_PM0_PROMISC … #define ENETC_PM0_PAUSE_IGN … #define ENETC_PM0_CMD_XGLP … #define ENETC_PM0_CMD_TXP … #define ENETC_PM0_CMD_PHY_TX_EN … #define ENETC_PM0_CMD_SFD … #define ENETC_PM0_MAXFRM … #define ENETC_SET_TX_MTU(val) … #define ENETC_SET_MAXFRM(val) … #define ENETC_PM0_RX_FIFO … #define ENETC_PM0_RX_FIFO_VAL … #define ENETC_PM_IMDIO_BASE … #define ENETC_PM0_PAUSE_QUANTA … #define ENETC_PM0_PAUSE_THRESH … #define ENETC_PM0_SINGLE_STEP … #define ENETC_PM0_SINGLE_STEP_CH … #define ENETC_PM0_SINGLE_STEP_EN … #define ENETC_SET_SINGLE_STEP_OFFSET(v) … #define ENETC_PM0_IF_MODE … #define ENETC_PM0_IFM_RG … #define ENETC_PM0_IFM_RLP … #define ENETC_PM0_IFM_EN_AUTO … #define ENETC_PM0_IFM_SSP_MASK … #define ENETC_PM0_IFM_SSP_1000 … #define ENETC_PM0_IFM_SSP_100 … #define ENETC_PM0_IFM_SSP_10 … #define ENETC_PM0_IFM_FULL_DPX … #define ENETC_PM0_IFM_IFMODE_MASK … #define ENETC_PM0_IFM_IFMODE_XGMII … #define ENETC_PM0_IFM_IFMODE_GMII … #define ENETC_PSIDCAPR … #define ENETC_PSIDCAPR_MSK … #define ENETC_PSFCAPR … #define ENETC_PSFCAPR_MSK … #define ENETC_PSGCAPR … #define ENETC_PSGCAPR_GCL_MSK … #define ENETC_PSGCAPR_SGIT_MSK … #define ENETC_PFMCAPR … #define ENETC_PFMCAPR_MSK … /* Port MAC counters: Port MAC 0 corresponds to the eMAC and * Port MAC 1 to the pMAC. */ #define ENETC_PM_REOCT(mac) … #define ENETC_PM_RALN(mac) … #define ENETC_PM_RXPF(mac) … #define ENETC_PM_RFRM(mac) … #define ENETC_PM_RFCS(mac) … #define ENETC_PM_RVLAN(mac) … #define ENETC_PM_RERR(mac) … #define ENETC_PM_RUCA(mac) … #define ENETC_PM_RMCA(mac) … #define ENETC_PM_RBCA(mac) … #define ENETC_PM_RDRP(mac) … #define ENETC_PM_RPKT(mac) … #define ENETC_PM_RUND(mac) … #define ENETC_PM_R64(mac) … #define ENETC_PM_R127(mac) … #define ENETC_PM_R255(mac) … #define ENETC_PM_R511(mac) … #define ENETC_PM_R1023(mac) … #define ENETC_PM_R1522(mac) … #define ENETC_PM_R1523X(mac) … #define ENETC_PM_ROVR(mac) … #define ENETC_PM_RJBR(mac) … #define ENETC_PM_RFRG(mac) … #define ENETC_PM_RCNP(mac) … #define ENETC_PM_RDRNTP(mac) … #define ENETC_PM_TEOCT(mac) … #define ENETC_PM_TOCT(mac) … #define ENETC_PM_TCRSE(mac) … #define ENETC_PM_TXPF(mac) … #define ENETC_PM_TFRM(mac) … #define ENETC_PM_TFCS(mac) … #define ENETC_PM_TVLAN(mac) … #define ENETC_PM_TERR(mac) … #define ENETC_PM_TUCA(mac) … #define ENETC_PM_TMCA(mac) … #define ENETC_PM_TBCA(mac) … #define ENETC_PM_TPKT(mac) … #define ENETC_PM_TUND(mac) … #define ENETC_PM_T64(mac) … #define ENETC_PM_T127(mac) … #define ENETC_PM_T255(mac) … #define ENETC_PM_T511(mac) … #define ENETC_PM_T1023(mac) … #define ENETC_PM_T1522(mac) … #define ENETC_PM_T1523X(mac) … #define ENETC_PM_TCNP(mac) … #define ENETC_PM_TDFR(mac) … #define ENETC_PM_TMCOL(mac) … #define ENETC_PM_TSCOL(mac) … #define ENETC_PM_TLCOL(mac) … #define ENETC_PM_TECOL(mac) … /* Port counters */ #define ENETC_PICDR(n) … #define ENETC_PBFDSIR … #define ENETC_PFDMSAPR … #define ENETC_UFDMF … #define ENETC_MFDMF … #define ENETC_PUFDVFR … #define ENETC_PMFDVFR … #define ENETC_PBFDVFR … /** Global regs, offset: 2_0000h */ #define ENETC_GLOBAL_BASE … #define ENETC_G_EIPBRR0 … #define ENETC_G_EIPBRR1 … #define ENETC_G_EPFBLPR(n) … #define ENETC_G_EPFBLPR1_XGMII … /* PCI device info */ struct enetc_hw { … }; /* ENETC register accessors */ /* MDIO issue workaround (on LS1028A) - * Due to a hardware issue, an access to MDIO registers * that is concurrent with other ENETC register accesses * may lead to the MDIO access being dropped or corrupted. * To protect the MDIO accesses a readers-writers locking * scheme is used, where the MDIO register accesses are * protected by write locks to insure exclusivity, while * the remaining ENETC registers are accessed under read * locks since they only compete with MDIO accesses. */ extern rwlock_t enetc_mdio_lock; /* use this locking primitive only on the fast datapath to * group together multiple non-MDIO register accesses to * minimize the overhead of the lock */ static inline void enetc_lock_mdio(void) { … } static inline void enetc_unlock_mdio(void) { … } /* use these accessors only on the fast datapath under * the enetc_lock_mdio() locking primitive to minimize * the overhead of the lock */ static inline u32 enetc_rd_reg_hot(void __iomem *reg) { … } static inline void enetc_wr_reg_hot(void __iomem *reg, u32 val) { … } /* internal helpers for the MDIO w/a */ static inline u32 _enetc_rd_reg_wa(void __iomem *reg) { … } static inline void _enetc_wr_reg_wa(void __iomem *reg, u32 val) { … } static inline u32 _enetc_rd_mdio_reg_wa(void __iomem *reg) { … } static inline void _enetc_wr_mdio_reg_wa(void __iomem *reg, u32 val) { … } #ifdef ioread64 static inline u64 _enetc_rd_reg64(void __iomem *reg) { return ioread64(reg); } #else /* using this to read out stats on 32b systems */ static inline u64 _enetc_rd_reg64(void __iomem *reg) { … } #endif static inline u64 _enetc_rd_reg64_wa(void __iomem *reg) { … } /* general register accessors */ #define enetc_rd_reg(reg) … #define enetc_wr_reg(reg, val) … #define enetc_rd(hw, off) … #define enetc_wr(hw, off, val) … #define enetc_rd_hot(hw, off) … #define enetc_wr_hot(hw, off, val) … #define enetc_rd64(hw, off) … /* port register accessors - PF only */ #define enetc_port_rd(hw, off) … #define enetc_port_wr(hw, off, val) … #define enetc_port_rd_mdio(hw, off) … #define enetc_port_wr_mdio(hw, off, val) … /* global register accessors - PF only */ #define enetc_global_rd(hw, off) … #define enetc_global_wr(hw, off, val) … /* BDR register accessors, see ENETC_BDR() */ #define enetc_bdr_rd(hw, t, n, off) … #define enetc_bdr_wr(hw, t, n, off, val) … #define enetc_txbdr_rd(hw, n, off) … #define enetc_rxbdr_rd(hw, n, off) … #define enetc_txbdr_wr(hw, n, off, val) … #define enetc_rxbdr_wr(hw, n, off, val) … /* Buffer Descriptors (BD) */ enetc_tx_bd; enum enetc_txbd_flags { … }; #define ENETC_TXBD_STATS_WIN … #define ENETC_TXBD_TXSTART_MASK … #define ENETC_TXBD_FLAGS_OFFSET … static inline __le32 enetc_txbd_set_tx_start(u64 tx_start, u8 flags) { … } static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd) { … } /* Extension flags */ #define ENETC_TXBD_E_FLAGS_VLAN_INS … #define ENETC_TXBD_E_FLAGS_ONE_STEP_PTP … #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP … enetc_rx_bd; #define ENETC_RXBD_LSTATUS_R … #define ENETC_RXBD_LSTATUS_F … #define ENETC_RXBD_ERR_MASK … #define ENETC_RXBD_LSTATUS(flags) … #define ENETC_RXBD_FLAG_VLAN … #define ENETC_RXBD_FLAG_TSTMP … #define ENETC_RXBD_FLAG_TPID … #define ENETC_MAC_ADDR_FILT_CNT … #define EMETC_MAC_ADDR_FILT_RES … #define ENETC_MAX_NUM_VFS … #define ENETC_CBD_FLAGS_SF … #define ENETC_CBD_STATUS_MASK … struct enetc_cmd_rfse { … }; #define ENETC_RFSE_EN … #define ENETC_RFSE_MODE_BD … static inline void enetc_load_primary_mac_addr(struct enetc_hw *hw, struct net_device *ndev) { … } #define ENETC_SI_INT_IDX … /* base index for Rx/Tx interrupts */ #define ENETC_BDR_INT_BASE_IDX … /* Messaging */ /* Command completion status */ enum enetc_msg_cmd_status { … }; /* VSI-PSI command message types */ enum enetc_msg_cmd_type { … }; /* VSI-PSI command action types */ enum enetc_msg_cmd_action_type { … }; /* PSI-VSI command header format */ struct enetc_msg_cmd_header { … }; /* Common H/W utility functions */ static inline void enetc_bdr_enable_rxvlan(struct enetc_hw *hw, int idx, bool en) { … } static inline void enetc_bdr_enable_txvlan(struct enetc_hw *hw, int idx, bool en) { … } static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx, int prio) { … } enum bdcr_cmd_class { … }; /* class 5, command 0 */ struct tgs_gcl_conf { … }; /* gate control list entry */ struct gce { … }; /* tgs_gcl_conf address point to this data space */ struct tgs_gcl_data { … }; /* class 7, command 0, Stream Identity Entry Configuration */ struct streamid_conf { … }; #define ENETC_CBDR_SID_VID_MASK … #define ENETC_CBDR_SID_VIDM … #define ENETC_CBDR_SID_TG_MASK … /* streamid_conf address point to this data space */ struct streamid_data { … }; #define ENETC_CBDR_SFI_PRI_MASK … #define ENETC_CBDR_SFI_PRIM … #define ENETC_CBDR_SFI_BLOV … #define ENETC_CBDR_SFI_BLEN … #define ENETC_CBDR_SFI_MSDUEN … #define ENETC_CBDR_SFI_FMITEN … #define ENETC_CBDR_SFI_ENABLE … /* class 8, command 0, Stream Filter Instance, Short Format */ struct sfi_conf { … }; /* class 8, command 2 stream Filter Instance status query short format * command no need structure define * Stream Filter Instance Query Statistics Response data */ struct sfi_counter_data { … }; #define ENETC_CBDR_SGI_OIPV_MASK … #define ENETC_CBDR_SGI_OIPV_EN … #define ENETC_CBDR_SGI_CGTST … #define ENETC_CBDR_SGI_OGTST … #define ENETC_CBDR_SGI_CFG_CHG … #define ENETC_CBDR_SGI_CFG_PND … #define ENETC_CBDR_SGI_OEX … #define ENETC_CBDR_SGI_OEXEN … #define ENETC_CBDR_SGI_IRX … #define ENETC_CBDR_SGI_IRXEN … #define ENETC_CBDR_SGI_ACLLEN_MASK … #define ENETC_CBDR_SGI_OCLLEN_MASK … #define ENETC_CBDR_SGI_EN … /* class 9, command 0, Stream Gate Instance Table, Short Format * class 9, command 2, Stream Gate Instance Table entry query write back * Short Format */ struct sgi_table { … }; #define ENETC_CBDR_SGI_AIPV_MASK … #define ENETC_CBDR_SGI_AIPV_EN … #define ENETC_CBDR_SGI_AGTST … /* class 9, command 1, Stream Gate Control List, Long Format */ struct sgcl_conf { … }; #define ENETC_CBDR_SGL_IOMEN … #define ENETC_CBDR_SGL_IPVEN … #define ENETC_CBDR_SGL_GTST … #define ENETC_CBDR_SGL_IPV_MASK … /* Stream Gate Control List Entry */ struct sgce { … }; /* stream control list class 9 , cmd 1 data buffer */ struct sgcl_data { … }; #define ENETC_CBDR_FMI_MR … #define ENETC_CBDR_FMI_MREN … #define ENETC_CBDR_FMI_DOY … #define ENETC_CBDR_FMI_CM … #define ENETC_CBDR_FMI_CF … #define ENETC_CBDR_FMI_NDOR … #define ENETC_CBDR_FMI_OALEN … #define ENETC_CBDR_FMI_IRFPP_MASK … /* class 10: command 0/1, Flow Meter Instance Set, short Format */ struct fmi_conf { … }; struct enetc_cbd { … }; #define ENETC_CLK … static inline u32 enetc_cycles_to_usecs(u32 cycles) { … } static inline u32 enetc_usecs_to_cycles(u32 usecs) { … } /* Port traffic class frame preemption register */ #define ENETC_PTCFPR(n) … #define ENETC_PTCFPR_FPE … /* port time gating control register */ #define ENETC_PTGCR … #define ENETC_PTGCR_TGE … #define ENETC_PTGCR_TGPE … /* Port time gating capability register */ #define ENETC_PTGCAPR … #define ENETC_PTGCAPR_MAX_GCL_LEN_MASK … /* Port time specific departure */ #define ENETC_PTCTSDR(n) … #define ENETC_TSDE … /* PSFP setting */ #define ENETC_PPSFPMR … #define ENETC_PPSFPMR_PSFPEN … #define ENETC_PPSFPMR_VS … #define ENETC_PPSFPMR_PVC … #define ENETC_PPSFPMR_PVZC …
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