// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* Copyright 2021 NXP * * The Integrated Endpoint Register Block (IERB) is configured by pre-boot * software and is supposed to be to ENETC what a NVRAM is to a 'real' PCIe * card. Upon FLR, values from the IERB are transferred to the ENETC PFs, and * are read-only in the PF memory space. * * This driver fixes up the power-on reset values for the ENETC shared FIFO, * such that the TX and RX allocations are sufficient for jumbo frames, and * that intelligent FIFO dropping is enabled before the internal data * structures are corrupted. * * Even though not all ports might be used on a given board, we are not * concerned with partitioning the FIFO, because the default values configure * no strict reservations, so the entire FIFO can be used by the RX of a single * port, or the TX of a single port. */ #include <linux/io.h> #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/platform_device.h> #include "enetc.h" #include "enetc_ierb.h" /* IERB registers */ #define ENETC_IERB_TXMBAR(port) … #define ENETC_IERB_RXMBER(port) … #define ENETC_IERB_RXMBLR(port) … #define ENETC_IERB_RXBCR(port) … #define ENETC_IERB_TXBCR(port) … #define ENETC_IERB_FMBDTR … #define ENETC_RESERVED_FOR_ICM … struct enetc_ierb { … }; static void enetc_ierb_write(struct enetc_ierb *ierb, u32 offset, u32 val) { … } int enetc_ierb_register_pf(struct platform_device *pdev, struct pci_dev *pf_pdev) { … } EXPORT_SYMBOL(…); static int enetc_ierb_probe(struct platform_device *pdev) { … } static const struct of_device_id enetc_ierb_match[] = …; MODULE_DEVICE_TABLE(of, enetc_ierb_match); static struct platform_driver enetc_ierb_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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