/* * QorIQ 10G MDIO Controller * * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2021 NXP * * Authors: Andy Fleming <[email protected]> * Timur Tabi <[email protected]> * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ #include <linux/acpi.h> #include <linux/acpi_mdio.h> #include <linux/clk.h> #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/mdio.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_mdio.h> #include <linux/phy.h> #include <linux/platform_device.h> #include <linux/slab.h> /* Number of microseconds to wait for a register to respond */ #define TIMEOUT … struct tgec_mdio_controller { … } __packed; #define MDIO_STAT_ENC … #define MDIO_STAT_CLKDIV(x) … #define MDIO_STAT_BSY … #define MDIO_STAT_RD_ER … #define MDIO_STAT_PRE_DIS … #define MDIO_CTL_DEV_ADDR(x) … #define MDIO_CTL_PORT_ADDR(x) … #define MDIO_CTL_PRE_DIS … #define MDIO_CTL_SCAN_EN … #define MDIO_CTL_POST_INC … #define MDIO_CTL_READ … #define MDIO_DATA(x) … struct mdio_fsl_priv { … }; static u32 xgmac_read32(void __iomem *regs, bool is_little_endian) { … } static void xgmac_write32(u32 value, void __iomem *regs, bool is_little_endian) { … } /* * Wait until the MDIO bus is free */ static int xgmac_wait_until_free(struct device *dev, struct tgec_mdio_controller __iomem *regs, bool is_little_endian) { … } /* * Wait till the MDIO read or write operation is complete */ static int xgmac_wait_until_done(struct device *dev, struct tgec_mdio_controller __iomem *regs, bool is_little_endian) { … } static int xgmac_mdio_write_c22(struct mii_bus *bus, int phy_id, int regnum, u16 value) { … } static int xgmac_mdio_write_c45(struct mii_bus *bus, int phy_id, int dev_addr, int regnum, u16 value) { … } /* Reads from register regnum in the PHY for device dev, returning the value. * Clears miimcom first. All PHY configuration has to be done through the * TSEC1 MIIM regs. */ static int xgmac_mdio_read_c22(struct mii_bus *bus, int phy_id, int regnum) { … } /* Reads from register regnum in the PHY for device dev, returning the value. * Clears miimcom first. All PHY configuration has to be done through the * TSEC1 MIIM regs. */ static int xgmac_mdio_read_c45(struct mii_bus *bus, int phy_id, int dev_addr, int regnum) { … } static int xgmac_mdio_set_mdc_freq(struct mii_bus *bus) { … } static void xgmac_mdio_set_suppress_preamble(struct mii_bus *bus) { … } static int xgmac_mdio_probe(struct platform_device *pdev) { … } static const struct of_device_id xgmac_mdio_match[] = …; MODULE_DEVICE_TABLE(of, xgmac_mdio_match); static const struct acpi_device_id xgmac_acpi_match[] = …; MODULE_DEVICE_TABLE(acpi, xgmac_acpi_match); static struct platform_driver xgmac_mdio_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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