/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * drivers/net/ethernet/freescale/gianfar.h * * Gianfar Ethernet Driver * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560 * Based on 8260_io/fcc_enet.c * * Author: Andy Fleming * Maintainer: Kumar Gala * Modifier: Sandeep Gopalpet <[email protected]> * * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc. * * Still left to do: * -Add support for module parameters * -Add patch for ethtool phys id */ #ifndef __GIANFAR_H #define __GIANFAR_H #include <linux/kernel.h> #include <linux/sched.h> #include <linux/string.h> #include <linux/errno.h> #include <linux/slab.h> #include <linux/interrupt.h> #include <linux/delay.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/skbuff.h> #include <linux/spinlock.h> #include <linux/mm.h> #include <linux/mii.h> #include <linux/phy.h> #include <asm/io.h> #include <asm/irq.h> #include <linux/uaccess.h> #include <linux/module.h> #include <linux/crc32.h> #include <linux/workqueue.h> #include <linux/ethtool.h> struct ethtool_flow_spec_container { … }; struct ethtool_rx_list { … }; /* Length for FCB */ #define GMAC_FCB_LEN … /* Length for TxPAL */ #define GMAC_TXPAL_LEN … /* Default padding amount */ #define DEFAULT_PADDING … /* Number of bytes to align the rx bufs to */ #define RXBUF_ALIGNMENT … #define DRV_NAME … /* MAXIMUM NUMBER OF QUEUES SUPPORTED */ #define MAX_TX_QS … #define MAX_RX_QS … /* MAXIMUM NUMBER OF GROUPS SUPPORTED */ #define MAXGROUPS … /* These need to be powers of 2 for this driver */ #define DEFAULT_TX_RING_SIZE … #define DEFAULT_RX_RING_SIZE … #define GFAR_RX_BUFF_ALLOC … #define GFAR_RX_MAX_RING_SIZE … #define GFAR_TX_MAX_RING_SIZE … #define FBTHR_SHIFT … #define DEFAULT_RX_LFC_THR … #define DEFAULT_LFC_PTVVAL … #define GFAR_RXB_TRUESIZE … #define GFAR_SKBFRAG_OVR … #define GFAR_RXB_SIZE … #define GFAR_SKBFRAG_SIZE … #define TX_RING_MOD_MASK(size) … #define RX_RING_MOD_MASK(size) … #define GFAR_JUMBO_FRAME_SIZE … #define DEFAULT_FIFO_TX_THR … #define DEFAULT_FIFO_TX_STARVE … #define DEFAULT_FIFO_TX_STARVE_OFF … /* The number of Exact Match registers */ #define GFAR_EM_NUM … /* Latency of interface clock in nanoseconds */ /* Interface clock latency , in this case, means the * time described by a value of 1 in the interrupt * coalescing registers' time fields. Since those fields * refer to the time it takes for 64 clocks to pass, the * latencies are as such: * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick */ #define GFAR_GBIT_TIME … #define GFAR_100_TIME … #define GFAR_10_TIME … #define DEFAULT_TX_COALESCE … #define DEFAULT_TXCOUNT … #define DEFAULT_TXTIME … #define DEFAULT_RXTIME … #define DEFAULT_RX_COALESCE … #define DEFAULT_RXCOUNT … /* TBI register addresses */ #define MII_TBICON … /* TBICON register bit fields */ #define TBICON_CLK_SELECT … /* MAC register bits */ #define MACCFG1_SOFT_RESET … #define MACCFG1_RESET_RX_MC … #define MACCFG1_RESET_TX_MC … #define MACCFG1_RESET_RX_FUN … #define MACCFG1_RESET_TX_FUN … #define MACCFG1_LOOPBACK … #define MACCFG1_RX_FLOW … #define MACCFG1_TX_FLOW … #define MACCFG1_SYNCD_RX_EN … #define MACCFG1_RX_EN … #define MACCFG1_SYNCD_TX_EN … #define MACCFG1_TX_EN … #define MACCFG2_INIT_SETTINGS … #define MACCFG2_FULL_DUPLEX … #define MACCFG2_IF … #define MACCFG2_MII … #define MACCFG2_GMII … #define MACCFG2_HUGEFRAME … #define MACCFG2_LENGTHCHECK … #define MACCFG2_MPEN … #define ECNTRL_FIFM … #define ECNTRL_INIT_SETTINGS … #define ECNTRL_TBI_MODE … #define ECNTRL_REDUCED_MODE … #define ECNTRL_R100 … #define ECNTRL_REDUCED_MII_MODE … #define ECNTRL_SGMII_MODE … #define MINFLR_INIT_SETTINGS … /* Tqueue control */ #define TQUEUE_EN0 … #define TQUEUE_EN1 … #define TQUEUE_EN2 … #define TQUEUE_EN3 … #define TQUEUE_EN4 … #define TQUEUE_EN5 … #define TQUEUE_EN6 … #define TQUEUE_EN7 … #define TQUEUE_EN_ALL … #define TR03WT_WT0_MASK … #define TR03WT_WT1_MASK … #define TR03WT_WT2_MASK … #define TR03WT_WT3_MASK … #define TR47WT_WT4_MASK … #define TR47WT_WT5_MASK … #define TR47WT_WT6_MASK … #define TR47WT_WT7_MASK … /* Rqueue control */ #define RQUEUE_EX0 … #define RQUEUE_EX1 … #define RQUEUE_EX2 … #define RQUEUE_EX3 … #define RQUEUE_EX4 … #define RQUEUE_EX5 … #define RQUEUE_EX6 … #define RQUEUE_EX7 … #define RQUEUE_EX_ALL … #define RQUEUE_EN0 … #define RQUEUE_EN1 … #define RQUEUE_EN2 … #define RQUEUE_EN3 … #define RQUEUE_EN4 … #define RQUEUE_EN5 … #define RQUEUE_EN6 … #define RQUEUE_EN7 … #define RQUEUE_EN_ALL … /* Init to do tx snooping for buffers and descriptors */ #define DMACTRL_INIT_SETTINGS … #define DMACTRL_GRS … #define DMACTRL_GTS … #define TSTAT_CLEAR_THALT_ALL … #define TSTAT_CLEAR_THALT … #define TSTAT_CLEAR_THALT0 … #define TSTAT_CLEAR_THALT1 … #define TSTAT_CLEAR_THALT2 … #define TSTAT_CLEAR_THALT3 … #define TSTAT_CLEAR_THALT4 … #define TSTAT_CLEAR_THALT5 … #define TSTAT_CLEAR_THALT6 … #define TSTAT_CLEAR_THALT7 … /* Interrupt coalescing macros */ #define IC_ICEN … #define IC_ICFT_MASK … #define IC_ICFT_SHIFT … #define mk_ic_icft(x) … #define IC_ICTT_MASK … #define mk_ic_ictt(x) … #define mk_ic_value(count, time) … #define get_icft_value(ic) … #define get_ictt_value(ic) … #define DEFAULT_TXIC … #define DEFAULT_RXIC … #define RCTRL_TS_ENABLE … #define RCTRL_PAL_MASK … #define RCTRL_LFC … #define RCTRL_VLEX … #define RCTRL_FILREN … #define RCTRL_GHTX … #define RCTRL_IPCSEN … #define RCTRL_TUCSEN … #define RCTRL_PRSDEP_MASK … #define RCTRL_PRSDEP_INIT … #define RCTRL_PRSFM … #define RCTRL_PROM … #define RCTRL_EMEN … #define RCTRL_REQ_PARSER … #define RCTRL_CHECKSUMMING … #define RCTRL_EXTHASH … #define RCTRL_VLAN … #define RCTRL_PADDING(x) … #define RSTAT_CLEAR_RHALT … #define RSTAT_CLEAR_RXF0 … #define RSTAT_RXF_MASK … #define TCTRL_IPCSEN … #define TCTRL_TUCSEN … #define TCTRL_VLINS … #define TCTRL_THDF … #define TCTRL_RFCPAUSE … #define TCTRL_TFCPAUSE … #define TCTRL_TXSCHED_MASK … #define TCTRL_TXSCHED_INIT … /* priority scheduling */ #define TCTRL_TXSCHED_PRIO … /* weighted round-robin scheduling (WRRS) */ #define TCTRL_TXSCHED_WRRS … /* default WRRS weight and policy setting, * tailored to the tr03wt and tr47wt registers: * equal weight for all Tx Qs, measured in 64byte units */ #define DEFAULT_WRRS_WEIGHT … #define TCTRL_INIT_CSUM … #define IEVENT_INIT_CLEAR … #define IEVENT_BABR … #define IEVENT_RXC … #define IEVENT_BSY … #define IEVENT_EBERR … #define IEVENT_MSRO … #define IEVENT_GTSC … #define IEVENT_BABT … #define IEVENT_TXC … #define IEVENT_TXE … #define IEVENT_TXB … #define IEVENT_TXF … #define IEVENT_LC … #define IEVENT_CRL … #define IEVENT_XFUN … #define IEVENT_RXB0 … #define IEVENT_MAG … #define IEVENT_GRSC … #define IEVENT_RXF0 … #define IEVENT_FGPI … #define IEVENT_FIR … #define IEVENT_FIQ … #define IEVENT_DPE … #define IEVENT_PERR … #define IEVENT_RX_MASK … #define IEVENT_TX_MASK … #define IEVENT_RTX_MASK … #define IEVENT_ERR_MASK … #define IMASK_INIT_CLEAR … #define IMASK_BABR … #define IMASK_RXC … #define IMASK_BSY … #define IMASK_EBERR … #define IMASK_MSRO … #define IMASK_GTSC … #define IMASK_BABT … #define IMASK_TXC … #define IMASK_TXEEN … #define IMASK_TXBEN … #define IMASK_TXFEN … #define IMASK_LC … #define IMASK_CRL … #define IMASK_XFUN … #define IMASK_RXB0 … #define IMASK_MAG … #define IMASK_GRSC … #define IMASK_RXFEN0 … #define IMASK_FGPI … #define IMASK_FIR … #define IMASK_FIQ … #define IMASK_DPE … #define IMASK_PERR … #define IMASK_DEFAULT … #define IMASK_RX_DEFAULT … #define IMASK_TX_DEFAULT … #define IMASK_RX_DISABLED … #define IMASK_TX_DISABLED … /* Attribute fields */ /* This enables rx snooping for buffers and descriptors */ #define ATTR_BDSTASH … #define ATTR_BUFSTASH … #define ATTR_SNOOPING … #define ATTR_INIT_SETTINGS … #define ATTRELI_INIT_SETTINGS … #define ATTRELI_EL_MASK … #define ATTRELI_EL(x) … #define ATTRELI_EI_MASK … #define ATTRELI_EI(x) … #define BD_LFLAG(flags) … #define BD_LENGTH_MASK … #define FPR_FILER_MASK … #define MAX_FILER_IDX … /* This default RIR value directly corresponds * to the 3-bit hash value generated */ #define DEFAULT_8RXQ_RIR0 … /* Map even hash values to Q0, and odd ones to Q1 */ #define DEFAULT_2RXQ_RIR0 … /* RQFCR register bits */ #define RQFCR_GPI … #define RQFCR_HASHTBL_Q … #define RQFCR_HASHTBL_0 … #define RQFCR_HASHTBL_1 … #define RQFCR_HASHTBL_2 … #define RQFCR_HASHTBL_3 … #define RQFCR_HASH … #define RQFCR_QUEUE … #define RQFCR_CLE … #define RQFCR_RJE … #define RQFCR_AND … #define RQFCR_CMP_EXACT … #define RQFCR_CMP_MATCH … #define RQFCR_CMP_NOEXACT … #define RQFCR_CMP_NOMATCH … /* RQFCR PID values */ #define RQFCR_PID_MASK … #define RQFCR_PID_PARSE … #define RQFCR_PID_ARB … #define RQFCR_PID_DAH … #define RQFCR_PID_DAL … #define RQFCR_PID_SAH … #define RQFCR_PID_SAL … #define RQFCR_PID_ETY … #define RQFCR_PID_VID … #define RQFCR_PID_PRI … #define RQFCR_PID_TOS … #define RQFCR_PID_L4P … #define RQFCR_PID_DIA … #define RQFCR_PID_SIA … #define RQFCR_PID_DPT … #define RQFCR_PID_SPT … /* RQFPR when PID is 0x0001 */ #define RQFPR_HDR_GE_512 … #define RQFPR_LERR … #define RQFPR_RAR … #define RQFPR_RARQ … #define RQFPR_AR … #define RQFPR_ARQ … #define RQFPR_EBC … #define RQFPR_VLN … #define RQFPR_CFI … #define RQFPR_JUM … #define RQFPR_IPF … #define RQFPR_FIF … #define RQFPR_IPV4 … #define RQFPR_IPV6 … #define RQFPR_ICC … #define RQFPR_ICV … #define RQFPR_TCP … #define RQFPR_UDP … #define RQFPR_TUC … #define RQFPR_TUV … #define RQFPR_PER … #define RQFPR_EER … /* CAR1 bits */ #define CAR1_C164 … #define CAR1_C1127 … #define CAR1_C1255 … #define CAR1_C1511 … #define CAR1_C11K … #define CAR1_C1MAX … #define CAR1_C1MGV … #define CAR1_C1REJ … #define CAR1_C1RBY … #define CAR1_C1RPK … #define CAR1_C1RFC … #define CAR1_C1RMC … #define CAR1_C1RBC … #define CAR1_C1RXC … #define CAR1_C1RXP … #define CAR1_C1RXU … #define CAR1_C1RAL … #define CAR1_C1RFL … #define CAR1_C1RCD … #define CAR1_C1RCS … #define CAR1_C1RUN … #define CAR1_C1ROV … #define CAR1_C1RFR … #define CAR1_C1RJB … #define CAR1_C1RDR … /* CAM1 bits */ #define CAM1_M164 … #define CAM1_M1127 … #define CAM1_M1255 … #define CAM1_M1511 … #define CAM1_M11K … #define CAM1_M1MAX … #define CAM1_M1MGV … #define CAM1_M1REJ … #define CAM1_M1RBY … #define CAM1_M1RPK … #define CAM1_M1RFC … #define CAM1_M1RMC … #define CAM1_M1RBC … #define CAM1_M1RXC … #define CAM1_M1RXP … #define CAM1_M1RXU … #define CAM1_M1RAL … #define CAM1_M1RFL … #define CAM1_M1RCD … #define CAM1_M1RCS … #define CAM1_M1RUN … #define CAM1_M1ROV … #define CAM1_M1RFR … #define CAM1_M1RJB … #define CAM1_M1RDR … /* TxBD status field bits */ #define TXBD_READY … #define TXBD_PADCRC … #define TXBD_WRAP … #define TXBD_INTERRUPT … #define TXBD_LAST … #define TXBD_CRC … #define TXBD_DEF … #define TXBD_HUGEFRAME … #define TXBD_LATECOLLISION … #define TXBD_RETRYLIMIT … #define TXBD_RETRYCOUNTMASK … #define TXBD_UNDERRUN … #define TXBD_TOE … /* Tx FCB param bits */ #define TXFCB_VLN … #define TXFCB_IP … #define TXFCB_IP6 … #define TXFCB_TUP … #define TXFCB_UDP … #define TXFCB_CIP … #define TXFCB_CTU … #define TXFCB_NPH … #define TXFCB_DEFAULT … /* RxBD status field bits */ #define RXBD_EMPTY … #define RXBD_RO1 … #define RXBD_WRAP … #define RXBD_INTERRUPT … #define RXBD_LAST … #define RXBD_FIRST … #define RXBD_MISS … #define RXBD_BROADCAST … #define RXBD_MULTICAST … #define RXBD_LARGE … #define RXBD_NONOCTET … #define RXBD_SHORT … #define RXBD_CRCERR … #define RXBD_OVERRUN … #define RXBD_TRUNCATED … #define RXBD_STATS … #define RXBD_ERR … /* Rx FCB status field bits */ #define RXFCB_VLN … #define RXFCB_IP … #define RXFCB_IP6 … #define RXFCB_TUP … #define RXFCB_CIP … #define RXFCB_CTU … #define RXFCB_EIP … #define RXFCB_ETU … #define RXFCB_CSUM_MASK … #define RXFCB_PERR_MASK … #define RXFCB_PERR_BADL3 … #define GFAR_INT_NAME_MAX … #define GFAR_WOL_MAGIC … #define GFAR_WOL_FILER_UCAST … struct txbd8 { … }; struct txfcb { … }; struct rxbd8 { … }; struct rxfcb { … }; struct gianfar_skb_cb { … }; #define GFAR_CB(skb) … struct rmon_mib { … }; struct rmon_overflow { … }; struct gfar_extra_stats { … }; #define GFAR_RMON_LEN … #define GFAR_EXTRA_STATS_LEN … /* Number of stats exported via ethtool */ #define GFAR_STATS_LEN … struct gfar { … }; /* Flags related to gianfar device features */ #define FSL_GIANFAR_DEV_HAS_GIGABIT … #define FSL_GIANFAR_DEV_HAS_COALESCE … #define FSL_GIANFAR_DEV_HAS_RMON … #define FSL_GIANFAR_DEV_HAS_MULTI_INTR … #define FSL_GIANFAR_DEV_HAS_CSUM … #define FSL_GIANFAR_DEV_HAS_VLAN … #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH … #define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET … #define FSL_GIANFAR_DEV_HAS_BD_STASHING … #define FSL_GIANFAR_DEV_HAS_BUF_STASHING … #define FSL_GIANFAR_DEV_HAS_TIMER … #define FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER … #define FSL_GIANFAR_DEV_HAS_RX_FILER … #if (MAXGROUPS == 2) #define DEFAULT_MAPPING … #else #define DEFAULT_MAPPING … #endif #define ISRG_RR0 … #define ISRG_TR0 … /* The same driver can operate in two modes */ /* SQ_SG_MODE: Single Queue Single Group Mode * (Backward compatible mode) * MQ_MG_MODE: Multi Queue Multi Group mode */ enum { … }; /* * Per TX queue stats */ struct tx_q_stats { … }; /** * struct gfar_priv_tx_q - per tx queue structure * @txlock: per queue tx spin lock * @tx_skbuff:skb pointers * @skb_curtx: to be used skb pointer * @skb_dirtytx:the last used skb pointer * @stats: bytes/packets stats * @qindex: index of this queue * @dev: back pointer to the dev structure * @grp: back pointer to the group to which this queue belongs * @tx_bd_base: First tx buffer descriptor * @cur_tx: Next free ring entry * @dirty_tx: First buffer in line to be transmitted * @tx_ring_size: Tx ring size * @num_txbdfree: number of free TxBds * @txcoalescing: enable/disable tx coalescing * @txic: transmit interrupt coalescing value * @txcount: coalescing value if based on tx frame count * @txtime: coalescing value if based on time */ struct gfar_priv_tx_q { … }; /* * Per RX queue stats */ struct rx_q_stats { … }; struct gfar_rx_buff { … }; /** * struct gfar_priv_rx_q - per rx queue structure * @rx_buff: Array of buffer info metadata structs * @rx_bd_base: First rx buffer descriptor * @next_to_use: index of the next buffer to be alloc'd * @next_to_clean: index of the next buffer to be cleaned * @qindex: index of this queue * @ndev: back pointer to net_device * @rx_ring_size: Rx ring size * @rxcoalescing: enable/disable rx-coalescing * @rxic: receive interrupt coalescing vlaue */ struct gfar_priv_rx_q { … }; enum gfar_irqinfo_id { … }; struct gfar_irqinfo { … }; /** * struct gfar_priv_grp - per group structure * @napi: the napi poll function * @priv: back pointer to the priv structure * @regs: the ioremapped register space for this group * @irqinfo: TX/RX/ER irq data for this group */ struct gfar_priv_grp { … }; #define gfar_irq(grp, ID) … enum gfar_errata { … }; enum gfar_dev_state { … }; /* Struct stolen almost completely (and shamelessly) from the FCC enet source * (Ok, that's not so true anymore, but there is a family resemblance) * The GFAR buffer descriptors track the ring buffers. The rx_bd_base * and tx_bd_base always point to the currently available buffer. * The dirty_tx tracks the current buffer that is being sent by the * controller. The cur_tx and dirty_tx are equal under both completely * empty and completely full conditions. The empty/ready indicator in * the buffer descriptor determines the actual condition. */ struct gfar_private { … }; static inline int gfar_has_errata(struct gfar_private *priv, enum gfar_errata err) { … } static inline u32 gfar_read(unsigned __iomem *addr) { … } static inline void gfar_write(unsigned __iomem *addr, u32 val) { … } static inline void gfar_write_filer(struct gfar_private *priv, unsigned int far, unsigned int fcr, unsigned int fpr) { … } static inline void gfar_read_filer(struct gfar_private *priv, unsigned int far, unsigned int *fcr, unsigned int *fpr) { … } static inline void gfar_write_isrg(struct gfar_private *priv) { … } static inline int gfar_is_dma_stopped(struct gfar_private *priv) { … } static inline int gfar_is_rx_dma_stopped(struct gfar_private *priv) { … } static inline void gfar_wmb(void) { … } static inline void gfar_clear_txbd_status(struct txbd8 *bdp) { … } static inline int gfar_rxbd_unused(struct gfar_priv_rx_q *rxq) { … } static inline u32 gfar_rxbd_dma_lastfree(struct gfar_priv_rx_q *rxq) { … } int startup_gfar(struct net_device *dev); void stop_gfar(struct net_device *dev); void gfar_mac_reset(struct gfar_private *priv); int gfar_set_features(struct net_device *dev, netdev_features_t features); extern const struct ethtool_ops gfar_ethtool_ops; #define MAX_FILER_CACHE_IDX … #define RQFCR_PID_PRI_MASK … #define RQFCR_PID_L4P_MASK … #define RQFCR_PID_VID_MASK … #define RQFCR_PID_PORT_MASK … #define RQFCR_PID_MAC_MASK … /* Represents a receive filer table entry */ struct gfar_filer_entry { … }; /* The 20 additional entries are a shadow for one extra element */ struct filer_table { … }; #endif /* __GIANFAR_H */
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