// SPDX-License-Identifier: GPL-2.0 /* * Fast Ethernet Controller (ENET) PTP driver for MX6x. * * Copyright (C) 2012 Freescale Semiconductor, Inc. */ #define pr_fmt(fmt) … #include <linux/module.h> #include <linux/kernel.h> #include <linux/string.h> #include <linux/ptrace.h> #include <linux/errno.h> #include <linux/ioport.h> #include <linux/slab.h> #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/delay.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/skbuff.h> #include <linux/spinlock.h> #include <linux/workqueue.h> #include <linux/bitops.h> #include <linux/io.h> #include <linux/irq.h> #include <linux/clk.h> #include <linux/platform_device.h> #include <linux/phy.h> #include <linux/fec.h> #include <linux/of.h> #include <linux/of_gpio.h> #include <linux/of_net.h> #include "fec.h" /* FEC 1588 register bits */ #define FEC_T_CTRL_SLAVE … #define FEC_T_CTRL_CAPTURE … #define FEC_T_CTRL_RESTART … #define FEC_T_CTRL_PERIOD_RST … #define FEC_T_CTRL_PERIOD_EN … #define FEC_T_CTRL_ENABLE … #define FEC_T_INC_MASK … #define FEC_T_INC_OFFSET … #define FEC_T_INC_CORR_MASK … #define FEC_T_INC_CORR_OFFSET … #define FEC_T_CTRL_PINPER … #define FEC_T_TF0_MASK … #define FEC_T_TF0_OFFSET … #define FEC_T_TF1_MASK … #define FEC_T_TF1_OFFSET … #define FEC_T_TF2_MASK … #define FEC_T_TF2_OFFSET … #define FEC_T_TF3_MASK … #define FEC_T_TF3_OFFSET … #define FEC_T_TDRE_MASK … #define FEC_T_TDRE_OFFSET … #define FEC_T_TMODE_MASK … #define FEC_T_TMODE_OFFSET … #define FEC_T_TIE_MASK … #define FEC_T_TIE_OFFSET … #define FEC_T_TF_MASK … #define FEC_T_TF_OFFSET … #define FEC_ATIME_CTRL … #define FEC_ATIME … #define FEC_ATIME_EVT_OFFSET … #define FEC_ATIME_EVT_PERIOD … #define FEC_ATIME_CORR … #define FEC_ATIME_INC … #define FEC_TS_TIMESTAMP … #define FEC_TGSR … #define FEC_TCSR(n) … #define FEC_TCCR(n) … #define MAX_TIMER_CHANNEL … #define FEC_TMODE_TOGGLE … #define FEC_HIGH_PULSE … #define FEC_CC_MULT … #define FEC_COUNTER_PERIOD … #define PPS_OUPUT_RELOAD_PERIOD … #define FEC_CHANNLE_0 … #define DEFAULT_PPS_CHANNEL … #define FEC_PTP_MAX_NSEC_PERIOD … #define FEC_PTP_MAX_NSEC_COUNTER … /** * fec_ptp_enable_pps * @fep: the fec_enet_private structure handle * @enable: enable the channel pps output * * This function enble the PPS ouput on the timer channel. */ static int fec_ptp_enable_pps(struct fec_enet_private *fep, uint enable) { … } static int fec_ptp_pps_perout(struct fec_enet_private *fep) { … } static enum hrtimer_restart fec_ptp_pps_perout_handler(struct hrtimer *timer) { … } /** * fec_ptp_read - read raw cycle counter (to be used by time counter) * @cc: the cyclecounter structure * * this function reads the cyclecounter registers and is called by the * cyclecounter structure used to construct a ns counter from the * arbitrary fixed point registers */ static u64 fec_ptp_read(const struct cyclecounter *cc) { … } /** * fec_ptp_start_cyclecounter - create the cycle counter from hw * @ndev: network device * * this function initializes the timecounter and cyclecounter * structures for use in generated a ns counter from the arbitrary * fixed point cycles registers in the hardware. */ void fec_ptp_start_cyclecounter(struct net_device *ndev) { … } /** * fec_ptp_adjfine - adjust ptp cycle frequency * @ptp: the ptp clock structure * @scaled_ppm: scaled parts per million adjustment from base * * Adjust the frequency of the ptp cycle counter by the * indicated amount from the base frequency. * * Scaled parts per million is ppm with a 16-bit binary fractional field. * * Because ENET hardware frequency adjust is complex, * using software method to do that. */ static int fec_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) { … } /** * fec_ptp_adjtime * @ptp: the ptp clock structure * @delta: offset to adjust the cycle counter by * * adjust the timer by resetting the timecounter structure. */ static int fec_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) { … } /** * fec_ptp_gettime * @ptp: the ptp clock structure * @ts: timespec structure to hold the current time value * * read the timecounter and return the correct value on ns, * after converting it into a struct timespec. */ static int fec_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) { … } /** * fec_ptp_settime * @ptp: the ptp clock structure * @ts: the timespec containing the new time for the cycle counter * * reset the timecounter to use a new base value instead of the kernel * wall timer value. */ static int fec_ptp_settime(struct ptp_clock_info *ptp, const struct timespec64 *ts) { … } static int fec_ptp_pps_disable(struct fec_enet_private *fep, uint channel) { … } /** * fec_ptp_enable * @ptp: the ptp clock structure * @rq: the requested feature to change * @on: whether to enable or disable the feature * */ static int fec_ptp_enable(struct ptp_clock_info *ptp, struct ptp_clock_request *rq, int on) { … } int fec_ptp_set(struct net_device *ndev, struct kernel_hwtstamp_config *config, struct netlink_ext_ack *extack) { … } void fec_ptp_get(struct net_device *ndev, struct kernel_hwtstamp_config *config) { … } /* * fec_time_keep - call timecounter_read every second to avoid timer overrun * because ENET just support 32bit counter, will timeout in 4s */ static void fec_time_keep(struct work_struct *work) { … } /* This function checks the pps event and reloads the timer compare counter. */ static irqreturn_t fec_pps_interrupt(int irq, void *dev_id) { … } /** * fec_ptp_init * @pdev: The FEC network adapter * @irq_idx: the interrupt index * * This function performs the required steps for enabling ptp * support. If ptp support has already been loaded it simply calls the * cyclecounter init routine and exits. */ void fec_ptp_init(struct platform_device *pdev, int irq_idx) { … } void fec_ptp_stop(struct platform_device *pdev) { … }
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