/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2014-2015 Hisilicon Limited. */ #ifndef _DSAF_REG_H_ #define _DSAF_REG_H_ #include <linux/regmap.h> #define HNS_DEBUG_RING_IRQ_IDX … #define HNS_SERVICE_RING_IRQ_IDX … #define HNSV2_SERVICE_RING_IRQ_IDX … #define DSAF_MAX_PORT_NUM … #define DSAF_MAX_VM_NUM … #define DSAF_COMM_DEV_NUM … #define DSAF_PPE_INODE_BASE … #define DSAF_DEBUG_NW_NUM … #define DSAF_SERVICE_NW_NUM … #define DSAF_COMM_CHN … #define DSAF_GE_NUM … #define DSAF_XGE_NUM … #define DSAF_PORT_TYPE_NUM … #define DSAF_NODE_NUM … #define DSAF_XOD_BIG_NUM … #define DSAF_SBM_NUM … #define DSAFV2_SBM_NUM … #define DSAFV2_SBM_XGE_CHN … #define DSAFV2_SBM_PPE_CHN … #define DASFV2_ROCEE_CRD_NUM … #define DSAF_VOQ_NUM … #define DSAF_INODE_NUM … #define DSAF_XOD_NUM … #define DSAF_TBL_NUM … #define DSAF_SW_PORT_NUM … #define DSAF_TOTAL_QUEUE_NUM … /* reserved a tcam entry for each port to support promisc by fuzzy match */ #define DSAFV2_MAC_FUZZY_TCAM_NUM … #define DSAF_TCAM_SUM … #define DSAF_LINE_SUM … #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG … #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG … #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG … #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG … #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG … #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG … #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG … #define DSAF_SUB_SC_DSAF_CLK_EN_REG … #define DSAF_SUB_SC_DSAF_CLK_DIS_REG … #define DSAF_SUB_SC_NT_CLK_EN_REG … #define DSAF_SUB_SC_NT_CLK_DIS_REG … #define DSAF_SUB_SC_XGE_CLK_EN_REG … #define DSAF_SUB_SC_XGE_CLK_DIS_REG … #define DSAF_SUB_SC_GE_CLK_EN_REG … #define DSAF_SUB_SC_GE_CLK_DIS_REG … #define DSAF_SUB_SC_PPE_CLK_EN_REG … #define DSAF_SUB_SC_PPE_CLK_DIS_REG … #define DSAF_SUB_SC_RCB_PPE_COM_CLK_EN_REG … #define DSAF_SUB_SC_RCB_PPE_COM_CLK_DIS_REG … #define DSAF_SUB_SC_XBAR_RESET_REQ_REG … #define DSAF_SUB_SC_XBAR_RESET_DREQ_REG … #define DSAF_SUB_SC_NT_RESET_REQ_REG … #define DSAF_SUB_SC_NT_RESET_DREQ_REG … #define DSAF_SUB_SC_XGE_RESET_REQ_REG … #define DSAF_SUB_SC_XGE_RESET_DREQ_REG … #define DSAF_SUB_SC_GE_RESET_REQ0_REG … #define DSAF_SUB_SC_GE_RESET_DREQ0_REG … #define DSAF_SUB_SC_GE_RESET_REQ1_REG … #define DSAF_SUB_SC_GE_RESET_DREQ1_REG … #define DSAF_SUB_SC_PPE_RESET_REQ_REG … #define DSAF_SUB_SC_PPE_RESET_DREQ_REG … #define DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG … #define DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG … #define DSAF_SUB_SC_DSAF_RESET_REQ_REG … #define DSAF_SUB_SC_DSAF_RESET_DREQ_REG … #define DSAF_SUB_SC_ROCEE_RESET_REQ_REG … #define DSAF_SUB_SC_ROCEE_RESET_DREQ_REG … #define DSAF_SUB_SC_ROCEE_CLK_DIS_REG … #define DSAF_SUB_SC_ROCEE_CLK_EN_REG … #define DSAF_SUB_SC_LIGHT_MODULE_DETECT_EN_REG … #define DSAF_SUB_SC_TCAM_MBIST_EN_REG … #define DSAF_SUB_SC_DSAF_CLK_ST_REG … #define DSAF_SUB_SC_NT_CLK_ST_REG … #define DSAF_SUB_SC_XGE_CLK_ST_REG … #define DSAF_SUB_SC_GE_CLK_ST_REG … #define DSAF_SUB_SC_PPE_CLK_ST_REG … #define DSAF_SUB_SC_ROCEE_CLK_ST_REG … #define DSAF_SUB_SC_CPU_CLK_ST_REG … #define DSAF_SUB_SC_RCB_PPE_COM_CLK_ST_REG … #define DSAF_SUB_SC_XBAR_RESET_ST_REG … #define DSAF_SUB_SC_NT_RESET_ST_REG … #define DSAF_SUB_SC_XGE_RESET_ST_REG … #define DSAF_SUB_SC_GE_RESET_ST0_REG … #define DSAF_SUB_SC_GE_RESET_ST1_REG … #define DSAF_SUB_SC_PPE_RESET_ST_REG … #define DSAF_SUB_SC_RCB_PPE_COM_RESET_ST_REG … /*serdes offset**/ #define HNS_MAC_HILINK3_REG … #define HNS_MAC_HILINK4_REG … #define HNS_MAC_HILINK3V2_REG … #define HNS_MAC_HILINK4V2_REG … #define HNS_MAC_LANE0_CTLEDFE_REG … #define HNS_MAC_LANE1_CTLEDFE_REG … #define HNS_MAC_LANE2_CTLEDFE_REG … #define HNS_MAC_LANE3_CTLEDFE_REG … #define HNS_MAC_LANE0_STATE_REG … #define HNS_MAC_LANE1_STATE_REG … #define HNS_MAC_LANE2_STATE_REG … #define HNS_MAC_LANE3_STATE_REG … #define HILINK_RESET_TIMOUT … #define DSAF_SRAM_INIT_OVER_0_REG … #define DSAF_CFG_0_REG … #define DSAF_ECC_ERR_INVERT_0_REG … #define DSAF_ABNORMAL_TIMEOUT_0_REG … #define DSAF_FSM_TIMEOUT_0_REG … #define DSAF_DSA_REG_CNT_CLR_CE_REG … #define DSAF_DSA_SBM_INF_FIFO_THRD_REG … #define DSAF_DSA_SRAM_1BIT_ECC_SEL_REG … #define DSAF_DSA_SRAM_1BIT_ECC_CNT_REG … #define DSAF_PFC_EN_0_REG … #define DSAF_PFC_UNIT_CNT_0_REG … #define DSAF_XGE_INT_MSK_0_REG … #define DSAF_PPE_INT_MSK_0_REG … #define DSAF_ROCEE_INT_MSK_0_REG … #define DSAF_XGE_INT_SRC_0_REG … #define DSAF_PPE_INT_SRC_0_REG … #define DSAF_ROCEE_INT_SRC_0_REG … #define DSAF_XGE_INT_STS_0_REG … #define DSAF_PPE_INT_STS_0_REG … #define DSAF_ROCEE_INT_STS_0_REG … #define DSAFV2_SERDES_LBK_0_REG … #define DSAF_PAUSE_CFG_REG … #define DSAF_ROCE_PORT_MAP_REG … #define DSAF_ROCE_SL_MAP_REG … #define DSAF_PPE_QID_CFG_0_REG … #define DSAF_SW_PORT_TYPE_0_REG … #define DSAF_STP_PORT_TYPE_0_REG … #define DSAF_MIX_DEF_QID_0_REG … #define DSAF_PORT_DEF_VLAN_0_REG … #define DSAF_VM_DEF_VLAN_0_REG … #define DSAF_INODE_CUT_THROUGH_CFG_0_REG … #define DSAF_INODE_ECC_INVERT_EN_0_REG … #define DSAF_INODE_ECC_ERR_ADDR_0_REG … #define DSAF_INODE_IN_PORT_NUM_0_REG … #define DSAF_INODE_PRI_TC_CFG_0_REG … #define DSAF_INODE_BP_STATUS_0_REG … #define DSAF_INODE_PAD_DISCARD_NUM_0_REG … #define DSAF_INODE_FINAL_IN_MAN_NUM_0_REG … #define DSAF_INODE_FINAL_IN_PKT_NUM_0_REG … #define DSAF_INODE_SBM_PID_NUM_0_REG … #define DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG … #define DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG … #define DSAF_INODE_SBM_RELS_NUM_0_REG … #define DSAF_INODE_SBM_DROP_NUM_0_REG … #define DSAF_INODE_CRC_FALSE_NUM_0_REG … #define DSAF_INODE_BP_DISCARD_NUM_0_REG … #define DSAF_INODE_RSLT_DISCARD_NUM_0_REG … #define DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG … #define DSAF_INODE_VOQ_OVER_NUM_0_REG … #define DSAF_INODE_BD_SAVE_STATUS_0_REG … #define DSAF_INODE_BD_ORDER_STATUS_0_REG … #define DSAF_INODE_SW_VLAN_TAG_DISC_0_REG … #define DSAF_INODE_IN_DATA_STP_DISC_0_REG … #define DSAF_INODE_GE_FC_EN_0_REG … #define DSAF_INODE_VC0_IN_PKT_NUM_0_REG … #define DSAF_INODE_VC1_IN_PKT_NUM_0_REG … #define DSAF_INODE_IN_PRIO_PAUSE_BASE_REG … #define DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET … #define DSAF_INODE_IN_PRIO_PAUSE_OFFSET … #define DSAF_SBM_CFG_REG_0_REG … #define DSAF_SBM_BP_CFG_0_XGE_REG_0_REG … #define DSAF_SBM_BP_CFG_0_PPE_REG_0_REG … #define DSAF_SBM_BP_CFG_0_ROCEE_REG_0_REG … #define DSAF_SBM_BP_CFG_1_REG_0_REG … #define DSAF_SBM_BP_CFG_2_XGE_REG_0_REG … #define DSAF_SBM_BP_CFG_2_PPE_REG_0_REG … #define DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG … #define DSAF_SBM_ROCEE_CFG_REG_REG … #define DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG … #define DSAF_SBM_FREE_CNT_0_0_REG … #define DSAF_SBM_FREE_CNT_1_0_REG … #define DSAF_SBM_BP_CNT_0_0_REG … #define DSAF_SBM_BP_CNT_1_0_REG … #define DSAF_SBM_BP_CNT_2_0_REG … #define DSAF_SBM_BP_CNT_3_0_REG … #define DSAF_SBM_INER_ST_0_REG … #define DSAF_SBM_MIB_REQ_FAILED_TC_0_REG … #define DSAF_SBM_LNK_INPORT_CNT_0_REG … #define DSAF_SBM_LNK_DROP_CNT_0_REG … #define DSAF_SBM_INF_OUTPORT_CNT_0_REG … #define DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG … #define DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG … #define DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG … #define DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG … #define DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG … #define DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG … #define DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG … #define DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG … #define DSAF_SBM_LNK_REQ_CNT_0_REG … #define DSAF_SBM_LNK_RELS_CNT_0_REG … #define DSAF_SBM_BP_CFG_3_REG_0_REG … #define DSAF_SBM_BP_CFG_4_REG_0_REG … #define DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG … #define DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG … #define DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG … #define DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG … #define DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG … #define DSAF_XOD_ETS_TOKEN_CFG_0_REG … #define DSAF_XOD_PFS_CFG_0_0_REG … #define DSAF_XOD_PFS_CFG_1_0_REG … #define DSAF_XOD_PFS_CFG_2_0_REG … #define DSAF_XOD_GNT_L_0_REG … #define DSAF_XOD_GNT_H_0_REG … #define DSAF_XOD_CONNECT_STATE_0_REG … #define DSAF_XOD_RCVPKT_CNT_0_REG … #define DSAF_XOD_RCVTC0_CNT_0_REG … #define DSAF_XOD_RCVTC1_CNT_0_REG … #define DSAF_XOD_RCVTC2_CNT_0_REG … #define DSAF_XOD_RCVTC3_CNT_0_REG … #define DSAF_XOD_RCVVC0_CNT_0_REG … #define DSAF_XOD_RCVVC1_CNT_0_REG … #define DSAF_XOD_XGE_RCVIN0_CNT_0_REG … #define DSAF_XOD_XGE_RCVIN1_CNT_0_REG … #define DSAF_XOD_XGE_RCVIN2_CNT_0_REG … #define DSAF_XOD_XGE_RCVIN3_CNT_0_REG … #define DSAF_XOD_XGE_RCVIN4_CNT_0_REG … #define DSAF_XOD_XGE_RCVIN5_CNT_0_REG … #define DSAF_XOD_XGE_RCVIN6_CNT_0_REG … #define DSAF_XOD_XGE_RCVIN7_CNT_0_REG … #define DSAF_XOD_PPE_RCVIN0_CNT_0_REG … #define DSAF_XOD_PPE_RCVIN1_CNT_0_REG … #define DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG … #define DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG … #define DSAF_XOD_FIFO_STATUS_0_REG … #define DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG … #define DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET … #define DSAF_VOQ_ECC_INVERT_EN_0_REG … #define DSAF_VOQ_SRAM_PKT_NUM_0_REG … #define DSAF_VOQ_IN_PKT_NUM_0_REG … #define DSAF_VOQ_OUT_PKT_NUM_0_REG … #define DSAF_VOQ_ECC_ERR_ADDR_0_REG … #define DSAF_VOQ_BP_STATUS_0_REG … #define DSAF_VOQ_SPUP_IDLE_0_REG … #define DSAF_VOQ_XGE_XOD_REQ_0_0_REG … #define DSAF_VOQ_XGE_XOD_REQ_1_0_REG … #define DSAF_VOQ_PPE_XOD_REQ_0_REG … #define DSAF_VOQ_ROCEE_XOD_REQ_0_REG … #define DSAF_VOQ_BP_ALL_THRD_0_REG … #define DSAF_TBL_CTRL_0_REG … #define DSAF_TBL_INT_MSK_0_REG … #define DSAF_TBL_INT_SRC_0_REG … #define DSAF_TBL_INT_STS_0_REG … #define DSAF_TBL_TCAM_ADDR_0_REG … #define DSAF_TBL_LINE_ADDR_0_REG … #define DSAF_TBL_TCAM_HIGH_0_REG … #define DSAF_TBL_TCAM_LOW_0_REG … #define DSAF_TBL_TCAM_MCAST_CFG_4_0_REG … #define DSAF_TBL_TCAM_MCAST_CFG_3_0_REG … #define DSAF_TBL_TCAM_MCAST_CFG_2_0_REG … #define DSAF_TBL_TCAM_MCAST_CFG_1_0_REG … #define DSAF_TBL_TCAM_MCAST_CFG_0_0_REG … #define DSAF_TBL_TCAM_UCAST_CFG_0_REG … #define DSAF_TBL_LIN_CFG_0_REG … #define DSAF_TBL_TCAM_RDATA_HIGH_0_REG … #define DSAF_TBL_TCAM_RDATA_LOW_0_REG … #define DSAF_TBL_TCAM_RAM_RDATA4_0_REG … #define DSAF_TBL_TCAM_RAM_RDATA3_0_REG … #define DSAF_TBL_TCAM_RAM_RDATA2_0_REG … #define DSAF_TBL_TCAM_RAM_RDATA1_0_REG … #define DSAF_TBL_TCAM_RAM_RDATA0_0_REG … #define DSAF_TBL_LIN_RDATA_0_REG … #define DSAF_TBL_DA0_MIS_INFO1_0_REG … #define DSAF_TBL_DA0_MIS_INFO0_0_REG … #define DSAF_TBL_SA_MIS_INFO2_0_REG … #define DSAF_TBL_SA_MIS_INFO1_0_REG … #define DSAF_TBL_SA_MIS_INFO0_0_REG … #define DSAF_TBL_PUL_0_REG … #define DSAF_TBL_OLD_RSLT_0_REG … #define DSAF_TBL_OLD_SCAN_VAL_0_REG … #define DSAF_TBL_DFX_CTRL_0_REG … #define DSAF_TBL_DFX_STAT_0_REG … #define DSAF_TBL_DFX_STAT_2_0_REG … #define DSAF_TBL_LKUP_NUM_I_0_REG … #define DSAF_TBL_LKUP_NUM_O_0_REG … #define DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG … #define DSAF_TBL_TCAM_MATCH_CFG_H_REG … #define DSAF_TBL_TCAM_MATCH_CFG_L_REG … #define DSAF_INODE_FIFO_WL_0_REG … #define DSAF_ONODE_FIFO_WL_0_REG … #define DSAF_XGE_GE_WORK_MODE_0_REG … #define DSAF_XGE_APP_RX_LINK_UP_0_REG … #define DSAF_NETPORT_CTRL_SIG_0_REG … #define DSAF_XGE_CTRL_SIG_CFG_0_REG … #define PPE_COM_CFG_QID_MODE_REG … #define PPE_COM_INTEN_REG … #define PPE_COM_RINT_REG … #define PPE_COM_INTSTS_REG … #define PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG … #define PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG … #define PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG … #define PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG … #define PPE_COM_COMMON_CNT_CLR_CE_REG … #define PPE_CFG_TX_FIFO_THRSLD_REG … #define PPE_CFG_RX_FIFO_THRSLD_REG … #define PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG … #define PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG … #define PPE_CFG_PAUSE_IDLE_CNT_REG … #define PPE_CFG_BUS_CTRL_REG … #define PPE_CFG_TNL_TO_BE_RST_REG … #define PPE_CURR_TNL_CAN_RST_REG … #define PPE_CFG_XGE_MODE_REG … #define PPE_CFG_MAX_FRAME_LEN_REG … #define PPE_CFG_RX_PKT_MODE_REG … #define PPE_CFG_RX_VLAN_TAG_REG … #define PPE_CFG_TAG_GEN_REG … #define PPE_CFG_PARSE_TAG_REG … #define PPE_CFG_PRO_CHECK_EN_REG … #define PPEV2_CFG_TSO_EN_REG … #define PPEV2_VLAN_STRIP_EN_REG … #define PPE_INTEN_REG … #define PPE_RINT_REG … #define PPE_INTSTS_REG … #define PPE_CFG_RX_PKT_INT_REG … #define PPE_CFG_HEAT_DECT_TIME0_REG … #define PPE_CFG_HEAT_DECT_TIME1_REG … #define PPE_HIS_RX_SW_PKT_CNT_REG … #define PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG … #define PPE_HIS_RX_PKT_NO_BUF_CNT_REG … #define PPE_HIS_TX_BD_CNT_REG … #define PPE_HIS_TX_PKT_CNT_REG … #define PPE_HIS_TX_PKT_OK_CNT_REG … #define PPE_HIS_TX_PKT_EPT_CNT_REG … #define PPE_HIS_TX_PKT_CS_FAIL_CNT_REG … #define PPE_HIS_RX_APP_BUF_FAIL_CNT_REG … #define PPE_HIS_RX_APP_BUF_WAIT_CNT_REG … #define PPE_HIS_RX_PKT_DROP_FUL_CNT_REG … #define PPE_HIS_RX_PKT_DROP_PRT_CNT_REG … #define PPE_TNL_0_5_CNT_CLR_CE_REG … #define PPE_CFG_AXI_DBG_REG … #define PPE_HIS_PRO_ERR_REG … #define PPE_HIS_TNL_FIFO_ERR_REG … #define PPE_CURR_CFF_DATA_NUM_REG … #define PPE_CURR_RX_ST_REG … #define PPE_CURR_TX_ST_REG … #define PPE_CURR_RX_FIFO0_REG … #define PPE_CURR_RX_FIFO1_REG … #define PPE_CURR_TX_FIFO0_REG … #define PPE_CURR_TX_FIFO1_REG … #define PPE_ECO0_REG … #define PPE_ECO1_REG … #define PPE_ECO2_REG … #define PPEV2_INDRECTION_TBL_REG … #define PPEV2_RSS_KEY_REG … #define RCB_COM_CFG_ENDIAN_REG … #define RCB_COM_CFG_SYS_FSH_REG … #define RCB_COM_CFG_INIT_FLAG_REG … #define RCB_COM_CFG_PKT_REG … #define RCB_COM_CFG_RINVLD_REG … #define RCB_COM_CFG_FNA_REG … #define RCB_COM_CFG_FA_REG … #define RCB_COM_CFG_PKT_TC_BP_REG … #define RCB_COM_CFG_PPE_TNL_CLKEN_REG … #define RCBV2_COM_CFG_USER_REG … #define RCBV2_COM_CFG_TSO_MODE_REG … #define RCB_COM_INTMSK_TX_PKT_REG … #define RCB_COM_RINT_TX_PKT_REG … #define RCB_COM_INTMASK_ECC_ERR_REG … #define RCB_COM_INTSTS_ECC_ERR_REG … #define RCB_COM_EBD_SRAM_ERR_REG … #define RCB_COM_RXRING_ERR_REG … #define RCB_COM_TXRING_ERR_REG … #define RCB_COM_TX_FBD_ERR_REG … #define RCB_SRAM_ECC_CHK_EN_REG … #define RCB_SRAM_ECC_CHK0_REG … #define RCB_SRAM_ECC_CHK1_REG … #define RCB_SRAM_ECC_CHK2_REG … #define RCB_SRAM_ECC_CHK3_REG … #define RCB_SRAM_ECC_CHK4_REG … #define RCB_SRAM_ECC_CHK5_REG … #define RCB_ECC_ERR_ADDR0_REG … #define RCB_ECC_ERR_ADDR3_REG … #define RCB_ECC_ERR_ADDR4_REG … #define RCB_ECC_ERR_ADDR5_REG … #define RCB_COM_SF_CFG_INTMASK_RING … #define RCB_COM_SF_CFG_RING_STS … #define RCB_COM_SF_CFG_RING … #define RCB_COM_SF_CFG_INTMASK_BD … #define RCB_COM_SF_CFG_BD_RINT_STS … #define RCB_COM_RCB_RD_BD_BUSY … #define RCB_COM_RCB_FBD_CRT_EN … #define RCB_COM_AXI_WR_ERR_INTMASK … #define RCB_COM_AXI_ERR_STS … #define RCB_COM_CHK_TX_FBD_NUM_REG … #define RCB_CFG_BD_NUM_REG … #define RCB_CFG_PKTLINE_REG … #define RCB_CFG_OVERTIME_REG … #define RCB_CFG_PKTLINE_INT_NUM_REG … #define RCB_CFG_OVERTIME_INT_NUM_REG … #define RCB_PORT_INT_GAPTIME_REG … #define RCB_PORT_CFG_OVERTIME_REG … #define RCB_RING_RX_RING_BASEADDR_L_REG … #define RCB_RING_RX_RING_BASEADDR_H_REG … #define RCB_RING_RX_RING_BD_NUM_REG … #define RCB_RING_RX_RING_BD_LEN_REG … #define RCB_RING_RX_RING_PKTLINE_REG … #define RCB_RING_RX_RING_TAIL_REG … #define RCB_RING_RX_RING_HEAD_REG … #define RCB_RING_RX_RING_FBDNUM_REG … #define RCB_RING_RX_RING_PKTNUM_RECORD_REG … #define RCB_RING_TX_RING_BASEADDR_L_REG … #define RCB_RING_TX_RING_BASEADDR_H_REG … #define RCB_RING_TX_RING_BD_NUM_REG … #define RCB_RING_TX_RING_BD_LEN_REG … #define RCB_RING_TX_RING_PKTLINE_REG … #define RCB_RING_TX_RING_TAIL_REG … #define RCB_RING_TX_RING_HEAD_REG … #define RCB_RING_TX_RING_FBDNUM_REG … #define RCB_RING_TX_RING_OFFSET_REG … #define RCB_RING_TX_RING_PKTNUM_RECORD_REG … #define RCB_RING_PREFETCH_EN_REG … #define RCB_RING_CFG_VF_NUM_REG … #define RCB_RING_ASID_REG … #define RCB_RING_RX_VM_REG … #define RCB_RING_T0_BE_RST … #define RCB_RING_COULD_BE_RST … #define RCB_RING_WRR_WEIGHT_REG … #define RCB_RING_INTMSK_RXWL_REG … #define RCB_RING_INTSTS_RX_RING_REG … #define RCBV2_RX_RING_INT_STS_REG … #define RCB_RING_INTMSK_TXWL_REG … #define RCB_RING_INTSTS_TX_RING_REG … #define RCBV2_TX_RING_INT_STS_REG … #define RCB_RING_INTMSK_RX_OVERTIME_REG … #define RCB_RING_INTSTS_RX_OVERTIME_REG … #define RCB_RING_INTMSK_TX_OVERTIME_REG … #define RCB_RING_INTSTS_TX_OVERTIME_REG … #define GMAC_FIFO_STATE_REG … #define GMAC_DUPLEX_TYPE_REG … #define GMAC_FD_FC_TYPE_REG … #define GMAC_TX_WATER_LINE_REG … #define GMAC_FC_TX_TIMER_REG … #define GMAC_FD_FC_ADDR_LOW_REG … #define GMAC_FD_FC_ADDR_HIGH_REG … #define GMAC_IPG_TX_TIMER_REG … #define GMAC_PAUSE_THR_REG … #define GMAC_MAX_FRM_SIZE_REG … #define GMAC_PORT_MODE_REG … #define GMAC_PORT_EN_REG … #define GMAC_PAUSE_EN_REG … #define GMAC_SHORT_RUNTS_THR_REG … #define GMAC_AN_NEG_STATE_REG … #define GMAC_TX_LOCAL_PAGE_REG … #define GMAC_TRANSMIT_CONTROL_REG … #define GMAC_REC_FILT_CONTROL_REG … #define GMAC_PTP_CONFIG_REG … #define GMAC_RX_OCTETS_TOTAL_OK_REG … #define GMAC_RX_OCTETS_BAD_REG … #define GMAC_RX_UC_PKTS_REG … #define GMAC_RX_MC_PKTS_REG … #define GMAC_RX_BC_PKTS_REG … #define GMAC_RX_PKTS_64OCTETS_REG … #define GMAC_RX_PKTS_65TO127OCTETS_REG … #define GMAC_RX_PKTS_128TO255OCTETS_REG … #define GMAC_RX_PKTS_255TO511OCTETS_REG … #define GMAC_RX_PKTS_512TO1023OCTETS_REG … #define GMAC_RX_PKTS_1024TO1518OCTETS_REG … #define GMAC_RX_PKTS_1519TOMAXOCTETS_REG … #define GMAC_RX_FCS_ERRORS_REG … #define GMAC_RX_TAGGED_REG … #define GMAC_RX_DATA_ERR_REG … #define GMAC_RX_ALIGN_ERRORS_REG … #define GMAC_RX_LONG_ERRORS_REG … #define GMAC_RX_JABBER_ERRORS_REG … #define GMAC_RX_PAUSE_MACCTRL_FRAM_REG … #define GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG … #define GMAC_RX_VERY_LONG_ERR_CNT_REG … #define GMAC_RX_RUNT_ERR_CNT_REG … #define GMAC_RX_SHORT_ERR_CNT_REG … #define GMAC_RX_FILT_PKT_CNT_REG … #define GMAC_RX_OCTETS_TOTAL_FILT_REG … #define GMAC_OCTETS_TRANSMITTED_OK_REG … #define GMAC_OCTETS_TRANSMITTED_BAD_REG … #define GMAC_TX_UC_PKTS_REG … #define GMAC_TX_MC_PKTS_REG … #define GMAC_TX_BC_PKTS_REG … #define GMAC_TX_PKTS_64OCTETS_REG … #define GMAC_TX_PKTS_65TO127OCTETS_REG … #define GMAC_TX_PKTS_128TO255OCTETS_REG … #define GMAC_TX_PKTS_255TO511OCTETS_REG … #define GMAC_TX_PKTS_512TO1023OCTETS_REG … #define GMAC_TX_PKTS_1024TO1518OCTETS_REG … #define GMAC_TX_PKTS_1519TOMAXOCTETS_REG … #define GMAC_TX_EXCESSIVE_LENGTH_DROP_REG … #define GMAC_TX_UNDERRUN_REG … #define GMAC_TX_TAGGED_REG … #define GMAC_TX_CRC_ERROR_REG … #define GMAC_TX_PAUSE_FRAMES_REG … #define GAMC_RX_MAX_FRAME … #define GMAC_LINE_LOOP_BACK_REG … #define GMAC_CF_CRC_STRIP_REG … #define GMAC_MODE_CHANGE_EN_REG … #define GMAC_SIXTEEN_BIT_CNTR_REG … #define GMAC_LD_LINK_COUNTER_REG … #define GMAC_LOOP_REG … #define GMAC_RECV_CONTROL_REG … #define GMAC_PCS_RX_EN_REG … #define GMAC_VLAN_CODE_REG … #define GMAC_RX_OVERRUN_CNT_REG … #define GMAC_RX_LENGTHFIELD_ERR_CNT_REG … #define GMAC_RX_FAIL_COMMA_CNT_REG … #define GMAC_STATION_ADDR_LOW_0_REG … #define GMAC_STATION_ADDR_HIGH_0_REG … #define GMAC_STATION_ADDR_LOW_1_REG … #define GMAC_STATION_ADDR_HIGH_1_REG … #define GMAC_STATION_ADDR_LOW_2_REG … #define GMAC_STATION_ADDR_HIGH_2_REG … #define GMAC_STATION_ADDR_LOW_3_REG … #define GMAC_STATION_ADDR_HIGH_3_REG … #define GMAC_STATION_ADDR_LOW_4_REG … #define GMAC_STATION_ADDR_HIGH_4_REG … #define GMAC_STATION_ADDR_LOW_5_REG … #define GMAC_STATION_ADDR_HIGH_5_REG … #define GMAC_STATION_ADDR_LOW_MSK_0_REG … #define GMAC_STATION_ADDR_HIGH_MSK_0_REG … #define GMAC_STATION_ADDR_LOW_MSK_1_REG … #define GMAC_STATION_ADDR_HIGH_MSK_1_REG … #define GMAC_MAC_SKIP_LEN_REG … #define GMAC_TX_LOOP_PKT_PRI_REG … #define XGMAC_INT_STATUS_REG … #define XGMAC_INT_ENABLE_REG … #define XGMAC_INT_SET_REG … #define XGMAC_IERR_U_INFO_REG … #define XGMAC_OVF_INFO_REG … #define XGMAC_OVF_CNT_REG … #define XGMAC_PORT_MODE_REG … #define XGMAC_CLK_ENABLE_REG … #define XGMAC_RESET_REG … #define XGMAC_LINK_CONTROL_REG … #define XGMAC_LINK_STATUS_REG … #define XGMAC_SPARE_REG … #define XGMAC_SPARE_CNT_REG … #define XGMAC_MAC_ENABLE_REG … #define XGMAC_MAC_CONTROL_REG … #define XGMAC_MAC_IPG_REG … #define XGMAC_MAC_MSG_CRC_EN_REG … #define XGMAC_MAC_MSG_IMG_REG … #define XGMAC_MAC_MSG_FC_CFG_REG … #define XGMAC_MAC_MSG_TC_CFG_REG … #define XGMAC_MAC_PAD_SIZE_REG … #define XGMAC_MAC_MIN_PKT_SIZE_REG … #define XGMAC_MAC_MAX_PKT_SIZE_REG … #define XGMAC_MAC_PAUSE_CTRL_REG … #define XGMAC_MAC_PAUSE_TIME_REG … #define XGMAC_MAC_PAUSE_GAP_REG … #define XGMAC_MAC_PAUSE_LOCAL_MAC_H_REG … #define XGMAC_MAC_PAUSE_LOCAL_MAC_L_REG … #define XGMAC_MAC_PAUSE_PEER_MAC_H_REG … #define XGMAC_MAC_PAUSE_PEER_MAC_L_REG … #define XGMAC_MAC_PFC_PRI_EN_REG … #define XGMAC_MAC_1588_CTRL_REG … #define XGMAC_MAC_1588_TX_PORT_DLY_REG … #define XGMAC_MAC_1588_RX_PORT_DLY_REG … #define XGMAC_MAC_1588_ASYM_DLY_REG … #define XGMAC_MAC_1588_ADJUST_CFG_REG … #define XGMAC_MAC_Y1731_ETH_TYPE_REG … #define XGMAC_MAC_MIB_CONTROL_REG … #define XGMAC_MAC_WAN_RATE_ADJUST_REG … #define XGMAC_MAC_TX_ERR_MARK_REG … #define XGMAC_MAC_TX_LF_RF_CONTROL_REG … #define XGMAC_MAC_RX_LF_RF_STATUS_REG … #define XGMAC_MAC_TX_RUNT_PKT_CNT_REG … #define XGMAC_MAC_RX_RUNT_PKT_CNT_REG … #define XGMAC_MAC_RX_PREAM_ERR_PKT_CNT_REG … #define XGMAC_MAC_TX_LF_RF_TERM_PKT_CNT_REG … #define XGMAC_MAC_TX_SN_MISMATCH_PKT_CNT_REG … #define XGMAC_MAC_RX_ERR_MSG_CNT_REG … #define XGMAC_MAC_RX_ERR_EFD_CNT_REG … #define XGMAC_MAC_ERR_INFO_REG … #define XGMAC_MAC_DBG_INFO_REG … #define XGMAC_PCS_BASER_SYNC_THD_REG … #define XGMAC_PCS_STATUS1_REG … #define XGMAC_PCS_BASER_STATUS1_REG … #define XGMAC_PCS_BASER_STATUS2_REG … #define XGMAC_PCS_BASER_SEEDA_0_REG … #define XGMAC_PCS_BASER_SEEDA_1_REG … #define XGMAC_PCS_BASER_SEEDB_0_REG … #define XGMAC_PCS_BASER_SEEDB_1_REG … #define XGMAC_PCS_BASER_TEST_CONTROL_REG … #define XGMAC_PCS_BASER_TEST_ERR_CNT_REG … #define XGMAC_PCS_DBG_INFO_REG … #define XGMAC_PCS_DBG_INFO1_REG … #define XGMAC_PCS_DBG_INFO2_REG … #define XGMAC_PCS_DBG_INFO3_REG … #define XGMAC_PMA_ENABLE_REG … #define XGMAC_PMA_CONTROL_REG … #define XGMAC_PMA_SIGNAL_STATUS_REG … #define XGMAC_PMA_DBG_INFO_REG … #define XGMAC_PMA_FEC_ABILITY_REG … #define XGMAC_PMA_FEC_CONTROL_REG … #define XGMAC_PMA_FEC_CORR_BLOCK_CNT__REG … #define XGMAC_PMA_FEC_UNCORR_BLOCK_CNT__REG … #define XGMAC_TX_PKTS_FRAGMENT … #define XGMAC_TX_PKTS_UNDERSIZE … #define XGMAC_TX_PKTS_UNDERMIN … #define XGMAC_TX_PKTS_64OCTETS … #define XGMAC_TX_PKTS_65TO127OCTETS … #define XGMAC_TX_PKTS_128TO255OCTETS … #define XGMAC_TX_PKTS_256TO511OCTETS … #define XGMAC_TX_PKTS_512TO1023OCTETS … #define XGMAC_TX_PKTS_1024TO1518OCTETS … #define XGMAC_TX_PKTS_1519TOMAXOCTETS … #define XGMAC_TX_PKTS_1519TOMAXOCTETSOK … #define XGMAC_TX_PKTS_OVERSIZE … #define XGMAC_TX_PKTS_JABBER … #define XGMAC_TX_GOODPKTS … #define XGMAC_TX_GOODOCTETS … #define XGMAC_TX_TOTAL_PKTS … #define XGMAC_TX_TOTALOCTETS … #define XGMAC_TX_UNICASTPKTS … #define XGMAC_TX_MULTICASTPKTS … #define XGMAC_TX_BROADCASTPKTS … #define XGMAC_TX_PRI0PAUSEPKTS … #define XGMAC_TX_PRI1PAUSEPKTS … #define XGMAC_TX_PRI2PAUSEPKTS … #define XGMAC_TX_PRI3PAUSEPKTS … #define XGMAC_TX_PRI4PAUSEPKTS … #define XGMAC_TX_PRI5PAUSEPKTS … #define XGMAC_TX_PRI6PAUSEPKTS … #define XGMAC_TX_PRI7PAUSEPKTS … #define XGMAC_TX_MACCTRLPKTS … #define XGMAC_TX_1731PKTS … #define XGMAC_TX_1588PKTS … #define XGMAC_RX_FROMAPPGOODPKTS … #define XGMAC_RX_FROMAPPBADPKTS … #define XGMAC_TX_ERRALLPKTS … #define XGMAC_RX_PKTS_FRAGMENT … #define XGMAC_RX_PKTSUNDERSIZE … #define XGMAC_RX_PKTS_UNDERMIN … #define XGMAC_RX_PKTS_64OCTETS … #define XGMAC_RX_PKTS_65TO127OCTETS … #define XGMAC_RX_PKTS_128TO255OCTETS … #define XGMAC_RX_PKTS_256TO511OCTETS … #define XGMAC_RX_PKTS_512TO1023OCTETS … #define XGMAC_RX_PKTS_1024TO1518OCTETS … #define XGMAC_RX_PKTS_1519TOMAXOCTETS … #define XGMAC_RX_PKTS_1519TOMAXOCTETSOK … #define XGMAC_RX_PKTS_OVERSIZE … #define XGMAC_RX_PKTS_JABBER … #define XGMAC_RX_GOODPKTS … #define XGMAC_RX_GOODOCTETS … #define XGMAC_RX_TOTAL_PKTS … #define XGMAC_RX_TOTALOCTETS … #define XGMAC_RX_UNICASTPKTS … #define XGMAC_RX_MULTICASTPKTS … #define XGMAC_RX_BROADCASTPKTS … #define XGMAC_RX_PRI0PAUSEPKTS … #define XGMAC_RX_PRI1PAUSEPKTS … #define XGMAC_RX_PRI2PAUSEPKTS … #define XGMAC_RX_PRI3PAUSEPKTS … #define XGMAC_RX_PRI4PAUSEPKTS … #define XGMAC_RX_PRI5PAUSEPKTS … #define XGMAC_RX_PRI6PAUSEPKTS … #define XGMAC_RX_PRI7PAUSEPKTS … #define XGMAC_RX_MACCTRLPKTS … #define XGMAC_TX_SENDAPPGOODPKTS … #define XGMAC_TX_SENDAPPBADPKTS … #define XGMAC_RX_1731PKTS … #define XGMAC_RX_SYMBOLERRPKTS … #define XGMAC_RX_FCSERRPKTS … #define DSAF_SRAM_INIT_OVER_M … #define DSAFV2_SRAM_INIT_OVER_M … #define DSAF_SRAM_INIT_OVER_S … #define DSAF_CFG_EN_S … #define DSAF_CFG_TC_MODE_S … #define DSAF_CFG_CRC_EN_S … #define DSAF_CFG_SBM_INIT_S … #define DSAF_CFG_MIX_MODE_S … #define DSAF_CFG_STP_MODE_S … #define DSAF_CFG_LOCA_ADDR_EN_S … #define DSAFV2_CFG_VLAN_TAG_MODE_S … #define DSAF_CNT_CLR_CE_S … #define DSAF_SNAP_EN_S … #define HNS_DSAF_PFC_UNIT_CNT_FOR_XGE … #define HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000 … #define HNS_DSAF_PFC_UNIT_CNT_FOR_GE_2500 … #define DSAF_PFC_UNINT_CNT_M … #define DSAF_PFC_UNINT_CNT_S … #define DSAF_MAC_PAUSE_RX_EN_B … #define DSAF_PFC_PAUSE_RX_EN_B … #define DSAF_PFC_PAUSE_TX_EN_B … #define DSAF_PPE_QID_CFG_M … #define DSAF_PPE_QID_CFG_S … #define DSAF_SW_PORT_TYPE_M … #define DSAF_SW_PORT_TYPE_S … #define DSAF_STP_PORT_TYPE_M … #define DSAF_STP_PORT_TYPE_S … #define DSAF_INODE_IN_PORT_NUM_M … #define DSAF_INODE_IN_PORT_NUM_S … #define DSAFV2_INODE_IN_PORT1_NUM_M … #define DSAFV2_INODE_IN_PORT1_NUM_S … #define DSAFV2_INODE_IN_PORT2_NUM_M … #define DSAFV2_INODE_IN_PORT2_NUM_S … #define DSAFV2_INODE_IN_PORT3_NUM_M … #define DSAFV2_INODE_IN_PORT3_NUM_S … #define DSAFV2_INODE_IN_PORT4_NUM_M … #define DSAFV2_INODE_IN_PORT4_NUM_S … #define DSAFV2_INODE_IN_PORT5_NUM_M … #define DSAFV2_INODE_IN_PORT5_NUM_S … #define HNS_DSAF_I4TC_CFG … #define HNS_DSAF_I8TC_CFG … #define DSAF_SBM_CFG_SHCUT_EN_S … #define DSAF_SBM_CFG_EN_S … #define DSAF_SBM_CFG_MIB_EN_S … #define DSAF_SBM_CFG_ECC_INVERT_EN_S … #define DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S … #define DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M … #define DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S … #define DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M … #define DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S … #define DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M … #define DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S … #define DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M … #define DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S … #define DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M … #define DSAF_SBM_CFG2_SET_BUF_NUM_S … #define DSAF_SBM_CFG2_SET_BUF_NUM_M … #define DSAF_SBM_CFG2_RESET_BUF_NUM_S … #define DSAF_SBM_CFG2_RESET_BUF_NUM_M … #define DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S … #define DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M … #define DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S … #define DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M … #define DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S … #define DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M … #define DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S … #define DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M … #define DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S … #define DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M … #define DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S … #define DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M … #define DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S … #define DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M … #define DSAFV2_SBM_CFG2_SET_BUF_NUM_S … #define DSAFV2_SBM_CFG2_SET_BUF_NUM_M … #define DSAFV2_SBM_CFG2_RESET_BUF_NUM_S … #define DSAFV2_SBM_CFG2_RESET_BUF_NUM_M … #define DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S … #define DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M … #define DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S … #define DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M … #define DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S … #define DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M … #define DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S … #define DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M … #define DSAF_CHNS_MASK … #define DSAF_SBM_ROCEE_CFG_CRD_EN_B … #define SRST_TIME_INTERVAL … #define DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_S … #define DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_M … #define DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_S … #define DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_M … #define DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_S … #define DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_M … #define DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_S … #define DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_M … #define DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_S … #define DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_M … #define DSAF_TBL_TCAM_ADDR_S … #define DSAF_TBL_TCAM_ADDR_M … #define DSAF_TBL_LINE_ADDR_S … #define DSAF_TBL_LINE_ADDR_M … #define DSAF_TBL_MCAST_CFG4_VM128_112_S … #define DSAF_TBL_MCAST_CFG4_VM128_112_M … #define DSAF_TBL_MCAST_CFG4_ITEM_VLD_S … #define DSAF_TBL_MCAST_CFG4_OLD_EN_S … #define DSAF_TBL_MCAST_CFG0_XGE5_0_S … #define DSAF_TBL_MCAST_CFG0_XGE5_0_M … #define DSAF_TBL_MCAST_CFG0_VM25_0_S … #define DSAF_TBL_MCAST_CFG0_VM25_0_M … #define DSAF_TBL_UCAST_CFG1_OUT_PORT_S … #define DSAF_TBL_UCAST_CFG1_OUT_PORT_M … #define DSAF_TBL_UCAST_CFG1_DVC_S … #define DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S … #define DSAF_TBL_UCAST_CFG1_ITEM_VLD_S … #define DSAF_TBL_UCAST_CFG1_OLD_EN_S … #define DSAF_TBL_LINE_CFG_OUT_PORT_S … #define DSAF_TBL_LINE_CFG_OUT_PORT_M … #define DSAF_TBL_LINE_CFG_DVC_S … #define DSAF_TBL_LINE_CFG_MAC_DISCARD_S … #define DSAF_TBL_PUL_OLD_RSLT_RE_S … #define DSAF_TBL_PUL_MCAST_VLD_S … #define DSAF_TBL_PUL_TCAM_DATA_VLD_S … #define DSAF_TBL_PUL_UCAST_VLD_S … #define DSAF_TBL_PUL_LINE_VLD_S … #define DSAF_TBL_PUL_TCAM_LOAD_S … #define DSAF_TBL_PUL_LINE_LOAD_S … #define DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S … #define DSAF_TBL_DFX_UC_LKUP_NUM_EN_S … #define DSAF_TBL_DFX_MC_LKUP_NUM_EN_S … #define DSAF_TBL_DFX_BC_LKUP_NUM_EN_S … #define DSAF_TBL_DFX_RAM_ERR_INJECT_EN_S … #define DSAF_VOQ_BP_ALL_DOWNTHRD_S … #define DSAF_VOQ_BP_ALL_DOWNTHRD_M … #define DSAF_VOQ_BP_ALL_UPTHRD_S … #define DSAF_VOQ_BP_ALL_UPTHRD_M … #define DSAF_XGE_GE_WORK_MODE_S … #define DSAF_XGE_GE_LOOPBACK_S … #define DSAF_FC_XGE_TX_PAUSE_S … #define DSAF_REGS_XGE_CNT_CAR_S … #define PPE_CFG_QID_MODE_DEF_QID_S … #define PPE_CFG_QID_MODE_DEF_QID_M … #define PPE_CFG_QID_MODE_CF_QID_MODE_S … #define PPE_CFG_QID_MODE_CF_QID_MODE_M … #define PPEV2_CFG_RSS_TBL_4N0_S … #define PPEV2_CFG_RSS_TBL_4N0_M … #define PPEV2_CFG_RSS_TBL_4N1_S … #define PPEV2_CFG_RSS_TBL_4N1_M … #define PPEV2_CFG_RSS_TBL_4N2_S … #define PPEV2_CFG_RSS_TBL_4N2_M … #define PPEV2_CFG_RSS_TBL_4N3_S … #define PPEV2_CFG_RSS_TBL_4N3_M … #define DSAFV2_SERDES_LBK_EN_B … #define DSAFV2_SERDES_LBK_QID_S … #define DSAFV2_SERDES_LBK_QID_M … #define PPE_CNT_CLR_CE_B … #define PPE_CNT_CLR_SNAP_EN_B … #define PPE_INT_GAPTIME_B … #define PPE_INT_GAPTIME_M … #define PPE_COMMON_CNT_CLR_CE_B … #define PPE_COMMON_CNT_CLR_SNAP_EN_B … #define RCB_COM_TSO_MODE_B … #define RCB_COM_CFG_FNA_B … #define RCB_COM_CFG_FA_B … #define GMAC_DUPLEX_TYPE_B … #define GMAC_TX_WATER_LINE_MASK … #define GMAC_TX_WATER_LINE_SHIFT … #define GMAC_FC_TX_TIMER_S … #define GMAC_FC_TX_TIMER_M … #define GMAC_MAX_FRM_SIZE_S … #define GMAC_MAX_FRM_SIZE_M … #define GMAC_PORT_MODE_S … #define GMAC_PORT_MODE_M … #define GMAC_RGMII_1000M_DELAY_B … #define GMAC_MII_TX_EDGE_SEL_B … #define GMAC_FIFO_ERR_AUTO_RST_B … #define GMAC_DBG_CLK_LOS_MSK_B … #define GMAC_PORT_RX_EN_B … #define GMAC_PORT_TX_EN_B … #define GMAC_PAUSE_EN_RX_FDFC_B … #define GMAC_PAUSE_EN_TX_FDFC_B … #define GMAC_PAUSE_EN_TX_HDFC_B … #define GMAC_SHORT_RUNTS_THR_S … #define GMAC_SHORT_RUNTS_THR_M … #define GMAC_AN_NEG_STAT_FD_B … #define GMAC_AN_NEG_STAT_HD_B … #define GMAC_AN_NEG_STAT_RF1_DUPLIEX_B … #define GMAC_AN_NEG_STAT_RF2_B … #define GMAC_AN_NEG_STAT_NP_LNK_OK_B … #define GMAC_AN_NEG_STAT_RX_SYNC_OK_B … #define GMAC_AN_NEG_STAT_AN_DONE_B … #define GMAC_AN_NEG_STAT_PS_S … #define GMAC_AN_NEG_STAT_PS_M … #define GMAC_AN_NEG_STAT_SPEED_S … #define GMAC_AN_NEG_STAT_SPEED_M … #define GMAC_TX_AN_EN_B … #define GMAC_TX_CRC_ADD_B … #define GMAC_TX_PAD_EN_B … #define GMAC_LINE_LOOPBACK_B … #define GMAC_LP_REG_CF_EXT_DRV_LP_B … #define GMAC_LP_REG_CF2MI_LP_EN_B … #define GMAC_MODE_CHANGE_EB_B … #define GMAC_UC_MATCH_EN_B … #define GMAC_ADDR_EN_B … #define GMAC_RECV_CTRL_STRIP_PAD_EN_B … #define GMAC_RECV_CTRL_RUNT_PKT_EN_B … #define GMAC_TX_LOOP_PKT_HIG_PRI_B … #define GMAC_TX_LOOP_PKT_EN_B … #define XGMAC_PORT_MODE_TX_S … #define XGMAC_PORT_MODE_TX_M … #define XGMAC_PORT_MODE_TX_40G_B … #define XGMAC_PORT_MODE_RX_S … #define XGMAC_PORT_MODE_RX_M … #define XGMAC_PORT_MODE_RX_40G_B … #define XGMAC_ENABLE_TX_B … #define XGMAC_ENABLE_RX_B … #define XGMAC_UNIDIR_EN_B … #define XGMAC_RF_TX_EN_B … #define XGMAC_LF_RF_INSERT_S … #define XGMAC_LF_RF_INSERT_M … #define XGMAC_CTL_TX_FCS_B … #define XGMAC_CTL_TX_PAD_B … #define XGMAC_CTL_TX_PREAMBLE_TRANS_B … #define XGMAC_CTL_TX_UNDER_MIN_ERR_B … #define XGMAC_CTL_TX_TRUNCATE_B … #define XGMAC_CTL_TX_1588_B … #define XGMAC_CTL_TX_1731_B … #define XGMAC_CTL_TX_PFC_B … #define XGMAC_CTL_RX_FCS_B … #define XGMAC_CTL_RX_FCS_STRIP_B … #define XGMAC_CTL_RX_PREAMBLE_TRANS_B … #define XGMAC_CTL_RX_UNDER_MIN_ERR_B … #define XGMAC_CTL_RX_TRUNCATE_B … #define XGMAC_CTL_RX_1588_B … #define XGMAC_CTL_RX_1731_B … #define XGMAC_CTL_RX_PFC_B … #define XGMAC_PMA_FEC_CTL_TX_B … #define XGMAC_PMA_FEC_CTL_RX_B … #define XGMAC_PMA_FEC_CTL_ERR_EN … #define XGMAC_PMA_FEC_CTL_ERR_SH … #define XGMAC_PAUSE_CTL_TX_B … #define XGMAC_PAUSE_CTL_RX_B … #define XGMAC_PAUSE_CTL_RSP_MODE_B … #define XGMAC_PAUSE_CTL_TX_XOFF_B … static inline void dsaf_write_reg(u8 __iomem *base, u32 reg, u32 value) { … } #define dsaf_write_dev(a, reg, value) … static inline u32 dsaf_read_reg(u8 __iomem *base, u32 reg) { … } static inline void dsaf_write_syscon(struct regmap *base, u32 reg, u32 value) { … } static inline int dsaf_read_syscon(struct regmap *base, u32 reg, u32 *val) { … } #define dsaf_read_dev(a, reg) … #define dsaf_set_field(origin, mask, shift, val) … #define dsaf_set_bit(origin, shift, val) … static inline void dsaf_set_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift, u32 val) { … } #define dsaf_set_dev_field(dev, reg, mask, shift, val) … #define dsaf_set_dev_bit(dev, reg, bit, val) … #define dsaf_get_field(origin, mask, shift) … #define dsaf_get_bit(origin, shift) … static inline u32 dsaf_get_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift) { … } #define dsaf_get_dev_field(dev, reg, mask, shift) … #define dsaf_get_dev_bit(dev, reg, bit) … #define dsaf_write_b(addr, data) … #define dsaf_read_b(addr) … #define hns_mac_reg_read64(drv, offset) … #endif /* _DSAF_REG_H */
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