#ifndef __HNAE3_H
#define __HNAE3_H
#include <linux/acpi.h>
#include <linux/dcbnl.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/ethtool.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/pci.h>
#include <linux/pkt_sched.h>
#include <linux/types.h>
#include <linux/bitmap.h>
#include <net/pkt_cls.h>
#include <net/pkt_sched.h>
#define HNAE3_MOD_VERSION …
#define HNAE3_MIN_VECTOR_NUM …
#define HNAE3_DEVICE_VERSION_V1 …
#define HNAE3_DEVICE_VERSION_V2 …
#define HNAE3_DEVICE_VERSION_V3 …
#define HNAE3_PCI_REVISION_BIT_SIZE …
#define HNAE3_DEV_ID_GE …
#define HNAE3_DEV_ID_25GE …
#define HNAE3_DEV_ID_25GE_RDMA …
#define HNAE3_DEV_ID_25GE_RDMA_MACSEC …
#define HNAE3_DEV_ID_50GE_RDMA …
#define HNAE3_DEV_ID_50GE_RDMA_MACSEC …
#define HNAE3_DEV_ID_100G_RDMA_MACSEC …
#define HNAE3_DEV_ID_200G_RDMA …
#define HNAE3_DEV_ID_VF …
#define HNAE3_DEV_ID_RDMA_DCB_PFC_VF …
#define HNAE3_CLASS_NAME_SIZE …
#define HNAE3_DEV_INITED_B …
#define HNAE3_DEV_SUPPORT_ROCE_B …
#define HNAE3_DEV_SUPPORT_DCB_B …
#define HNAE3_KNIC_CLIENT_INITED_B …
#define HNAE3_UNIC_CLIENT_INITED_B …
#define HNAE3_ROCE_CLIENT_INITED_B …
#define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS …
#define hnae3_dev_roce_supported(hdev) …
#define hnae3_dev_dcb_supported(hdev) …
enum HNAE3_DEV_CAP_BITS { … };
#define hnae3_ae_dev_fd_supported(ae_dev) …
#define hnae3_ae_dev_gro_supported(ae_dev) …
#define hnae3_dev_fec_supported(hdev) …
#define hnae3_dev_udp_gso_supported(hdev) …
#define hnae3_dev_qb_supported(hdev) …
#define hnae3_dev_fd_forward_tc_supported(hdev) …
#define hnae3_dev_ptp_supported(hdev) …
#define hnae3_dev_int_ql_supported(hdev) …
#define hnae3_dev_hw_csum_supported(hdev) …
#define hnae3_dev_tx_push_supported(hdev) …
#define hnae3_dev_phy_imp_supported(hdev) …
#define hnae3_dev_ras_imp_supported(hdev) …
#define hnae3_dev_tqp_txrx_indep_supported(hdev) …
#define hnae3_dev_hw_pad_supported(hdev) …
#define hnae3_dev_stash_supported(hdev) …
#define hnae3_dev_pause_supported(hdev) …
#define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) …
#define hnae3_ae_dev_rxd_adv_layout_supported(ae_dev) …
#define hnae3_ae_dev_mc_mac_mng_supported(ae_dev) …
#define hnae3_ae_dev_cq_supported(ae_dev) …
#define hnae3_ae_dev_fec_stats_supported(ae_dev) …
#define hnae3_ae_dev_lane_num_supported(ae_dev) …
#define hnae3_ae_dev_wol_supported(ae_dev) …
#define hnae3_ae_dev_tm_flush_supported(hdev) …
#define hnae3_ae_dev_vf_fault_supported(ae_dev) …
#define hnae3_ae_dev_gen_reg_dfx_supported(hdev) …
enum HNAE3_PF_CAP_BITS { … };
#define ring_ptr_move_fw(ring, p) …
#define ring_ptr_move_bw(ring, p) …
struct hnae3_handle;
struct hnae3_queue { … };
struct hns3_mac_stats { … };
enum hnae3_loop { … };
enum hnae3_client_type { … };
enum hnae3_media_type { … };
enum hnae3_module_type { … };
enum hnae3_fec_mode { … };
enum hnae3_reset_notify_type { … };
enum hnae3_hw_error_type { … };
enum hnae3_reset_type { … };
enum hnae3_port_base_vlan_state { … };
enum hnae3_dbg_cmd { … };
enum hnae3_tc_map_mode { … };
struct hnae3_vector_info { … };
#define HNAE3_RING_TYPE_B …
#define HNAE3_RING_TYPE_TX …
#define HNAE3_RING_TYPE_RX …
#define HNAE3_RING_GL_IDX_S …
#define HNAE3_RING_GL_IDX_M …
#define HNAE3_RING_GL_RX …
#define HNAE3_RING_GL_TX …
#define HNAE3_FW_VERSION_BYTE3_SHIFT …
#define HNAE3_FW_VERSION_BYTE3_MASK …
#define HNAE3_FW_VERSION_BYTE2_SHIFT …
#define HNAE3_FW_VERSION_BYTE2_MASK …
#define HNAE3_FW_VERSION_BYTE1_SHIFT …
#define HNAE3_FW_VERSION_BYTE1_MASK …
#define HNAE3_FW_VERSION_BYTE0_SHIFT …
#define HNAE3_FW_VERSION_BYTE0_MASK …
#define HNAE3_SCC_VERSION_BYTE3_SHIFT …
#define HNAE3_SCC_VERSION_BYTE3_MASK …
#define HNAE3_SCC_VERSION_BYTE2_SHIFT …
#define HNAE3_SCC_VERSION_BYTE2_MASK …
#define HNAE3_SCC_VERSION_BYTE1_SHIFT …
#define HNAE3_SCC_VERSION_BYTE1_MASK …
#define HNAE3_SCC_VERSION_BYTE0_SHIFT …
#define HNAE3_SCC_VERSION_BYTE0_MASK …
struct hnae3_ring_chain_node { … };
#define HNAE3_IS_TX_RING(node) …
struct hnae3_dev_specs { … };
struct hnae3_client_ops { … };
#define HNAE3_CLIENT_NAME_LENGTH …
struct hnae3_client { … };
#define HNAE3_DEV_CAPS_MAX_NUM …
struct hnae3_ae_dev { … };
struct hnae3_ae_ops { … };
struct hnae3_dcb_ops { … };
struct hnae3_ae_algo { … };
#define HNAE3_INT_NAME_LEN …
#define HNAE3_ITR_COUNTDOWN_START …
#define HNAE3_MAX_TC …
#define HNAE3_MAX_USER_PRIO …
struct hnae3_tc_info { … };
#define HNAE3_MAX_DSCP …
#define HNAE3_PRIO_ID_INVALID …
struct hnae3_knic_private_info { … };
struct hnae3_roce_private_info { … };
#define HNAE3_SUPPORT_APP_LOOPBACK …
#define HNAE3_SUPPORT_PHY_LOOPBACK …
#define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK …
#define HNAE3_SUPPORT_VF …
#define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK …
#define HNAE3_SUPPORT_EXTERNAL_LOOPBACK …
#define HNAE3_USER_UPE …
#define HNAE3_USER_MPE …
#define HNAE3_BPE …
#define HNAE3_OVERFLOW_UPE …
#define HNAE3_OVERFLOW_MPE …
#define HNAE3_UPE …
#define HNAE3_MPE …
enum hnae3_pflag { … };
struct hnae3_handle { … };
#define hnae3_set_field(origin, mask, shift, val) …
#define hnae3_get_field(origin, mask, shift) …
#define hnae3_set_bit(origin, shift, val) …
#define hnae3_get_bit(origin, shift) …
#define HNAE3_FORMAT_MAC_ADDR_LEN …
#define HNAE3_FORMAT_MAC_ADDR_OFFSET_0 …
#define HNAE3_FORMAT_MAC_ADDR_OFFSET_4 …
#define HNAE3_FORMAT_MAC_ADDR_OFFSET_5 …
static inline void hnae3_format_mac_addr(char *format_mac_addr,
const u8 *mac_addr)
{ … }
int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev);
void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev);
void hnae3_unregister_ae_algo_prepare(struct hnae3_ae_algo *ae_algo);
void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo);
void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo);
void hnae3_unregister_client(struct hnae3_client *client);
int hnae3_register_client(struct hnae3_client *client);
void hnae3_set_client_init_flag(struct hnae3_client *client,
struct hnae3_ae_dev *ae_dev,
unsigned int inited);
#endif