linux/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h

/* SPDX-License-Identifier: GPL-2.0+ */
// Copyright (c) 2021-2021 Hisilicon Limited.

#ifndef __HCLGE_COMM_CMD_H
#define __HCLGE_COMM_CMD_H
#include <linux/types.h>

#include "hnae3.h"

#define HCLGE_COMM_CMD_FLAG_IN …
#define HCLGE_COMM_CMD_FLAG_NEXT …
#define HCLGE_COMM_CMD_FLAG_WR …
#define HCLGE_COMM_CMD_FLAG_NO_INTR …

#define HCLGE_COMM_SEND_SYNC(flag) …

#define HCLGE_COMM_LINK_EVENT_REPORT_EN_B …
#define HCLGE_COMM_NCSI_ERROR_REPORT_EN_B …
#define HCLGE_COMM_PHY_IMP_EN_B …
#define HCLGE_COMM_MAC_STATS_EXT_EN_B …
#define HCLGE_COMM_SYNC_RX_RING_HEAD_EN_B …
#define HCLGE_COMM_LLRS_FEC_EN_B …

#define hclge_comm_dev_phy_imp_supported(ae_dev) …

#define HCLGE_COMM_TYPE_CRQ …
#define HCLGE_COMM_TYPE_CSQ …

#define HCLGE_COMM_CMDQ_CLEAR_WAIT_TIME …

/* bar registers for cmdq */
#define HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG …
#define HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG …
#define HCLGE_COMM_NIC_CSQ_DEPTH_REG …
#define HCLGE_COMM_NIC_CSQ_TAIL_REG …
#define HCLGE_COMM_NIC_CSQ_HEAD_REG …
#define HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG …
#define HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG …
#define HCLGE_COMM_NIC_CRQ_DEPTH_REG …
#define HCLGE_COMM_NIC_CRQ_TAIL_REG …
#define HCLGE_COMM_NIC_CRQ_HEAD_REG …
/* Vector0 interrupt CMDQ event source register(RW) */
#define HCLGE_COMM_VECTOR0_CMDQ_SRC_REG …
/* Vector0 interrupt CMDQ event status register(RO) */
#define HCLGE_COMM_VECTOR0_CMDQ_STATE_REG …
#define HCLGE_COMM_CMDQ_INTR_EN_REG …
#define HCLGE_COMM_CMDQ_INTR_GEN_REG …
#define HCLGE_COMM_CMDQ_INTR_STS_REG …

/* this bit indicates that the driver is ready for hardware reset */
#define HCLGE_COMM_NIC_SW_RST_RDY_B …
#define HCLGE_COMM_NIC_SW_RST_RDY …
#define HCLGE_COMM_NIC_CMQ_DESC_NUM_S …
#define HCLGE_COMM_NIC_CMQ_DESC_NUM …
#define HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT …
#define HCLGE_COMM_CMDQ_CFG_RST_TIMEOUT …

enum hclge_opcode_type { … };

enum hclge_comm_cmd_return_status { … };

enum HCLGE_COMM_CAP_BITS { … };

enum HCLGE_COMM_API_CAP_BITS { … };

/* capabilities bits map between imp firmware and local driver */
struct hclge_comm_caps_bit_map { … };

struct hclge_cmdq_tx_timeout_map { … };

struct hclge_comm_firmware_compat_cmd { … };

enum hclge_comm_cmd_state { … };

struct hclge_comm_errcode { … };

#define HCLGE_COMM_QUERY_CAP_LENGTH …
struct hclge_comm_query_version_cmd { … };

struct hclge_comm_query_scc_cmd { … };

#define HCLGE_DESC_DATA_LEN …
struct hclge_desc { … };

struct hclge_comm_cmq_ring { … };

enum hclge_comm_cmd_status { … };

struct hclge_comm_hw;
struct hclge_comm_cmq_ops { … };

struct hclge_comm_cmq { … };

struct hclge_comm_hw { … };

static inline void hclge_comm_write_reg(void __iomem *base, u32 reg, u32 value)
{ … }

static inline u32 hclge_comm_read_reg(u8 __iomem *base, u32 reg)
{ … }

#define hclge_comm_write_dev(a, reg, value) …
#define hclge_comm_read_dev(a, reg) …

void hclge_comm_cmd_init_regs(struct hclge_comm_hw *hw);
int hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev,
						struct hclge_comm_hw *hw,
						u32 *fw_version, bool is_pf);
int hclge_comm_alloc_cmd_queue(struct hclge_comm_hw *hw, int ring_type);
int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,
			int num);
void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev,
				      struct hclge_comm_hw *hw, bool en);
void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring);
void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc,
				     enum hclge_opcode_type opcode,
				     bool is_read);
void hclge_comm_cmd_uninit(struct hnae3_ae_dev *ae_dev,
			   struct hclge_comm_hw *hw);
int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw);
int hclge_comm_cmd_init(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw,
			u32 *fw_version, bool is_pf,
			unsigned long reset_pending);
void hclge_comm_cmd_init_ops(struct hclge_comm_hw *hw,
			     const struct hclge_comm_cmq_ops *ops);
#endif