/* SPDX-License-Identifier: GPL-2.0+ */ // Copyright (c) 2016-2017 Hisilicon Limited. #ifndef __HCLGE_TM_H #define __HCLGE_TM_H #include <linux/types.h> #include "hnae3.h" struct hclge_dev; struct hclge_vport; enum hclge_opcode_type; /* MAC Pause */ #define HCLGE_TX_MAC_PAUSE_EN_MSK … #define HCLGE_RX_MAC_PAUSE_EN_MSK … #define HCLGE_TM_PORT_BASE_MODE_MSK … #define HCLGE_DEFAULT_PAUSE_TRANS_GAP … #define HCLGE_DEFAULT_PAUSE_TRANS_TIME … /* SP or DWRR */ #define HCLGE_TM_TX_SCHD_DWRR_MSK … #define HCLGE_TM_TX_SCHD_SP_MSK … #define HCLGE_ETHER_MAX_RATE … #define HCLGE_TM_PF_MAX_PRI_NUM … #define HCLGE_TM_PF_MAX_QSET_NUM … #define HCLGE_DSCP_MAP_TC_BD_NUM … #define HCLGE_DSCP_TC_SHIFT(n) … #define HCLGE_TM_FLUSH_TIME_MS … #define HCLGE_TM_FLUSH_EN_MSK … struct hclge_pg_to_pri_link_cmd { … }; struct hclge_qs_to_pri_link_cmd { … }; struct hclge_nq_to_qs_link_cmd { … }; struct hclge_tqp_tx_queue_tc_cmd { … }; struct hclge_pg_weight_cmd { … }; struct hclge_priority_weight_cmd { … }; struct hclge_pri_sch_mode_cfg_cmd { … }; struct hclge_qs_sch_mode_cfg_cmd { … }; struct hclge_qs_weight_cmd { … }; struct hclge_ets_tc_weight_cmd { … }; #define HCLGE_TM_SHAP_IR_B_MSK … #define HCLGE_TM_SHAP_IR_B_LSH … #define HCLGE_TM_SHAP_IR_U_MSK … #define HCLGE_TM_SHAP_IR_U_LSH … #define HCLGE_TM_SHAP_IR_S_MSK … #define HCLGE_TM_SHAP_IR_S_LSH … #define HCLGE_TM_SHAP_BS_B_MSK … #define HCLGE_TM_SHAP_BS_B_LSH … #define HCLGE_TM_SHAP_BS_S_MSK … #define HCLGE_TM_SHAP_BS_S_LSH … enum hclge_shap_bucket { … }; /* set bit HCLGE_TM_RATE_VLD to 1 means use 'rate' to config shaping */ #define HCLGE_TM_RATE_VLD … struct hclge_pri_shapping_cmd { … }; struct hclge_pg_shapping_cmd { … }; struct hclge_qs_shapping_cmd { … }; #define HCLGE_BP_GRP_NUM … #define HCLGE_BP_SUB_GRP_ID_S … #define HCLGE_BP_SUB_GRP_ID_M … #define HCLGE_BP_GRP_ID_S … #define HCLGE_BP_GRP_ID_M … #define HCLGE_BP_EXT_GRP_NUM … #define HCLGE_BP_EXT_GRP_ID_S … #define HCLGE_BP_EXT_GRP_ID_M … struct hclge_bp_to_qs_map_cmd { … }; #define HCLGE_PFC_DISABLE … #define HCLGE_PFC_TX_RX_DISABLE … struct hclge_pfc_en_cmd { … }; struct hclge_cfg_pause_param_cmd { … }; struct hclge_pfc_stats_cmd { … }; struct hclge_port_shapping_cmd { … }; struct hclge_shaper_ir_para { … }; struct hclge_tm_nodes_cmd { … }; struct hclge_tm_shaper_para { … }; #define hclge_tm_set_field(dest, string, val) … #define hclge_tm_get_field(src, string) … int hclge_tm_schd_init(struct hclge_dev *hdev); int hclge_tm_vport_map_update(struct hclge_dev *hdev); int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init); int hclge_tm_schd_setup_hw(struct hclge_dev *hdev); void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc); void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc); void hclge_tm_pfc_info_update(struct hclge_dev *hdev); int hclge_tm_dwrr_cfg(struct hclge_dev *hdev); int hclge_tm_init_hw(struct hclge_dev *hdev, bool init); int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap, u8 pfc_bitmap); int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx); int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr); int hclge_mac_pause_setup_hw(struct hclge_dev *hdev); void hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats); void hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats); int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate); int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev); int hclge_tm_get_qset_num(struct hclge_dev *hdev, u16 *qset_num); int hclge_tm_get_pri_num(struct hclge_dev *hdev, u8 *pri_num); int hclge_tm_get_qset_map_pri(struct hclge_dev *hdev, u16 qset_id, u8 *priority, u8 *link_vld); int hclge_tm_get_qset_sch_mode(struct hclge_dev *hdev, u16 qset_id, u8 *mode); int hclge_tm_get_qset_weight(struct hclge_dev *hdev, u16 qset_id, u8 *weight); int hclge_tm_get_qset_shaper(struct hclge_dev *hdev, u16 qset_id, struct hclge_tm_shaper_para *para); int hclge_tm_get_pri_sch_mode(struct hclge_dev *hdev, u8 pri_id, u8 *mode); int hclge_tm_get_pri_weight(struct hclge_dev *hdev, u8 pri_id, u8 *weight); int hclge_tm_get_pri_shaper(struct hclge_dev *hdev, u8 pri_id, enum hclge_opcode_type cmd, struct hclge_tm_shaper_para *para); int hclge_tm_get_q_to_qs_map(struct hclge_dev *hdev, u16 q_id, u16 *qset_id); int hclge_tm_get_q_to_tc(struct hclge_dev *hdev, u16 q_id, u8 *tc_id); int hclge_tm_get_pg_to_pri_map(struct hclge_dev *hdev, u8 pg_id, u8 *pri_bit_map); int hclge_tm_get_pg_weight(struct hclge_dev *hdev, u8 pg_id, u8 *weight); int hclge_tm_get_pg_sch_mode(struct hclge_dev *hdev, u8 pg_id, u8 *mode); int hclge_tm_get_pg_shaper(struct hclge_dev *hdev, u8 pg_id, enum hclge_opcode_type cmd, struct hclge_tm_shaper_para *para); int hclge_tm_get_port_shaper(struct hclge_dev *hdev, struct hclge_tm_shaper_para *para); int hclge_up_to_tc_map(struct hclge_dev *hdev); int hclge_dscp_to_tc_map(struct hclge_dev *hdev); int hclge_tm_flush_cfg(struct hclge_dev *hdev, bool enable); void hclge_reset_tc_config(struct hclge_dev *hdev); #endif
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