hclge_err.h | Explore in Territory

/* SPDX-License-Identifier: GPL-2.0+ */
/*  Copyright (c) 2016-2017 Hisilicon Limited. */

#ifndef __HCLGE_ERR_H
#define __HCLGE_ERR_H

#include "hclge_main.h"
#include "hclge_debugfs.h"
#include "hnae3.h"

#define HCLGE_MPF_RAS_INT_MIN_BD_NUM …
#define HCLGE_PF_RAS_INT_MIN_BD_NUM …
#define HCLGE_MPF_MSIX_INT_MIN_BD_NUM …
#define HCLGE_PF_MSIX_INT_MIN_BD_NUM …

#define HCLGE_RAS_PF_OTHER_INT_STS_REG …
#define HCLGE_RAS_REG_NFE_MASK …
#define HCLGE_RAS_REG_ROCEE_ERR_MASK …
#define HCLGE_RAS_REG_ERR_MASK …

#define HCLGE_VECTOR0_REG_MSIX_MASK …

#define HCLGE_IMP_TCM_ECC_ERR_INT_EN …
#define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK …
#define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN …
#define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK …
#define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN …
#define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK …
#define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN …
#define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK …
#define HCLGE_IMP_RD_POISON_ERR_INT_EN …
#define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK …
#define HCLGE_TQP_ECC_ERR_INT_EN …
#define HCLGE_TQP_ECC_ERR_INT_EN_MASK …
#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK …
#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN …
#define HCLGE_IGU_ERR_INT_EN …
#define HCLGE_IGU_ERR_INT_TYPE …
#define HCLGE_IGU_ERR_INT_EN_MASK …
#define HCLGE_IGU_TNL_ERR_INT_EN …
#define HCLGE_IGU_TNL_ERR_INT_EN_MASK …
#define HCLGE_PPP_MPF_ECC_ERR_INT0_EN …
#define HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK …
#define HCLGE_PPP_MPF_ECC_ERR_INT1_EN …
#define HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK …
#define HCLGE_PPP_PF_ERR_INT_EN …
#define HCLGE_PPP_PF_ERR_INT_EN_MASK …
#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN …
#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK …
#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN …
#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK …
#define HCLGE_TM_SCH_ECC_ERR_INT_EN …
#define HCLGE_TM_QCN_ERR_INT_TYPE …
#define HCLGE_TM_QCN_FIFO_INT_EN …
#define HCLGE_TM_QCN_MEM_ERR_INT_EN …
#define HCLGE_NCSI_ERR_INT_EN …
#define HCLGE_NCSI_ERR_INT_TYPE …
#define HCLGE_MAC_COMMON_ERR_INT_EN …
#define HCLGE_MAC_COMMON_ERR_INT_EN_MASK …
#define HCLGE_MAC_TNL_INT_EN …
#define HCLGE_MAC_TNL_INT_EN_MASK …
#define HCLGE_MAC_TNL_INT_CLR …
#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN …
#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK …
#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN …
#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK …
#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN …
#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK …
#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2 …
#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK …
#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN …
#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK …
#define HCLGE_PPU_PF_ABNORMAL_INT_EN …
#define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK …
#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN …
#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK …
#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN …
#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK …
#define HCLGE_SSU_BIT32_ECC_ERR_INT_EN …
#define HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK …
#define HCLGE_SSU_COMMON_INT_EN …
#define HCLGE_SSU_COMMON_INT_EN_MASK …
#define HCLGE_SSU_PORT_BASED_ERR_INT_EN …
#define HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK …
#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN …
#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK …

#define HCLGE_SSU_COMMON_ERR_INT_MASK …
#define HCLGE_SSU_PORT_INT_MSIX_MASK …
#define HCLGE_IGU_INT_MASK …
#define HCLGE_IGU_EGU_TNL_INT_MASK …
#define HCLGE_PPP_MPF_INT_ST3_MASK …
#define HCLGE_PPU_MPF_INT_ST3_MASK …
#define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK …
#define HCLGE_PPU_PF_INT_RAS_MASK …
#define HCLGE_PPU_PF_INT_MSIX_MASK …
#define HCLGE_PPU_PF_OVER_8BD_ERR_MASK …
#define HCLGE_QCN_FIFO_INT_MASK …
#define HCLGE_QCN_ECC_INT_MASK …
#define HCLGE_NCSI_ECC_INT_MASK …

#define HCLGE_ROCEE_RAS_NFE_INT_EN …
#define HCLGE_ROCEE_RAS_CE_INT_EN …
#define HCLGE_ROCEE_RAS_NFE_INT_EN_MASK …
#define HCLGE_ROCEE_RAS_CE_INT_EN_MASK …
#define HCLGE_ROCEE_RERR_INT_MASK …
#define HCLGE_ROCEE_BERR_INT_MASK …
#define HCLGE_ROCEE_AXI_ERR_INT_MASK …
#define HCLGE_ROCEE_ECC_INT_MASK …
#define HCLGE_ROCEE_OVF_INT_MASK …
#define HCLGE_ROCEE_OVF_ERR_INT_MASK …
#define HCLGE_ROCEE_OVF_ERR_TYPE_MASK …

#define HCLGE_DESC_DATA_MAX …
#define HCLGE_REG_NUM_MAX …
#define HCLGE_DESC_NO_DATA_LEN …

#define HCLGE_BD_NUM_SSU_REG_0 …
#define HCLGE_BD_NUM_SSU_REG_1 …
#define HCLGE_BD_NUM_RPU_REG_0 …
#define HCLGE_BD_NUM_RPU_REG_1 …
#define HCLGE_BD_NUM_IGU_EGU_REG …
#define HCLGE_BD_NUM_GEN_REG …
#define HCLGE_MOD_REG_INFO_LEN_MAX …
#define HCLGE_MOD_REG_EXTRA_LEN …
#define HCLGE_MOD_REG_VALUE_LEN …
#define HCLGE_MOD_REG_GROUP_MAX_SIZE …
#define HCLGE_MOD_MSG_PARA_ARRAY_MAX_SIZE …

enum hclge_err_int_type { … };

enum hclge_mod_name_list { … };

enum hclge_err_type_list { … };

struct hclge_hw_blk { … };

struct hclge_hw_error { … };

struct hclge_hw_module_id { … };

struct hclge_hw_type_id { … };

struct hclge_sum_err_info { … };

struct hclge_mod_err_info { … };

struct hclge_type_reg_err_info { … };

struct hclge_mod_reg_info { … };

/* This structure defines cmdq used to query the hardware module debug
 * regisgers.
 */
struct hclge_mod_reg_common_msg { … };

int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en);
int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state);
int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en);
void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev);
bool hclge_find_error_source(struct hclge_dev *hdev);
void hclge_handle_occurred_error(struct hclge_dev *hdev);
pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev);
int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
			       unsigned long *reset_requests);
int hclge_handle_error_info_log(struct hnae3_ae_dev *ae_dev);
int hclge_handle_mac_tnl(struct hclge_dev *hdev);
int hclge_handle_vf_queue_err_ras(struct hclge_dev *hdev);
#endif
linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
