linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h

/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (c) 2018-2019 Hisilicon Limited. */

#ifndef __HCLGE_DEBUGFS_H
#define __HCLGE_DEBUGFS_H

#include <linux/etherdevice.h>
#include "hclge_cmd.h"

#define HCLGE_DBG_MNG_TBL_MAX …

#define HCLGE_DBG_MNG_VLAN_MASK_B …
#define HCLGE_DBG_MNG_MAC_MASK_B …
#define HCLGE_DBG_MNG_ETHER_MASK_B …
#define HCLGE_DBG_MNG_E_TYPE_B …
#define HCLGE_DBG_MNG_DROP_B …
#define HCLGE_DBG_MNG_VLAN_TAG …
#define HCLGE_DBG_MNG_PF_ID …
#define HCLGE_DBG_MNG_VF_ID …

/* Get DFX BD number offset */
#define HCLGE_DBG_DFX_BIOS_OFFSET …
#define HCLGE_DBG_DFX_SSU_0_OFFSET …
#define HCLGE_DBG_DFX_SSU_1_OFFSET …
#define HCLGE_DBG_DFX_IGU_OFFSET …
#define HCLGE_DBG_DFX_RPU_0_OFFSET …

#define HCLGE_DBG_DFX_RPU_1_OFFSET …
#define HCLGE_DBG_DFX_NCSI_OFFSET …
#define HCLGE_DBG_DFX_RTC_OFFSET …
#define HCLGE_DBG_DFX_PPP_OFFSET …
#define HCLGE_DBG_DFX_RCB_OFFSET …
#define HCLGE_DBG_DFX_TQP_OFFSET …

#define HCLGE_DBG_DFX_SSU_2_OFFSET …

struct hclge_qos_pri_map_cmd { … };

struct hclge_dbg_bitmap_cmd { … };

struct hclge_dbg_reg_common_msg { … };

struct hclge_dbg_tcam_msg { … };

#define HCLGE_DBG_MAX_DFX_MSG_LEN …
struct hclge_dbg_dfx_message { … };

#define HCLGE_DBG_MAC_REG_TYPE_LEN …
struct hclge_dbg_reg_type_info { … };

struct hclge_dbg_func { … };

struct hclge_dbg_status_dfx_info { … };

#define HCLGE_DBG_INFO_LEN …
#define HCLGE_DBG_VLAN_FLTR_INFO_LEN …
#define HCLGE_DBG_VLAN_OFFLOAD_INFO_LEN …
#define HCLGE_DBG_ID_LEN …
#define HCLGE_DBG_ITEM_NAME_LEN …
#define HCLGE_DBG_DATA_STR_LEN …
#define HCLGE_DBG_TM_INFO_LEN …

#define HCLGE_BILLION_NANO_SECONDS …

struct hclge_dbg_item { … };

struct hclge_dbg_vlan_cfg { … };

int hclge_dbg_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc_src,
		       int index, int bd_num, enum hclge_opcode_type cmd);

#endif