/* SPDX-License-Identifier: GPL-2.0 */ // Copyright (c) 2017 Cadence // Cadence PCIe controller driver. // Author: Cyrille Pitchen <[email protected]> #ifndef _PCIE_CADENCE_H #define _PCIE_CADENCE_H #include <linux/kernel.h> #include <linux/pci.h> #include <linux/pci-epf.h> #include <linux/phy/phy.h> /* Parameters for the waiting for link up routine */ #define LINK_WAIT_MAX_RETRIES … #define LINK_WAIT_USLEEP_MIN … #define LINK_WAIT_USLEEP_MAX … /* * Local Management Registers */ #define CDNS_PCIE_LM_BASE … /* Vendor ID Register */ #define CDNS_PCIE_LM_ID … #define CDNS_PCIE_LM_ID_VENDOR_MASK … #define CDNS_PCIE_LM_ID_VENDOR_SHIFT … #define CDNS_PCIE_LM_ID_VENDOR(vid) … #define CDNS_PCIE_LM_ID_SUBSYS_MASK … #define CDNS_PCIE_LM_ID_SUBSYS_SHIFT … #define CDNS_PCIE_LM_ID_SUBSYS(sub) … /* Root Port Requester ID Register */ #define CDNS_PCIE_LM_RP_RID … #define CDNS_PCIE_LM_RP_RID_MASK … #define CDNS_PCIE_LM_RP_RID_SHIFT … #define CDNS_PCIE_LM_RP_RID_(rid) … /* Endpoint Bus and Device Number Register */ #define CDNS_PCIE_LM_EP_ID … #define CDNS_PCIE_LM_EP_ID_DEV_MASK … #define CDNS_PCIE_LM_EP_ID_DEV_SHIFT … #define CDNS_PCIE_LM_EP_ID_BUS_MASK … #define CDNS_PCIE_LM_EP_ID_BUS_SHIFT … /* Endpoint Function f BAR b Configuration Registers */ #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) … #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) … #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) … #define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) … #define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) … #define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) … #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) … #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) … #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) … #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) … /* Endpoint Function Configuration Register */ #define CDNS_PCIE_LM_EP_FUNC_CFG … /* Root Complex BAR Configuration Register */ #define CDNS_PCIE_LM_RC_BAR_CFG … #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK … #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) … #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK … #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) … #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK … #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) … #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK … #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) … #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE … #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS … #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS … #define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE … #define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS … #define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS … #define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE … /* BAR control values applicable to both Endpoint Function and Root Complex */ #define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED … #define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS … #define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS … #define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS … #define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS … #define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS … #define LM_RC_BAR_CFG_CTRL_DISABLED(bar) … #define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) … #define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) … #define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) … #define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) … #define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) … #define LM_RC_BAR_CFG_APERTURE(bar, aperture) … /* PTM Control Register */ #define CDNS_PCIE_LM_PTM_CTRL … #define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN … /* * Endpoint Function Registers (PCI configuration space for endpoint functions) */ #define CDNS_PCIE_EP_FUNC_BASE(fn) … #define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET … #define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET … #define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET … #define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET … /* * Endpoint PF Registers */ #define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) … #define CDNS_PCIE_ARI_CAP_NFN_MASK … /* * Root Port Registers (PCI configuration space for the root port function) */ #define CDNS_PCIE_RP_BASE … #define CDNS_PCIE_RP_CAP_OFFSET … /* * Address Translation Registers */ #define CDNS_PCIE_AT_BASE … /* Region r Outbound AXI to PCIe Address Translation Register 0 */ #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) … #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK … #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) … #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK … #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) … #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK … #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) … /* Region r Outbound AXI to PCIe Address Translation Register 1 */ #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) … /* Region r Outbound PCIe Descriptor Register 0 */ #define CDNS_PCIE_AT_OB_REGION_DESC0(r) … #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK … #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM … #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO … #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 … #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 … #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG … #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG … /* Bit 23 MUST be set in RC mode. */ #define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID … #define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK … #define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) … /* Region r Outbound PCIe Descriptor Register 1 */ #define CDNS_PCIE_AT_OB_REGION_DESC1(r) … #define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK … #define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) … /* Region r AXI Region Base Address Register 0 */ #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) … #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK … #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) … /* Region r AXI Region Base Address Register 1 */ #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) … /* Root Port BAR Inbound PCIe to AXI Address Translation Register */ #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) … #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK … #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) … #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) … /* AXI link down register */ #define CDNS_PCIE_AT_LINKDOWN … /* LTSSM Capabilities register */ #define CDNS_PCIE_LTSSM_CONTROL_CAP … #define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK … #define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT … #define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) … enum cdns_pcie_rp_bar { … }; #define CDNS_PCIE_RP_MAX_IB … #define CDNS_PCIE_MAX_OB … struct cdns_pcie_rp_ib_bar { … }; /* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ #define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) … #define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) … /* Normal/Vendor specific message access: offset inside some outbound region */ #define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK … #define CDNS_PCIE_NORMAL_MSG_ROUTING(route) … #define CDNS_PCIE_NORMAL_MSG_CODE_MASK … #define CDNS_PCIE_NORMAL_MSG_CODE(code) … #define CDNS_PCIE_MSG_NO_DATA … struct cdns_pcie; enum cdns_pcie_msg_code { … }; enum cdns_pcie_msg_routing { … }; struct cdns_pcie_ops { … }; /** * struct cdns_pcie - private data for Cadence PCIe controller drivers * @reg_base: IO mapped register base * @mem_res: start/end offsets in the physical system memory to map PCI accesses * @dev: PCIe controller * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint. * @phy_count: number of supported PHY devices * @phy: list of pointers to specific PHY control blocks * @link: list of pointers to corresponding device link representations * @ops: Platform-specific ops to control various inputs from Cadence PCIe * wrapper */ struct cdns_pcie { … }; /** * struct cdns_pcie_rc - private data for this PCIe Root Complex driver * @pcie: Cadence PCIe controller * @dev: pointer to PCIe device * @cfg_res: start/end offsets in the physical system memory to map PCI * configuration space accesses * @cfg_base: IO mapped window to access the PCI configuration space of a * single function at a time * @vendor_id: PCI vendor ID * @device_id: PCI device ID * @avail_ib_bar: Status of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or * available * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk */ struct cdns_pcie_rc { … }; /** * struct cdns_pcie_epf - Structure to hold info about endpoint function * @epf: Info about virtual functions attached to the physical function * @epf_bar: reference to the pci_epf_bar for the six Base Address Registers */ struct cdns_pcie_epf { … }; /** * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver * @pcie: Cadence PCIe controller * @max_regions: maximum number of regions supported by hardware * @ob_region_map: bitmask of mapped outbound regions * @ob_addr: base addresses in the AXI bus where the outbound regions start * @irq_phys_addr: base address on the AXI bus where the MSI/INTX IRQ * dedicated outbound regions is mapped. * @irq_cpu_addr: base address in the CPU space where a write access triggers * the sending of a memory write (MSI) / normal message (INTX * IRQ) TLP through the PCIe bus. * @irq_pci_addr: used to save the current mapping of the MSI/INTX IRQ * dedicated outbound region. * @irq_pci_fn: the latest PCI function that has updated the mapping of * the MSI/INTX IRQ dedicated outbound region. * @irq_pending: bitmask of asserted INTX IRQs. * @lock: spin lock to disable interrupts while modifying PCIe controller * registers fields (RMW) accessible by both remote RC and EP to * minimize time between read and write * @epf: Structure to hold info about endpoint function * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk * @quirk_disable_flr: Disable FLR (Function Level Reset) quirk flag */ struct cdns_pcie_ep { … }; /* Register access */ static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) { … } static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) { … } static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) { … } static inline void cdns_pcie_write_sz(void __iomem *addr, int size, u32 value) { … } /* Root Port register access */ static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie, u32 reg, u8 value) { … } static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, u32 reg, u16 value) { … } static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) { … } /* Endpoint Function register access */ static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, u32 reg, u8 value) { … } static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn, u32 reg, u16 value) { … } static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn, u32 reg, u32 value) { … } static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg) { … } static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) { … } static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) { … } static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie) { … } static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) { … } #ifdef CONFIG_PCIE_CADENCE_HOST int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, int where); #else static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) { return 0; } static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { return NULL; } #endif #ifdef CONFIG_PCIE_CADENCE_EP int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep); #else static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) { return 0; } #endif void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, u32 r, bool is_io, u64 cpu_addr, u64 pci_addr, size_t size); void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 busnr, u8 fn, u32 r, u64 cpu_addr); void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r); void cdns_pcie_disable_phy(struct cdns_pcie *pcie); int cdns_pcie_enable_phy(struct cdns_pcie *pcie); int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); extern const struct dev_pm_ops cdns_pcie_pm_ops; #endif /* _PCIE_CADENCE_H */
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