/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright(c) 2013 - 2021 Intel Corporation. */ #ifndef _I40E_TYPE_H_ #define _I40E_TYPE_H_ #include <uapi/linux/if_ether.h> #include "i40e_adminq.h" #include "i40e_hmc.h" #define I40E_MAX_VSI_QP … #define I40E_MAX_VF_VSI … #define I40E_MAX_CHAINED_RX_BUFFERS … #define I40E_MAX_PF_UDP_OFFLOAD_PORTS … /* Max default timeout in ms, */ #define I40E_MAX_NVM_TIMEOUT … /* Max timeout in ms for the phy to respond */ #define I40E_MAX_PHY_TIMEOUT … /* Switch from ms to the 1usec global time (this is the GTIME resolution) */ #define I40E_MS_TO_GTIME(time) … /* forward declaration */ struct i40e_hw; I40E_ADMINQ_CALLBACK; /* Data type manipulation macros. */ #define I40E_DESC_UNUSED(R) … /* bitfields for Tx queue mapping in QTX_CTL */ #define I40E_QTX_CTL_VF_QUEUE … #define I40E_QTX_CTL_VM_QUEUE … #define I40E_QTX_CTL_PF_QUEUE … #define I40E_MDIO_CLAUSE22_STCODE_MASK … #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK … #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK … #define I40E_MDIO_CLAUSE45_STCODE_MASK … #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK … #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK … #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK … #define I40E_PHY_COM_REG_PAGE … #define I40E_PHY_LED_LINK_MODE_MASK … #define I40E_PHY_LED_MANUAL_ON … #define I40E_PHY_LED_PROV_REG_1 … #define I40E_PHY_LED_MODE_MASK … #define I40E_PHY_LED_MODE_ORIG … /* These are structs for managing the hardware information and the operations. * The structures of function pointers are filled out at init time when we * know for sure exactly which hardware we're working with. This gives us the * flexibility of using the same main driver code but adapting to slightly * different hardware needs as new parts are developed. For this architecture, * the Firmware and AdminQ are intended to insulate the driver from most of the * future changes, but these structures will also do part of the job. */ enum i40e_mac_type { … }; enum i40e_media_type { … }; enum i40e_fc_mode { … }; enum i40e_set_fc_aq_failures { … }; enum i40e_vsi_type { … }; enum i40e_queue_type { … }; struct i40e_link_status { … }; struct i40e_phy_info { … }; #define I40E_CAP_PHY_TYPE_SGMII … #define I40E_CAP_PHY_TYPE_1000BASE_KX … #define I40E_CAP_PHY_TYPE_10GBASE_KX4 … #define I40E_CAP_PHY_TYPE_10GBASE_KR … #define I40E_CAP_PHY_TYPE_40GBASE_KR4 … #define I40E_CAP_PHY_TYPE_XAUI … #define I40E_CAP_PHY_TYPE_XFI … #define I40E_CAP_PHY_TYPE_SFI … #define I40E_CAP_PHY_TYPE_XLAUI … #define I40E_CAP_PHY_TYPE_XLPPI … #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU … #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU … #define I40E_CAP_PHY_TYPE_10GBASE_AOC … #define I40E_CAP_PHY_TYPE_40GBASE_AOC … #define I40E_CAP_PHY_TYPE_100BASE_TX … #define I40E_CAP_PHY_TYPE_1000BASE_T … #define I40E_CAP_PHY_TYPE_10GBASE_T … #define I40E_CAP_PHY_TYPE_10GBASE_SR … #define I40E_CAP_PHY_TYPE_10GBASE_LR … #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU … #define I40E_CAP_PHY_TYPE_10GBASE_CR1 … #define I40E_CAP_PHY_TYPE_40GBASE_CR4 … #define I40E_CAP_PHY_TYPE_40GBASE_SR4 … #define I40E_CAP_PHY_TYPE_40GBASE_LR4 … #define I40E_CAP_PHY_TYPE_1000BASE_SX … #define I40E_CAP_PHY_TYPE_1000BASE_LX … #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL … #define I40E_CAP_PHY_TYPE_20GBASE_KR2 … /* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So, * a shift is needed to adjust for this with values larger than 31. The * only affected values are I40E_PHY_TYPE_25GBASE_*. */ #define I40E_PHY_TYPE_OFFSET … #define I40E_CAP_PHY_TYPE_25GBASE_KR … #define I40E_CAP_PHY_TYPE_25GBASE_CR … #define I40E_CAP_PHY_TYPE_25GBASE_SR … #define I40E_CAP_PHY_TYPE_25GBASE_LR … #define I40E_CAP_PHY_TYPE_25GBASE_AOC … #define I40E_CAP_PHY_TYPE_25GBASE_ACC … /* Offset for 2.5G/5G PHY Types value to bit number conversion */ #define I40E_CAP_PHY_TYPE_2_5GBASE_T … #define I40E_CAP_PHY_TYPE_5GBASE_T … #define I40E_HW_CAP_MAX_GPIO … /* Capabilities of a PF or a VF or the whole device */ struct i40e_hw_capabilities { … }; struct i40e_mac_info { … }; enum i40e_aq_resources_ids { … }; enum i40e_aq_resource_access_type { … }; struct i40e_nvm_info { … }; /* definitions used in NVM update support */ enum i40e_nvmupd_cmd { … }; enum i40e_nvmupd_state { … }; /* nvm_access definition and its masks/shifts need to be accessible to * application, core driver, and shared code. Where is the right file? */ #define I40E_NVM_READ … #define I40E_NVM_WRITE … #define I40E_NVM_MOD_PNT_MASK … #define I40E_NVM_TRANS_SHIFT … #define I40E_NVM_TRANS_MASK … #define I40E_NVM_PRESERVATION_FLAGS_SHIFT … #define I40E_NVM_PRESERVATION_FLAGS_MASK … #define I40E_NVM_PRESERVATION_FLAGS_SELECTED … #define I40E_NVM_PRESERVATION_FLAGS_ALL … #define I40E_NVM_CON … #define I40E_NVM_SNT … #define I40E_NVM_LCB … #define I40E_NVM_SA … #define I40E_NVM_ERA … #define I40E_NVM_CSUM … #define I40E_NVM_AQE … #define I40E_NVM_EXEC … #define I40E_NVMUPD_MAX_DATA … struct i40e_nvm_access { … }; /* (Q)SFP module access definitions */ #define I40E_I2C_EEPROM_DEV_ADDR … #define I40E_I2C_EEPROM_DEV_ADDR2 … #define I40E_MODULE_REVISION_ADDR … #define I40E_MODULE_SFF_8472_COMP … #define I40E_MODULE_SFF_8472_SWAP … #define I40E_MODULE_SFF_ADDR_MODE … #define I40E_MODULE_SFF_DDM_IMPLEMENTED … #define I40E_MODULE_TYPE_QSFP_PLUS … #define I40E_MODULE_TYPE_QSFP28 … #define I40E_MODULE_QSFP_MAX_LEN … /* PCI bus types */ enum i40e_bus_type { … }; /* PCI bus speeds */ enum i40e_bus_speed { … }; /* PCI bus widths */ enum i40e_bus_width { … }; /* Bus parameters */ struct i40e_bus_info { … }; /* Flow control (FC) parameters */ struct i40e_fc_info { … }; #define I40E_MAX_TRAFFIC_CLASS … #define I40E_MAX_USER_PRIORITY … #define I40E_DCBX_MAX_APPS … #define I40E_LLDPDU_SIZE … #define I40E_TLV_STATUS_OPER … #define I40E_TLV_STATUS_SYNC … #define I40E_TLV_STATUS_ERR … #define I40E_CEE_OPER_MAX_APPS … #define I40E_APP_PROTOID_FCOE … #define I40E_APP_PROTOID_ISCSI … #define I40E_APP_PROTOID_FIP … #define I40E_APP_SEL_ETHTYPE … #define I40E_APP_SEL_TCPIP … #define I40E_CEE_APP_SEL_ETHTYPE … #define I40E_CEE_APP_SEL_TCPIP … /* CEE or IEEE 802.1Qaz ETS Configuration data */ struct i40e_dcb_ets_config { … }; /* CEE or IEEE 802.1Qaz PFC Configuration data */ struct i40e_dcb_pfc_config { … }; /* CEE or IEEE 802.1Qaz Application Priority data */ struct i40e_dcb_app_priority_table { … }; struct i40e_dcbx_config { … }; enum i40e_hw_flags { … }; /* Port hardware description */ struct i40e_hw { … }; struct i40e_driver_version { … }; /* RX Descriptors */ i40e_16byte_rx_desc; i40e_32byte_rx_desc; enum i40e_rx_desc_status_bits { … }; #define I40E_RXD_QW1_STATUS_SHIFT … #define I40E_RXD_QW1_STATUS_MASK … #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT … #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK … #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT … #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK … enum i40e_rx_desc_fltstat_values { … }; #define I40E_RXD_QW1_ERROR_SHIFT … #define I40E_RXD_QW1_ERROR_MASK … enum i40e_rx_desc_error_bits { … }; enum i40e_rx_desc_error_l3l4e_fcoe_masks { … }; #define I40E_RXD_QW1_PTYPE_SHIFT … #define I40E_RXD_QW1_PTYPE_MASK … #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT … #define I40E_RXD_QW1_LENGTH_PBUF_MASK … #define I40E_RXD_QW1_LENGTH_SPH_SHIFT … #define I40E_RXD_QW1_LENGTH_SPH_MASK … enum i40e_rx_desc_ext_status_bits { … }; enum i40e_rx_desc_pe_status_bits { … }; #define I40E_RX_PROG_STATUS_DESC_LENGTH … #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT … #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK … #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT … #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK … enum i40e_rx_prog_status_desc_status_bits { … }; enum i40e_rx_prog_status_desc_prog_id_masks { … }; enum i40e_rx_prog_status_desc_error_bits { … }; /* TX Descriptor */ struct i40e_tx_desc { … }; enum i40e_tx_desc_dtype_value { … }; #define I40E_TXD_QW1_CMD_SHIFT … enum i40e_tx_desc_cmd_bits { … }; #define I40E_TXD_QW1_OFFSET_SHIFT … enum i40e_tx_desc_length_fields { … }; #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT … #define I40E_TXD_QW1_L2TAG1_SHIFT … /* Context descriptors */ struct i40e_tx_context_desc { … }; #define I40E_TXD_CTX_QW1_CMD_SHIFT … enum i40e_tx_ctx_desc_cmd_bits { … }; #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT … #define I40E_TXD_CTX_QW1_MSS_SHIFT … enum i40e_tx_ctx_desc_eipt_offload { … }; #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT … #define I40E_TXD_CTX_QW0_NATT_SHIFT … #define I40E_TXD_CTX_UDP_TUNNELING … #define I40E_TXD_CTX_GRE_TUNNELING … #define I40E_TXD_CTX_QW0_NATLEN_SHIFT … #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT … #define I40E_TXD_CTX_QW0_L4T_CS_MASK … struct i40e_filter_program_desc { … }; #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT … #define I40E_TXD_FLTR_QW0_QINDEX_MASK … #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT … #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK … #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT … #define I40E_TXD_FLTR_QW0_PCTYPE_MASK … /* Packet Classifier Types for filters */ enum i40e_filter_pctype { … }; enum i40e_filter_program_desc_dest { … }; enum i40e_filter_program_desc_fd_status { … }; #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT … #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK … #define I40E_TXD_FLTR_QW1_CMD_SHIFT … #define I40E_TXD_FLTR_QW1_PCMD_SHIFT … enum i40e_filter_program_desc_pcmd { … }; #define I40E_TXD_FLTR_QW1_DEST_SHIFT … #define I40E_TXD_FLTR_QW1_DEST_MASK … #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT … #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK … #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT … #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK … #define I40E_TXD_FLTR_QW1_ATR_SHIFT … #define I40E_TXD_FLTR_QW1_ATR_MASK … #define I40E_TXD_FLTR_QW1_ATR_SHIFT … #define I40E_TXD_FLTR_QW1_ATR_MASK … #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT … #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK … enum i40e_filter_type { … }; struct i40e_vsi_context { … }; struct i40e_veb_context { … }; /* Statistics collected by each port, VSI, VEB, and S-channel */ struct i40e_eth_stats { … }; /* Statistics collected per VEB per TC */ struct i40e_veb_tc_stats { … }; /* Statistics collected by the MAC */ struct i40e_hw_port_stats { … }; /* Checksum and Shadow RAM pointers */ #define I40E_SR_NVM_CONTROL_WORD … #define I40E_EMP_MODULE_PTR … #define I40E_SR_EMP_MODULE_PTR … #define I40E_SR_PBA_FLAGS … #define I40E_SR_PBA_BLOCK_PTR … #define I40E_SR_BOOT_CONFIG_PTR … #define I40E_NVM_OEM_VER_OFF … #define I40E_SR_NVM_DEV_STARTER_VERSION … #define I40E_SR_NVM_WAKE_ON_LAN … #define I40E_SR_NVM_EETRACK_LO … #define I40E_SR_NVM_EETRACK_HI … #define I40E_SR_VPD_PTR … #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR … #define I40E_SR_SW_CHECKSUM_WORD … #define I40E_SR_EMP_SR_SETTINGS_PTR … /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ #define I40E_SR_VPD_MODULE_MAX_SIZE … #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE … #define I40E_SR_CONTROL_WORD_1_SHIFT … #define I40E_SR_CONTROL_WORD_1_MASK … #define I40E_SR_NVM_MAP_STRUCTURE_TYPE … #define I40E_PTR_TYPE … #define I40E_SR_OCP_CFG_WORD0 … #define I40E_SR_OCP_ENABLED … /* Shadow RAM related */ #define I40E_SR_SECTOR_SIZE_IN_WORDS … #define I40E_SR_WORDS_IN_1KB … /* Checksum should be calculated such that after adding all the words, * including the checksum word itself, the sum should be 0xBABA. */ #define I40E_SR_SW_CHECKSUM_BASE … #define I40E_SRRD_SRCTL_ATTEMPTS … enum i40e_switch_element_types { … }; /* Supported EtherType filters */ enum i40e_ether_type_index { … }; /* Filter context base size is 1K */ #define I40E_HASH_FILTER_BASE_SIZE … /* Supported Hash filter values */ enum i40e_hash_filter_size { … }; /* DMA context base size is 0.5K */ #define I40E_DMA_CNTX_BASE_SIZE … /* Supported DMA context values */ enum i40e_dma_cntx_size { … }; /* Supported Hash look up table (LUT) sizes */ enum i40e_hash_lut_size { … }; /* Structure to hold a per PF filter control settings */ struct i40e_filter_control_settings { … }; /* Structure to hold device level control filter counts */ struct i40e_control_filter_stats { … }; enum i40e_reset_type { … }; /* IEEE 802.1AB LLDP Agent Variables from NVM */ #define I40E_NVM_LLDP_CFG_PTR … #define I40E_SR_LLDP_CFG_PTR … struct i40e_lldp_variables { … }; /* Offsets into Alternate Ram */ #define I40E_ALT_STRUCT_FIRST_PF_OFFSET … #define I40E_ALT_STRUCT_DWORDS_PER_PF … #define I40E_ALT_STRUCT_MIN_BW_OFFSET … #define I40E_ALT_STRUCT_MAX_BW_OFFSET … /* Alternate Ram Bandwidth Masks */ #define I40E_ALT_BW_VALUE_MASK … #define I40E_ALT_BW_VALID_MASK … /* RSS Hash Table Size */ #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 … /* INPUT SET MASK for RSS, flow director, and flexible payload */ #define I40E_X722_L3_SRC_SHIFT … #define I40E_X722_L3_SRC_MASK … #define I40E_X722_L3_DST_SHIFT … #define I40E_X722_L3_DST_MASK … #define I40E_L3_SRC_SHIFT … #define I40E_L3_SRC_MASK … #define I40E_L3_V6_SRC_SHIFT … #define I40E_L3_V6_SRC_MASK … #define I40E_L3_DST_SHIFT … #define I40E_L3_DST_MASK … #define I40E_L3_V6_DST_SHIFT … #define I40E_L3_V6_DST_MASK … #define I40E_L4_SRC_SHIFT … #define I40E_L4_SRC_MASK … #define I40E_L4_DST_SHIFT … #define I40E_L4_DST_MASK … #define I40E_VERIFY_TAG_SHIFT … #define I40E_VERIFY_TAG_MASK … #define I40E_VLAN_SRC_SHIFT … #define I40E_VLAN_SRC_MASK … #define I40E_FLEX_50_SHIFT … #define I40E_FLEX_50_MASK … #define I40E_FLEX_51_SHIFT … #define I40E_FLEX_51_MASK … #define I40E_FLEX_52_SHIFT … #define I40E_FLEX_52_MASK … #define I40E_FLEX_53_SHIFT … #define I40E_FLEX_53_MASK … #define I40E_FLEX_54_SHIFT … #define I40E_FLEX_54_MASK … #define I40E_FLEX_55_SHIFT … #define I40E_FLEX_55_MASK … #define I40E_FLEX_56_SHIFT … #define I40E_FLEX_56_MASK … #define I40E_FLEX_57_SHIFT … #define I40E_FLEX_57_MASK … /* Version format for Dynamic Device Personalization(DDP) */ struct i40e_ddp_version { … }; #define I40E_DDP_NAME_SIZE … /* Package header */ struct i40e_package_header { … }; /* Generic segment header */ struct i40e_generic_seg_header { … }; struct i40e_metadata_segment { … }; struct i40e_device_id_entry { … }; struct i40e_profile_segment { … }; struct i40e_section_table { … }; struct i40e_profile_section_header { … }; struct i40e_profile_tlv_section_record { … }; /* Generic AQ section in proflie */ struct i40e_profile_aq_section { … }; struct i40e_profile_info { … }; #endif /* _I40E_TYPE_H_ */
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