/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright(c) 2013 - 2018 Intel Corporation. */ #ifndef _IAVF_TYPE_H_ #define _IAVF_TYPE_H_ #include "iavf_status.h" #include "iavf_osdep.h" #include "iavf_register.h" #include "iavf_adminq.h" #include "iavf_devids.h" /* IAVF_MASK is a macro used on 32 bit registers */ #define IAVF_MASK(mask, shift) … #define IAVF_MAX_VSI_QP … #define IAVF_MAX_VF_VSI … #define IAVF_MAX_CHAINED_RX_BUFFERS … /* forward declaration */ struct iavf_hw; IAVF_ADMINQ_CALLBACK; /* Data type manipulation macros. */ #define IAVF_DESC_UNUSED(R) … /* bitfields for Tx queue mapping in QTX_CTL */ #define IAVF_QTX_CTL_VF_QUEUE … #define IAVF_QTX_CTL_VM_QUEUE … #define IAVF_QTX_CTL_PF_QUEUE … /* debug masks - set these bits in hw->debug_mask to control output */ enum iavf_debug_mask { … }; /* These are structs for managing the hardware information and the operations. * The structures of function pointers are filled out at init time when we * know for sure exactly which hardware we're working with. This gives us the * flexibility of using the same main driver code but adapting to slightly * different hardware needs as new parts are developed. For this architecture, * the Firmware and AdminQ are intended to insulate the driver from most of the * future changes, but these structures will also do part of the job. */ enum iavf_vsi_type { … }; enum iavf_queue_type { … }; #define IAVF_HW_CAP_MAX_GPIO … /* Capabilities of a PF or a VF or the whole device */ struct iavf_hw_capabilities { … }; struct iavf_mac_info { … }; /* PCI bus types */ enum iavf_bus_type { … }; /* PCI bus speeds */ enum iavf_bus_speed { … }; /* PCI bus widths */ enum iavf_bus_width { … }; /* Bus parameters */ struct iavf_bus_info { … }; #define IAVF_MAX_USER_PRIORITY … /* Port hardware description */ struct iavf_hw { … }; /* RX Descriptors */ iavf_16byte_rx_desc; iavf_32byte_rx_desc; enum iavf_rx_desc_status_bits { … }; #define IAVF_RXD_QW1_STATUS_SHIFT … #define IAVF_RXD_QW1_STATUS_MASK … #define IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT … #define IAVF_RXD_QW1_STATUS_TSYNINDX_MASK … #define IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT … #define IAVF_RXD_QW1_STATUS_TSYNVALID_MASK … enum iavf_rx_desc_fltstat_values { … }; #define IAVF_RXD_QW1_ERROR_SHIFT … #define IAVF_RXD_QW1_ERROR_MASK … enum iavf_rx_desc_error_bits { … }; enum iavf_rx_desc_error_l3l4e_fcoe_masks { … }; #define IAVF_RXD_QW1_PTYPE_SHIFT … #define IAVF_RXD_QW1_PTYPE_MASK … #define IAVF_RXD_QW1_LENGTH_PBUF_SHIFT … #define IAVF_RXD_QW1_LENGTH_PBUF_MASK … #define IAVF_RXD_QW1_LENGTH_HBUF_SHIFT … #define IAVF_RXD_QW1_LENGTH_HBUF_MASK … #define IAVF_RXD_QW1_LENGTH_SPH_SHIFT … #define IAVF_RXD_QW1_LENGTH_SPH_MASK … enum iavf_rx_desc_ext_status_bits { … }; enum iavf_rx_desc_pe_status_bits { … }; #define IAVF_RX_PROG_STATUS_DESC_LENGTH_SHIFT … #define IAVF_RX_PROG_STATUS_DESC_LENGTH … #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT … #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_MASK … #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT … #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_MASK … enum iavf_rx_prog_status_desc_status_bits { … }; enum iavf_rx_prog_status_desc_prog_id_masks { … }; enum iavf_rx_prog_status_desc_error_bits { … }; /* TX Descriptor */ struct iavf_tx_desc { … }; #define IAVF_TXD_QW1_DTYPE_SHIFT … #define IAVF_TXD_QW1_DTYPE_MASK … enum iavf_tx_desc_dtype_value { … }; #define IAVF_TXD_QW1_CMD_SHIFT … #define IAVF_TXD_QW1_CMD_MASK … enum iavf_tx_desc_cmd_bits { … }; #define IAVF_TXD_QW1_OFFSET_SHIFT … #define IAVF_TXD_QW1_OFFSET_MASK … enum iavf_tx_desc_length_fields { … }; #define IAVF_TXD_QW1_TX_BUF_SZ_SHIFT … #define IAVF_TXD_QW1_TX_BUF_SZ_MASK … #define IAVF_TXD_QW1_L2TAG1_SHIFT … #define IAVF_TXD_QW1_L2TAG1_MASK … /* Context descriptors */ struct iavf_tx_context_desc { … }; #define IAVF_TXD_CTX_QW1_CMD_SHIFT … #define IAVF_TXD_CTX_QW1_CMD_MASK … enum iavf_tx_ctx_desc_cmd_bits { … }; /* Packet Classifier Types for filters */ enum iavf_filter_pctype { … }; #define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT … #define IAVF_TXD_CTX_QW1_TSO_LEN_MASK … #define IAVF_TXD_CTX_QW1_MSS_SHIFT … #define IAVF_TXD_CTX_QW1_MSS_MASK … #define IAVF_TXD_CTX_QW1_VSI_SHIFT … #define IAVF_TXD_CTX_QW1_VSI_MASK … #define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT … #define IAVF_TXD_CTX_QW0_EXT_IP_MASK … enum iavf_tx_ctx_desc_eipt_offload { … }; #define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT … #define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK … #define IAVF_TXD_CTX_QW0_NATT_SHIFT … #define IAVF_TXD_CTX_QW0_NATT_MASK … #define IAVF_TXD_CTX_UDP_TUNNELING … #define IAVF_TXD_CTX_GRE_TUNNELING … #define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT … #define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK … #define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST … #define IAVF_TXD_CTX_QW0_NATLEN_SHIFT … #define IAVF_TXD_CTX_QW0_NATLEN_MASK … #define IAVF_TXD_CTX_QW0_DECTTL_SHIFT … #define IAVF_TXD_CTX_QW0_DECTTL_MASK … #define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT … #define IAVF_TXD_CTX_QW0_L4T_CS_MASK … /* Statistics collected by each port, VSI, VEB, and S-channel */ struct iavf_eth_stats { … }; #endif /* _IAVF_TYPE_H_ */
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