/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ /* Do not edit directly, auto-generated from: */ /* Documentation/netlink/specs/dpll.yaml */ /* YNL-GEN uapi header */ #ifndef _UAPI_LINUX_DPLL_H #define _UAPI_LINUX_DPLL_H #define DPLL_FAMILY_NAME … #define DPLL_FAMILY_VERSION … /** * enum dpll_mode - working modes a dpll can support, differentiates if and how * dpll selects one of its inputs to syntonize with it, valid values for * DPLL_A_MODE attribute * @DPLL_MODE_MANUAL: input can be only selected by sending a request to dpll * @DPLL_MODE_AUTOMATIC: highest prio input pin auto selected by dpll */ enum dpll_mode { … }; /** * enum dpll_lock_status - provides information of dpll device lock status, * valid values for DPLL_A_LOCK_STATUS attribute * @DPLL_LOCK_STATUS_UNLOCKED: dpll was not yet locked to any valid input (or * forced by setting DPLL_A_MODE to DPLL_MODE_DETACHED) * @DPLL_LOCK_STATUS_LOCKED: dpll is locked to a valid signal, but no holdover * available * @DPLL_LOCK_STATUS_LOCKED_HO_ACQ: dpll is locked and holdover acquired * @DPLL_LOCK_STATUS_HOLDOVER: dpll is in holdover state - lost a valid lock or * was forced by disconnecting all the pins (latter possible only when dpll * lock-state was already DPLL_LOCK_STATUS_LOCKED_HO_ACQ, if dpll lock-state * was not DPLL_LOCK_STATUS_LOCKED_HO_ACQ, the dpll's lock-state shall remain * DPLL_LOCK_STATUS_UNLOCKED) */ enum dpll_lock_status { … }; /** * enum dpll_lock_status_error - if previous status change was done due to a * failure, this provides information of dpll device lock status error. Valid * values for DPLL_A_LOCK_STATUS_ERROR attribute * @DPLL_LOCK_STATUS_ERROR_NONE: dpll device lock status was changed without * any error * @DPLL_LOCK_STATUS_ERROR_UNDEFINED: dpll device lock status was changed due * to undefined error. Driver fills this value up in case it is not able to * obtain suitable exact error type. * @DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN: dpll device lock status was changed * because of associated media got down. This may happen for example if dpll * device was previously locked on an input pin of type * PIN_TYPE_SYNCE_ETH_PORT. * @DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH: the FFO * (Fractional Frequency Offset) between the RX and TX symbol rate on the * media got too high. This may happen for example if dpll device was * previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT. */ enum dpll_lock_status_error { … }; #define DPLL_TEMP_DIVIDER … /** * enum dpll_type - type of dpll, valid values for DPLL_A_TYPE attribute * @DPLL_TYPE_PPS: dpll produces Pulse-Per-Second signal * @DPLL_TYPE_EEC: dpll drives the Ethernet Equipment Clock */ enum dpll_type { … }; /** * enum dpll_pin_type - defines possible types of a pin, valid values for * DPLL_A_PIN_TYPE attribute * @DPLL_PIN_TYPE_MUX: aggregates another layer of selectable pins * @DPLL_PIN_TYPE_EXT: external input * @DPLL_PIN_TYPE_SYNCE_ETH_PORT: ethernet port PHY's recovered clock * @DPLL_PIN_TYPE_INT_OSCILLATOR: device internal oscillator * @DPLL_PIN_TYPE_GNSS: GNSS recovered clock */ enum dpll_pin_type { … }; /** * enum dpll_pin_direction - defines possible direction of a pin, valid values * for DPLL_A_PIN_DIRECTION attribute * @DPLL_PIN_DIRECTION_INPUT: pin used as a input of a signal * @DPLL_PIN_DIRECTION_OUTPUT: pin used to output the signal */ enum dpll_pin_direction { … }; #define DPLL_PIN_FREQUENCY_1_HZ … #define DPLL_PIN_FREQUENCY_10_KHZ … #define DPLL_PIN_FREQUENCY_77_5_KHZ … #define DPLL_PIN_FREQUENCY_10_MHZ … /** * enum dpll_pin_state - defines possible states of a pin, valid values for * DPLL_A_PIN_STATE attribute * @DPLL_PIN_STATE_CONNECTED: pin connected, active input of phase locked loop * @DPLL_PIN_STATE_DISCONNECTED: pin disconnected, not considered as a valid * input * @DPLL_PIN_STATE_SELECTABLE: pin enabled for automatic input selection */ enum dpll_pin_state { … }; /** * enum dpll_pin_capabilities - defines possible capabilities of a pin, valid * flags on DPLL_A_PIN_CAPABILITIES attribute * @DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE: pin direction can be changed * @DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE: pin priority can be changed * @DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE: pin state can be changed */ enum dpll_pin_capabilities { … }; #define DPLL_PHASE_OFFSET_DIVIDER … enum dpll_a { … }; enum dpll_a_pin { … }; enum dpll_cmd { … }; #define DPLL_MCGRP_MONITOR … #endif /* _UAPI_LINUX_DPLL_H */
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