/* SPDX-License-Identifier: GPL-2.0 */ /* * Definitions for Marvell PPv2 network controller for Armada 375 SoC. * * Copyright (C) 2014 Marvell * * Marcin Wojtas <[email protected]> */ #ifndef _MVPP2_H_ #define _MVPP2_H_ #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/netdevice.h> #include <linux/net_tstamp.h> #include <linux/phy.h> #include <linux/phylink.h> #include <net/flow_offload.h> #include <net/page_pool/types.h> #include <linux/bpf.h> #include <net/xdp.h> /* The PacketOffset field is measured in units of 32 bytes and is 3 bits wide, * so the maximum offset is 7 * 32 = 224 */ #define MVPP2_SKB_HEADROOM … #define MVPP2_XDP_PASS … #define MVPP2_XDP_DROPPED … #define MVPP2_XDP_TX … #define MVPP2_XDP_REDIR … /* Fifo Registers */ #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) … #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) … #define MVPP2_RX_MIN_PKT_SIZE_REG … #define MVPP2_RX_FIFO_INIT_REG … #define MVPP22_TX_FIFO_THRESH_REG(port) … #define MVPP22_TX_FIFO_SIZE_REG(port) … /* RX DMA Top Registers */ #define MVPP2_RX_CTRL_REG(port) … #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) … #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK … #define MVPP2_POOL_BUF_SIZE_REG(pool) … #define MVPP2_POOL_BUF_SIZE_OFFSET … #define MVPP2_RXQ_CONFIG_REG(rxq) … #define MVPP2_SNOOP_PKT_SIZE_MASK … #define MVPP2_SNOOP_BUF_HDR_MASK … #define MVPP2_RXQ_POOL_SHORT_OFFS … #define MVPP21_RXQ_POOL_SHORT_MASK … #define MVPP22_RXQ_POOL_SHORT_MASK … #define MVPP2_RXQ_POOL_LONG_OFFS … #define MVPP21_RXQ_POOL_LONG_MASK … #define MVPP22_RXQ_POOL_LONG_MASK … #define MVPP2_RXQ_PACKET_OFFSET_OFFS … #define MVPP2_RXQ_PACKET_OFFSET_MASK … #define MVPP2_RXQ_DISABLE_MASK … /* Top Registers */ #define MVPP2_MH_REG(port) … #define MVPP2_DSA_EXTENDED … #define MVPP2_VER_ID_REG … #define MVPP2_VER_PP22 … #define MVPP2_VER_PP23 … /* Parser Registers */ #define MVPP2_PRS_INIT_LOOKUP_REG … #define MVPP2_PRS_PORT_LU_MAX … #define MVPP2_PRS_PORT_LU_MASK(port) … #define MVPP2_PRS_PORT_LU_VAL(port, val) … #define MVPP2_PRS_INIT_OFFS_REG(port) … #define MVPP2_PRS_INIT_OFF_MASK(port) … #define MVPP2_PRS_INIT_OFF_VAL(port, val) … #define MVPP2_PRS_MAX_LOOP_REG(port) … #define MVPP2_PRS_MAX_LOOP_MASK(port) … #define MVPP2_PRS_MAX_LOOP_VAL(port, val) … #define MVPP2_PRS_TCAM_IDX_REG … #define MVPP2_PRS_TCAM_DATA_REG(idx) … #define MVPP2_PRS_TCAM_INV_MASK … #define MVPP2_PRS_SRAM_IDX_REG … #define MVPP2_PRS_SRAM_DATA_REG(idx) … #define MVPP2_PRS_TCAM_CTRL_REG … #define MVPP2_PRS_TCAM_EN_MASK … #define MVPP2_PRS_TCAM_HIT_IDX_REG … #define MVPP2_PRS_TCAM_HIT_CNT_REG … #define MVPP2_PRS_TCAM_HIT_CNT_MASK … /* RSS Registers */ #define MVPP22_RSS_INDEX … #define MVPP22_RSS_INDEX_TABLE_ENTRY(idx) … #define MVPP22_RSS_INDEX_TABLE(idx) … #define MVPP22_RSS_INDEX_QUEUE(idx) … #define MVPP22_RXQ2RSS_TABLE … #define MVPP22_RSS_TABLE_POINTER(p) … #define MVPP22_RSS_TABLE_ENTRY … #define MVPP22_RSS_WIDTH … /* Classifier Registers */ #define MVPP2_CLS_MODE_REG … #define MVPP2_CLS_MODE_ACTIVE_MASK … #define MVPP2_CLS_PORT_WAY_REG … #define MVPP2_CLS_PORT_WAY_MASK(port) … #define MVPP2_CLS_LKP_INDEX_REG … #define MVPP2_CLS_LKP_INDEX_WAY_OFFS … #define MVPP2_CLS_LKP_TBL_REG … #define MVPP2_CLS_LKP_TBL_RXQ_MASK … #define MVPP2_CLS_LKP_FLOW_PTR(flow) … #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK … #define MVPP2_CLS_FLOW_INDEX_REG … #define MVPP2_CLS_FLOW_TBL0_REG … #define MVPP2_CLS_FLOW_TBL0_LAST … #define MVPP2_CLS_FLOW_TBL0_ENG_MASK … #define MVPP2_CLS_FLOW_TBL0_OFFS … #define MVPP2_CLS_FLOW_TBL0_ENG(x) … #define MVPP2_CLS_FLOW_TBL0_PORT_ID_MASK … #define MVPP2_CLS_FLOW_TBL0_PORT_ID(port) … #define MVPP2_CLS_FLOW_TBL0_PORT_ID_SEL … #define MVPP2_CLS_FLOW_TBL1_REG … #define MVPP2_CLS_FLOW_TBL1_N_FIELDS_MASK … #define MVPP2_CLS_FLOW_TBL1_N_FIELDS(x) … #define MVPP2_CLS_FLOW_TBL1_LU_TYPE(lu) … #define MVPP2_CLS_FLOW_TBL1_PRIO_MASK … #define MVPP2_CLS_FLOW_TBL1_PRIO(x) … #define MVPP2_CLS_FLOW_TBL1_SEQ_MASK … #define MVPP2_CLS_FLOW_TBL1_SEQ(x) … #define MVPP2_CLS_FLOW_TBL2_REG … #define MVPP2_CLS_FLOW_TBL2_FLD_MASK … #define MVPP2_CLS_FLOW_TBL2_FLD_OFFS(n) … #define MVPP2_CLS_FLOW_TBL2_FLD(n, x) … #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) … #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS … #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK … #define MVPP2_CLS_SWFWD_P2HQ_REG(port) … #define MVPP2_CLS_SWFWD_PCTRL_REG … #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) … /* Classifier C2 engine Registers */ #define MVPP22_CLS_C2_TCAM_IDX … #define MVPP22_CLS_C2_TCAM_DATA0 … #define MVPP22_CLS_C2_TCAM_DATA1 … #define MVPP22_CLS_C2_TCAM_DATA2 … #define MVPP22_CLS_C2_TCAM_DATA3 … #define MVPP22_CLS_C2_TCAM_DATA4 … #define MVPP22_CLS_C2_LU_TYPE(lu) … #define MVPP22_CLS_C2_PORT_ID(port) … #define MVPP22_CLS_C2_PORT_MASK … #define MVPP22_CLS_C2_TCAM_INV … #define MVPP22_CLS_C2_TCAM_INV_BIT … #define MVPP22_CLS_C2_HIT_CTR … #define MVPP22_CLS_C2_ACT … #define MVPP22_CLS_C2_ACT_RSS_EN(act) … #define MVPP22_CLS_C2_ACT_FWD(act) … #define MVPP22_CLS_C2_ACT_QHIGH(act) … #define MVPP22_CLS_C2_ACT_QLOW(act) … #define MVPP22_CLS_C2_ACT_COLOR(act) … #define MVPP22_CLS_C2_ATTR0 … #define MVPP22_CLS_C2_ATTR0_QHIGH(qh) … #define MVPP22_CLS_C2_ATTR0_QHIGH_MASK … #define MVPP22_CLS_C2_ATTR0_QHIGH_OFFS … #define MVPP22_CLS_C2_ATTR0_QLOW(ql) … #define MVPP22_CLS_C2_ATTR0_QLOW_MASK … #define MVPP22_CLS_C2_ATTR0_QLOW_OFFS … #define MVPP22_CLS_C2_ATTR1 … #define MVPP22_CLS_C2_ATTR2 … #define MVPP22_CLS_C2_ATTR2_RSS_EN … #define MVPP22_CLS_C2_ATTR3 … #define MVPP22_CLS_C2_TCAM_CTRL … #define MVPP22_CLS_C2_TCAM_BYPASS_FIFO … /* Descriptor Manager Top Registers */ #define MVPP2_RXQ_NUM_REG … #define MVPP2_RXQ_DESC_ADDR_REG … #define MVPP22_DESC_ADDR_OFFS … #define MVPP2_RXQ_DESC_SIZE_REG … #define MVPP2_RXQ_DESC_SIZE_MASK … #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) … #define MVPP2_RXQ_NUM_PROCESSED_OFFSET … #define MVPP2_RXQ_NUM_NEW_OFFSET … #define MVPP2_RXQ_STATUS_REG(rxq) … #define MVPP2_RXQ_OCCUPIED_MASK … #define MVPP2_RXQ_NON_OCCUPIED_OFFSET … #define MVPP2_RXQ_NON_OCCUPIED_MASK … #define MVPP2_RXQ_THRESH_REG … #define MVPP2_OCCUPIED_THRESH_OFFSET … #define MVPP2_OCCUPIED_THRESH_MASK … #define MVPP2_RXQ_INDEX_REG … #define MVPP2_TXQ_NUM_REG … #define MVPP2_TXQ_DESC_ADDR_REG … #define MVPP2_TXQ_DESC_SIZE_REG … #define MVPP2_TXQ_DESC_SIZE_MASK … #define MVPP2_TXQ_THRESH_REG … #define MVPP2_TXQ_THRESH_OFFSET … #define MVPP2_TXQ_THRESH_MASK … #define MVPP2_AGGR_TXQ_UPDATE_REG … #define MVPP2_TXQ_INDEX_REG … #define MVPP2_TXQ_PREF_BUF_REG … #define MVPP2_PREF_BUF_PTR(desc) … #define MVPP2_PREF_BUF_SIZE_4 … #define MVPP2_PREF_BUF_SIZE_16 … #define MVPP2_PREF_BUF_THRESH(val) … #define MVPP2_TXQ_DRAIN_EN_MASK … #define MVPP2_TXQ_PENDING_REG … #define MVPP2_TXQ_PENDING_MASK … #define MVPP2_TXQ_INT_STATUS_REG … #define MVPP2_TXQ_SENT_REG(txq) … #define MVPP2_TRANSMITTED_COUNT_OFFSET … #define MVPP2_TRANSMITTED_COUNT_MASK … #define MVPP2_TXQ_RSVD_REQ_REG … #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET … #define MVPP2_TXQ_RSVD_RSLT_REG … #define MVPP2_TXQ_RSVD_RSLT_MASK … #define MVPP2_TXQ_RSVD_CLR_REG … #define MVPP2_TXQ_RSVD_CLR_OFFSET … #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) … #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS … #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) … #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK … #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) … #define MVPP2_AGGR_TXQ_PENDING_MASK … #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) … /* MBUS bridge registers */ #define MVPP2_WIN_BASE(w) … #define MVPP2_WIN_SIZE(w) … #define MVPP2_WIN_REMAP(w) … #define MVPP2_BASE_ADDR_ENABLE … /* AXI Bridge Registers */ #define MVPP22_AXI_BM_WR_ATTR_REG … #define MVPP22_AXI_BM_RD_ATTR_REG … #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG … #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG … #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG … #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG … #define MVPP22_AXI_RX_DATA_WR_ATTR_REG … #define MVPP22_AXI_TX_DATA_RD_ATTR_REG … #define MVPP22_AXI_RD_NORMAL_CODE_REG … #define MVPP22_AXI_RD_SNOOP_CODE_REG … #define MVPP22_AXI_WR_NORMAL_CODE_REG … #define MVPP22_AXI_WR_SNOOP_CODE_REG … /* Values for AXI Bridge registers */ #define MVPP22_AXI_ATTR_CACHE_OFFS … #define MVPP22_AXI_ATTR_DOMAIN_OFFS … #define MVPP22_AXI_CODE_CACHE_OFFS … #define MVPP22_AXI_CODE_DOMAIN_OFFS … #define MVPP22_AXI_CODE_CACHE_NON_CACHE … #define MVPP22_AXI_CODE_CACHE_WR_CACHE … #define MVPP22_AXI_CODE_CACHE_RD_CACHE … #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM … #define MVPP22_AXI_CODE_DOMAIN_SYSTEM … /* Interrupt Cause and Mask registers */ #define MVPP2_ISR_TX_THRESHOLD_REG(port) … #define MVPP2_MAX_ISR_TX_THRESHOLD … #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) … #define MVPP2_MAX_ISR_RX_THRESHOLD … #define MVPP21_ISR_RXQ_GROUP_REG(port) … #define MVPP22_ISR_RXQ_GROUP_INDEX_REG … #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK … #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK … #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET … #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK … #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK … #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG … #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK … #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK … #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET … #define MVPP2_ISR_ENABLE_REG(port) … #define MVPP2_ISR_ENABLE_INTERRUPT(mask) … #define MVPP2_ISR_DISABLE_INTERRUPT(mask) … #define MVPP2_ISR_RX_TX_CAUSE_REG(port) … #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(version) … #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK … #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET … #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK … #define MVPP2_CAUSE_FCS_ERR_MASK … #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK … #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK … #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK … #define MVPP2_CAUSE_MISC_SUM_MASK … #define MVPP2_ISR_RX_TX_MASK_REG(port) … #define MVPP2_ISR_PON_RX_TX_MASK_REG … #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK … #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK … #define MVPP2_PON_CAUSE_MISC_SUM_MASK … #define MVPP2_ISR_MISC_CAUSE_REG … #define MVPP2_ISR_RX_ERR_CAUSE_REG(port) … #define MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK … /* Buffer Manager registers */ #define MVPP2_BM_POOL_BASE_REG(pool) … #define MVPP2_BM_POOL_BASE_ADDR_MASK … #define MVPP2_BM_POOL_SIZE_REG(pool) … #define MVPP2_BM_POOL_SIZE_MASK … #define MVPP2_BM_POOL_READ_PTR_REG(pool) … #define MVPP2_BM_POOL_GET_READ_PTR_MASK … #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) … #define MVPP2_BM_POOL_PTRS_NUM_MASK … #define MVPP2_BM_BPPI_READ_PTR_REG(pool) … #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) … #define MVPP2_BM_BPPI_PTR_NUM_MASK … #define MVPP22_BM_POOL_PTRS_NUM_MASK … #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK … #define MVPP2_BM_POOL_CTRL_REG(pool) … #define MVPP2_BM_START_MASK … #define MVPP2_BM_STOP_MASK … #define MVPP2_BM_STATE_MASK … #define MVPP2_BM_LOW_THRESH_OFFS … #define MVPP2_BM_LOW_THRESH_MASK … #define MVPP2_BM_LOW_THRESH_VALUE(val) … #define MVPP2_BM_HIGH_THRESH_OFFS … #define MVPP2_BM_HIGH_THRESH_MASK … #define MVPP2_BM_HIGH_THRESH_VALUE(val) … #define MVPP2_BM_BPPI_HIGH_THRESH … #define MVPP2_BM_BPPI_LOW_THRESH … #define MVPP23_BM_BPPI_HIGH_THRESH … #define MVPP23_BM_BPPI_LOW_THRESH … #define MVPP2_BM_INTR_CAUSE_REG(pool) … #define MVPP2_BM_RELEASED_DELAY_MASK … #define MVPP2_BM_ALLOC_FAILED_MASK … #define MVPP2_BM_BPPE_EMPTY_MASK … #define MVPP2_BM_BPPE_FULL_MASK … #define MVPP2_BM_AVAILABLE_BP_LOW_MASK … #define MVPP2_BM_INTR_MASK_REG(pool) … #define MVPP2_BM_PHY_ALLOC_REG(pool) … #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK … #define MVPP2_BM_VIRT_ALLOC_REG … #define MVPP22_BM_ADDR_HIGH_ALLOC … #define MVPP22_BM_ADDR_HIGH_PHYS_MASK … #define MVPP22_BM_ADDR_HIGH_VIRT_MASK … #define MVPP22_BM_ADDR_HIGH_VIRT_SHIFT … #define MVPP2_BM_PHY_RLS_REG(pool) … #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK … #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK … #define MVPP2_BM_PHY_RLS_GRNTD_MASK … #define MVPP2_BM_VIRT_RLS_REG … #define MVPP22_BM_ADDR_HIGH_RLS_REG … #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK … #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK … #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT … /* Packet Processor per-port counters */ #define MVPP2_OVERRUN_ETH_DROP … #define MVPP2_CLS_ETH_DROP … #define MVPP22_BM_POOL_BASE_ADDR_HIGH_REG … #define MVPP22_BM_POOL_BASE_ADDR_HIGH_MASK … #define MVPP23_BM_8POOL_MODE … /* Hit counters registers */ #define MVPP2_CTRS_IDX … #define MVPP22_CTRS_TX_CTR(port, txq) … #define MVPP2_TX_DESC_ENQ_CTR … #define MVPP2_TX_DESC_ENQ_TO_DDR_CTR … #define MVPP2_TX_BUFF_ENQ_TO_DDR_CTR … #define MVPP2_TX_DESC_ENQ_HW_FWD_CTR … #define MVPP2_RX_DESC_ENQ_CTR … #define MVPP2_TX_PKTS_DEQ_CTR … #define MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR … #define MVPP2_TX_PKTS_EARLY_DROP_CTR … #define MVPP2_TX_PKTS_BM_DROP_CTR … #define MVPP2_TX_PKTS_BM_MC_DROP_CTR … #define MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR … #define MVPP2_RX_PKTS_EARLY_DROP_CTR … #define MVPP2_RX_PKTS_BM_DROP_CTR … #define MVPP2_CLS_DEC_TBL_HIT_CTR … #define MVPP2_CLS_FLOW_TBL_HIT_CTR … /* TX Scheduler registers */ #define MVPP2_TXP_SCHED_PORT_INDEX_REG … #define MVPP2_TXP_SCHED_Q_CMD_REG … #define MVPP2_TXP_SCHED_ENQ_MASK … #define MVPP2_TXP_SCHED_DISQ_OFFSET … #define MVPP2_TXP_SCHED_CMD_1_REG … #define MVPP2_TXP_SCHED_FIXED_PRIO_REG … #define MVPP2_TXP_SCHED_PERIOD_REG … #define MVPP2_TXP_SCHED_MTU_REG … #define MVPP2_TXP_MTU_MAX … #define MVPP2_TXP_SCHED_REFILL_REG … #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK … #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK … #define MVPP2_TXP_REFILL_PERIOD_MASK(v) … #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG … #define MVPP2_TXP_TOKEN_SIZE_MAX … #define MVPP2_TXQ_SCHED_REFILL_REG(q) … #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK … #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK … #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) … #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) … #define MVPP2_TXQ_TOKEN_SIZE_MAX … #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) … #define MVPP2_TXQ_TOKEN_CNTR_MAX … /* TX general registers */ #define MVPP2_TX_SNOOP_REG … #define MVPP2_TX_PORT_FLUSH_REG … #define MVPP2_TX_PORT_FLUSH_MASK(port) … /* LMS registers */ #define MVPP2_SRC_ADDR_MIDDLE … #define MVPP2_SRC_ADDR_HIGH … #define MVPP2_PHY_AN_CFG0_REG … #define MVPP2_PHY_AN_STOP_SMI0_MASK … #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG … #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT … /* Per-port registers */ #define MVPP2_GMAC_CTRL_0_REG … #define MVPP2_GMAC_PORT_EN_MASK … #define MVPP2_GMAC_PORT_TYPE_MASK … #define MVPP2_GMAC_MAX_RX_SIZE_OFFS … #define MVPP2_GMAC_MAX_RX_SIZE_MASK … #define MVPP2_GMAC_MIB_CNTR_EN_MASK … #define MVPP2_GMAC_CTRL_1_REG … #define MVPP2_GMAC_PERIODIC_XON_EN_MASK … #define MVPP2_GMAC_GMII_LB_EN_MASK … #define MVPP2_GMAC_PCS_LB_EN_BIT … #define MVPP2_GMAC_PCS_LB_EN_MASK … #define MVPP2_GMAC_SA_LOW_OFFS … #define MVPP2_GMAC_CTRL_2_REG … #define MVPP2_GMAC_INBAND_AN_MASK … #define MVPP2_GMAC_FLOW_CTRL_MASK … #define MVPP2_GMAC_PCS_ENABLE_MASK … #define MVPP2_GMAC_INTERNAL_CLK_MASK … #define MVPP2_GMAC_DISABLE_PADDING … #define MVPP2_GMAC_PORT_RESET_MASK … #define MVPP2_GMAC_AUTONEG_CONFIG … #define MVPP2_GMAC_FORCE_LINK_DOWN … #define MVPP2_GMAC_FORCE_LINK_PASS … #define MVPP2_GMAC_IN_BAND_AUTONEG … #define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS … #define MVPP2_GMAC_IN_BAND_RESTART_AN … #define MVPP2_GMAC_CONFIG_MII_SPEED … #define MVPP2_GMAC_CONFIG_GMII_SPEED … #define MVPP2_GMAC_AN_SPEED_EN … #define MVPP2_GMAC_FC_ADV_EN … #define MVPP2_GMAC_FC_ADV_ASM_EN … #define MVPP2_GMAC_FLOW_CTRL_AUTONEG … #define MVPP2_GMAC_CONFIG_FULL_DUPLEX … #define MVPP2_GMAC_AN_DUPLEX_EN … #define MVPP2_GMAC_STATUS0 … #define MVPP2_GMAC_STATUS0_LINK_UP … #define MVPP2_GMAC_STATUS0_GMII_SPEED … #define MVPP2_GMAC_STATUS0_MII_SPEED … #define MVPP2_GMAC_STATUS0_FULL_DUPLEX … #define MVPP2_GMAC_STATUS0_RX_PAUSE … #define MVPP2_GMAC_STATUS0_TX_PAUSE … #define MVPP2_GMAC_STATUS0_AN_COMPLETE … #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG … #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS … #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK … #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) … #define MVPP22_GMAC_INT_STAT … #define MVPP22_GMAC_INT_STAT_LINK … #define MVPP22_GMAC_INT_MASK … #define MVPP22_GMAC_INT_MASK_LINK_STAT … #define MVPP22_GMAC_CTRL_4_REG … #define MVPP22_CTRL4_EXT_PIN_GMII_SEL … #define MVPP22_CTRL4_RX_FC_EN … #define MVPP22_CTRL4_TX_FC_EN … #define MVPP22_CTRL4_DP_CLK_SEL … #define MVPP22_CTRL4_SYNC_BYPASS_DIS … #define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE … #define MVPP22_GMAC_INT_SUM_STAT … #define MVPP22_GMAC_INT_SUM_STAT_INTERNAL … #define MVPP22_GMAC_INT_SUM_STAT_PTP … #define MVPP22_GMAC_INT_SUM_MASK … #define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT … #define MVPP22_GMAC_INT_SUM_MASK_PTP … /* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0, * relative to port->base. */ #define MVPP22_XLG_CTRL0_REG … #define MVPP22_XLG_CTRL0_PORT_EN … #define MVPP22_XLG_CTRL0_MAC_RESET_DIS … #define MVPP22_XLG_CTRL0_FORCE_LINK_DOWN … #define MVPP22_XLG_CTRL0_FORCE_LINK_PASS … #define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN … #define MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN … #define MVPP22_XLG_CTRL0_MIB_CNT_DIS … #define MVPP22_XLG_CTRL1_REG … #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS … #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK … #define MVPP22_XLG_STATUS … #define MVPP22_XLG_STATUS_LINK_UP … #define MVPP22_XLG_INT_STAT … #define MVPP22_XLG_INT_STAT_LINK … #define MVPP22_XLG_INT_MASK … #define MVPP22_XLG_INT_MASK_LINK … #define MVPP22_XLG_CTRL3_REG … #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK … #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC … #define MVPP22_XLG_CTRL3_MACMODESELECT_10G … #define MVPP22_XLG_EXT_INT_STAT … #define MVPP22_XLG_EXT_INT_STAT_XLG … #define MVPP22_XLG_EXT_INT_STAT_PTP … #define MVPP22_XLG_EXT_INT_MASK … #define MVPP22_XLG_EXT_INT_MASK_XLG … #define MVPP22_XLG_EXT_INT_MASK_GIG … #define MVPP22_XLG_EXT_INT_MASK_PTP … #define MVPP22_XLG_CTRL4_REG … #define MVPP22_XLG_CTRL4_FWD_FC … #define MVPP22_XLG_CTRL4_FWD_PFC … #define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC … #define MVPP22_XLG_CTRL4_EN_IDLE_CHECK … /* SMI registers. PPv2.2 and PPv2.3, relative to priv->iface_base. */ #define MVPP22_SMI_MISC_CFG_REG … #define MVPP22_SMI_POLLING_EN … /* TAI registers, PPv2.2 only, relative to priv->iface_base */ #define MVPP22_TAI_INT_CAUSE … #define MVPP22_TAI_INT_MASK … #define MVPP22_TAI_CR0 … #define MVPP22_TAI_CR1 … #define MVPP22_TAI_TCFCR0 … #define MVPP22_TAI_TCFCR1 … #define MVPP22_TAI_TCFCR2 … #define MVPP22_TAI_FATWR … #define MVPP22_TAI_TOD_STEP_NANO_CR … #define MVPP22_TAI_TOD_STEP_FRAC_HIGH … #define MVPP22_TAI_TOD_STEP_FRAC_LOW … #define MVPP22_TAI_TAPDC_HIGH … #define MVPP22_TAI_TAPDC_LOW … #define MVPP22_TAI_TGTOD_SEC_HIGH … #define MVPP22_TAI_TGTOD_SEC_MED … #define MVPP22_TAI_TGTOD_SEC_LOW … #define MVPP22_TAI_TGTOD_NANO_HIGH … #define MVPP22_TAI_TGTOD_NANO_LOW … #define MVPP22_TAI_TGTOD_FRAC_HIGH … #define MVPP22_TAI_TGTOD_FRAC_LOW … #define MVPP22_TAI_TLV_SEC_HIGH … #define MVPP22_TAI_TLV_SEC_MED … #define MVPP22_TAI_TLV_SEC_LOW … #define MVPP22_TAI_TLV_NANO_HIGH … #define MVPP22_TAI_TLV_NANO_LOW … #define MVPP22_TAI_TLV_FRAC_HIGH … #define MVPP22_TAI_TLV_FRAC_LOW … #define MVPP22_TAI_TCV0_SEC_HIGH … #define MVPP22_TAI_TCV0_SEC_MED … #define MVPP22_TAI_TCV0_SEC_LOW … #define MVPP22_TAI_TCV0_NANO_HIGH … #define MVPP22_TAI_TCV0_NANO_LOW … #define MVPP22_TAI_TCV0_FRAC_HIGH … #define MVPP22_TAI_TCV0_FRAC_LOW … #define MVPP22_TAI_TCV1_SEC_HIGH … #define MVPP22_TAI_TCV1_SEC_MED … #define MVPP22_TAI_TCV1_SEC_LOW … #define MVPP22_TAI_TCV1_NANO_HIGH … #define MVPP22_TAI_TCV1_NANO_LOW … #define MVPP22_TAI_TCV1_FRAC_HIGH … #define MVPP22_TAI_TCV1_FRAC_LOW … #define MVPP22_TAI_TCSR … #define MVPP22_TAI_TUC_LSB … #define MVPP22_TAI_GFM_SEC_HIGH … #define MVPP22_TAI_GFM_SEC_MED … #define MVPP22_TAI_GFM_SEC_LOW … #define MVPP22_TAI_GFM_NANO_HIGH … #define MVPP22_TAI_GFM_NANO_LOW … #define MVPP22_TAI_GFM_FRAC_HIGH … #define MVPP22_TAI_GFM_FRAC_LOW … #define MVPP22_TAI_PCLK_DA_HIGH … #define MVPP22_TAI_PCLK_DA_LOW … #define MVPP22_TAI_CTCR … #define MVPP22_TAI_PCLK_CCC_HIGH … #define MVPP22_TAI_PCLK_CCC_LOW … #define MVPP22_TAI_DTC_HIGH … #define MVPP22_TAI_DTC_LOW … #define MVPP22_TAI_CCC_HIGH … #define MVPP22_TAI_CCC_LOW … #define MVPP22_TAI_ICICE … #define MVPP22_TAI_ICICC_LOW … #define MVPP22_TAI_TUC_MSB … #define MVPP22_GMAC_BASE(port) … #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK … /* Descriptor ring Macros */ #define MVPP2_QUEUE_NEXT_DESC(q, index) … /* XPCS registers.PPv2.2 and PPv2.3 */ #define MVPP22_MPCS_BASE(port) … #define MVPP22_MPCS_CTRL … #define MVPP22_MPCS_CTRL_FWD_ERR_CONN … #define MVPP22_MPCS_CLK_RESET … #define MAC_CLK_RESET_SD_TX … #define MAC_CLK_RESET_SD_RX … #define MAC_CLK_RESET_MAC … #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) … #define MVPP22_MPCS_CLK_RESET_DIV_SET … /* FCA registers. PPv2.2 and PPv2.3 */ #define MVPP22_FCA_BASE(port) … #define MVPP22_FCA_REG_SIZE … #define MVPP22_FCA_REG_MASK … #define MVPP22_FCA_CONTROL_REG … #define MVPP22_FCA_ENABLE_PERIODIC … #define MVPP22_PERIODIC_COUNTER_LSB_REG … #define MVPP22_PERIODIC_COUNTER_MSB_REG … /* XPCS registers. PPv2.2 and PPv2.3 */ #define MVPP22_XPCS_BASE(port) … #define MVPP22_XPCS_CFG0 … #define MVPP22_XPCS_CFG0_RESET_DIS … #define MVPP22_XPCS_CFG0_PCS_MODE(n) … #define MVPP22_XPCS_CFG0_ACTIVE_LANE(n) … /* PTP registers. PPv2.2 only */ #define MVPP22_PTP_BASE(port) … #define MVPP22_PTP_INT_CAUSE … #define MVPP22_PTP_INT_CAUSE_QUEUE1 … #define MVPP22_PTP_INT_CAUSE_QUEUE0 … #define MVPP22_PTP_INT_MASK … #define MVPP22_PTP_INT_MASK_QUEUE1 … #define MVPP22_PTP_INT_MASK_QUEUE0 … #define MVPP22_PTP_GCR … #define MVPP22_PTP_GCR_RX_RESET … #define MVPP22_PTP_GCR_TX_RESET … #define MVPP22_PTP_GCR_TSU_ENABLE … #define MVPP22_PTP_TX_Q0_R0 … #define MVPP22_PTP_TX_Q0_R1 … #define MVPP22_PTP_TX_Q0_R2 … #define MVPP22_PTP_TX_Q1_R0 … #define MVPP22_PTP_TX_Q1_R1 … #define MVPP22_PTP_TX_Q1_R2 … #define MVPP22_PTP_TPCR … #define MVPP22_PTP_V1PCR … #define MVPP22_PTP_V2PCR … #define MVPP22_PTP_Y1731PCR … #define MVPP22_PTP_NTPTSPCR … #define MVPP22_PTP_NTPRXPCR … #define MVPP22_PTP_NTPTXPCR … #define MVPP22_PTP_WAMPPCR … #define MVPP22_PTP_NAPCR … #define MVPP22_PTP_FAPCR … #define MVPP22_PTP_CAPCR … #define MVPP22_PTP_ATAPCR … #define MVPP22_PTP_ACTAPCR … #define MVPP22_PTP_CATAPCR … #define MVPP22_PTP_CACTAPCR … #define MVPP22_PTP_AITAPCR … #define MVPP22_PTP_CAITAPCR … #define MVPP22_PTP_CITAPCR … #define MVPP22_PTP_NTP_OFF_HIGH … #define MVPP22_PTP_NTP_OFF_LOW … #define MVPP22_PTP_TX_PIPE_STATUS_DELAY … /* System controller registers. Accessed through a regmap. */ #define GENCONF_SOFT_RESET1 … #define GENCONF_SOFT_RESET1_GOP … #define GENCONF_PORT_CTRL0 … #define GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT … #define GENCONF_PORT_CTRL0_RX_DATA_SAMPLE … #define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR … #define GENCONF_PORT_CTRL1 … #define GENCONF_PORT_CTRL1_EN(p) … #define GENCONF_PORT_CTRL1_RESET(p) … #define GENCONF_CTRL0 … #define GENCONF_CTRL0_PORT2_RGMII … #define GENCONF_CTRL0_PORT3_RGMII_MII … #define GENCONF_CTRL0_PORT3_RGMII … /* Various constants */ /* Coalescing */ #define MVPP2_TXDONE_COAL_PKTS_THRESH … #define MVPP2_TXDONE_HRTIMER_PERIOD_NS … #define MVPP2_TXDONE_COAL_USEC … #define MVPP2_RX_COAL_PKTS … #define MVPP2_RX_COAL_USEC … /* The two bytes Marvell header. Either contains a special value used * by Marvell switches when a specific hardware mode is enabled (not * supported by this driver) or is filled automatically by zeroes on * the RX side. Those two bytes being at the front of the Ethernet * header, they allow to have the IP header aligned on a 4 bytes * boundary automatically: the hardware skips those two bytes on its * own. */ #define MVPP2_MH_SIZE … #define MVPP2_ETH_TYPE_LEN … #define MVPP2_PPPOE_HDR_SIZE … #define MVPP2_VLAN_TAG_LEN … #define MVPP2_VLAN_TAG_EDSA_LEN … /* Lbtd 802.3 type */ #define MVPP2_IP_LBDT_TYPE … #define MVPP2_TX_CSUM_MAX_SIZE … /* Timeout constants */ #define MVPP2_TX_DISABLE_TIMEOUT_MSEC … #define MVPP2_TX_PENDING_TIMEOUT_MSEC … #define MVPP2_TX_MTU_MAX … /* Maximum number of T-CONTs of PON port */ #define MVPP2_MAX_TCONT … /* Maximum number of supported ports */ #define MVPP2_MAX_PORTS … /* Loopback port index */ #define MVPP2_LOOPBACK_PORT_INDEX … /* Maximum number of TXQs used by single port */ #define MVPP2_MAX_TXQ … /* MVPP2_MAX_TSO_SEGS is the maximum number of fragments to allow in the GSO * skb. As we need a maxium of two descriptors per fragments (1 header, 1 data), * multiply this value by two to count the maximum number of skb descs needed. */ #define MVPP2_MAX_TSO_SEGS … #define MVPP2_MAX_SKB_DESCS … /* Max number of RXQs per port */ #define MVPP2_PORT_MAX_RXQ … /* Max number of Rx descriptors */ #define MVPP2_MAX_RXD_MAX … #define MVPP2_MAX_RXD_DFLT … /* Max number of Tx descriptors */ #define MVPP2_MAX_TXD_MAX … #define MVPP2_MAX_TXD_DFLT … /* Amount of Tx descriptors that can be reserved at once by CPU */ #define MVPP2_CPU_DESC_CHUNK … /* Max number of Tx descriptors in each aggregated queue */ #define MVPP2_AGGR_TXQ_SIZE … /* Descriptor aligned size */ #define MVPP2_DESC_ALIGNED_SIZE … /* Descriptor alignment mask */ #define MVPP2_TX_DESC_ALIGN … /* RX FIFO constants */ #define MVPP2_RX_FIFO_PORT_DATA_SIZE_44KB … #define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB … #define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB … #define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB … #define MVPP2_RX_FIFO_PORT_ATTR_SIZE(data_size) … #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB … #define MVPP2_RX_FIFO_PORT_MIN_PKT … /* TX FIFO constants */ #define MVPP22_TX_FIFO_DATA_SIZE_18KB … #define MVPP22_TX_FIFO_DATA_SIZE_10KB … #define MVPP22_TX_FIFO_DATA_SIZE_1KB … #define MVPP2_TX_FIFO_THRESHOLD_MIN … #define MVPP2_TX_FIFO_THRESHOLD(kb) … /* RX FIFO threshold in 1KB granularity */ #define MVPP23_PORT0_FIFO_TRSH … #define MVPP23_PORT1_FIFO_TRSH … #define MVPP23_PORT2_FIFO_TRSH … /* RX Flow Control Registers */ #define MVPP2_RX_FC_REG(port) … #define MVPP2_RX_FC_EN … #define MVPP2_RX_FC_TRSH_OFFS … #define MVPP2_RX_FC_TRSH_MASK … #define MVPP2_RX_FC_TRSH_UNIT … /* MSS Flow control */ #define MSS_FC_COM_REG … #define FLOW_CONTROL_ENABLE_BIT … #define FLOW_CONTROL_UPDATE_COMMAND_BIT … #define FC_QUANTA … #define FC_CLK_DIVIDER … #define MSS_RXQ_TRESH_BASE … #define MSS_RXQ_TRESH_OFFS … #define MSS_RXQ_TRESH_REG(q, fq) … #define MSS_BUF_POOL_BASE … #define MSS_BUF_POOL_OFFS … #define MSS_BUF_POOL_REG(id) … #define MSS_BUF_POOL_STOP_MASK … #define MSS_BUF_POOL_START_MASK … #define MSS_BUF_POOL_START_OFFS … #define MSS_BUF_POOL_PORTS_MASK … #define MSS_BUF_POOL_PORTS_OFFS … #define MSS_BUF_POOL_PORT_OFFS(id) … #define MSS_RXQ_TRESH_START_MASK … #define MSS_RXQ_TRESH_STOP_MASK … #define MSS_RXQ_TRESH_STOP_OFFS … #define MSS_RXQ_ASS_BASE … #define MSS_RXQ_ASS_OFFS … #define MSS_RXQ_ASS_PER_REG … #define MSS_RXQ_ASS_PER_OFFS … #define MSS_RXQ_ASS_PORTID_OFFS … #define MSS_RXQ_ASS_PORTID_MASK … #define MSS_RXQ_ASS_HOSTID_OFFS … #define MSS_RXQ_ASS_HOSTID_MASK … #define MSS_RXQ_ASS_Q_BASE(q, fq) … #define MSS_RXQ_ASS_PQ_BASE(q, fq) … #define MSS_RXQ_ASS_REG(q, fq) … #define MSS_THRESHOLD_STOP … #define MSS_THRESHOLD_START … #define MSS_FC_MAX_TIMEOUT … /* RX buffer constants */ #define MVPP2_SKB_SHINFO_SIZE … #define MVPP2_RX_PKT_SIZE(mtu) … #define MVPP2_RX_BUF_SIZE(pkt_size) … #define MVPP2_RX_TOTAL_SIZE(buf_size) … #define MVPP2_RX_MAX_PKT_SIZE(total_size) … #define MVPP2_MAX_RX_BUF_SIZE … #define MVPP2_BIT_TO_BYTE(bit) … #define MVPP2_BIT_TO_WORD(bit) … #define MVPP2_BIT_IN_WORD(bit) … #define MVPP2_N_PRS_FLOWS … #define MVPP2_N_RFS_ENTRIES_PER_FLOW … /* There are 7 supported high-level flows */ #define MVPP2_N_RFS_RULES … /* RSS constants */ #define MVPP22_N_RSS_TABLES … #define MVPP22_RSS_TABLE_ENTRIES … /* IPv6 max L3 address size */ #define MVPP2_MAX_L3_ADDR_SIZE … /* Port flags */ #define MVPP2_F_LOOPBACK … #define MVPP2_F_DT_COMPAT … /* Marvell tag types */ enum mvpp2_tag_type { … }; /* L2 cast enum */ enum mvpp2_prs_l2_cast { … }; /* L3 cast enum */ enum mvpp2_prs_l3_cast { … }; /* PTP descriptor constants. The low bits of the descriptor are stored * separately from the high bits. */ #define MVPP22_PTP_DESC_MASK_LOW … /* PTPAction */ enum mvpp22_ptp_action { … }; /* PTPPacketFormat */ enum mvpp22_ptp_packet_format { … }; #define MVPP22_PTP_ACTION(x) … #define MVPP22_PTP_PACKETFORMAT(x) … #define MVPP22_PTP_MACTIMESTAMPINGEN … #define MVPP22_PTP_TIMESTAMPENTRYID(x) … #define MVPP22_PTP_TIMESTAMPQUEUESELECT … /* BM constants */ #define MVPP2_BM_JUMBO_BUF_NUM … #define MVPP2_BM_LONG_BUF_NUM … #define MVPP2_BM_SHORT_BUF_NUM … #define MVPP2_BM_POOL_SIZE_MAX … #define MVPP2_BM_POOL_PTR_ALIGN … #define MVPP2_BM_MAX_POOLS … /* BM cookie (32 bits) definition */ #define MVPP2_BM_COOKIE_POOL_OFFS … #define MVPP2_BM_COOKIE_CPU_OFFS … #define MVPP2_BM_SHORT_FRAME_SIZE … #define MVPP2_BM_LONG_FRAME_SIZE … #define MVPP2_BM_JUMBO_FRAME_SIZE … /* BM short pool packet size * These value assure that for SWF the total number * of bytes allocated for each buffer will be 512 */ #define MVPP2_BM_SHORT_PKT_SIZE … #define MVPP2_BM_LONG_PKT_SIZE … #define MVPP2_BM_JUMBO_PKT_SIZE … #define MVPP21_ADDR_SPACE_SZ … #define MVPP22_ADDR_SPACE_SZ … #define MVPP2_MAX_THREADS … #define MVPP2_MAX_QVECS … /* GMAC MIB Counters register definitions */ #define MVPP21_MIB_COUNTERS_OFFSET … #define MVPP21_MIB_COUNTERS_PORT_SZ … #define MVPP22_MIB_COUNTERS_OFFSET … #define MVPP22_MIB_COUNTERS_PORT_SZ … #define MVPP2_MIB_GOOD_OCTETS_RCVD … #define MVPP2_MIB_BAD_OCTETS_RCVD … #define MVPP2_MIB_CRC_ERRORS_SENT … #define MVPP2_MIB_UNICAST_FRAMES_RCVD … #define MVPP2_MIB_BROADCAST_FRAMES_RCVD … #define MVPP2_MIB_MULTICAST_FRAMES_RCVD … #define MVPP2_MIB_FRAMES_64_OCTETS … #define MVPP2_MIB_FRAMES_65_TO_127_OCTETS … #define MVPP2_MIB_FRAMES_128_TO_255_OCTETS … #define MVPP2_MIB_FRAMES_256_TO_511_OCTETS … #define MVPP2_MIB_FRAMES_512_TO_1023_OCTETS … #define MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS … #define MVPP2_MIB_GOOD_OCTETS_SENT … #define MVPP2_MIB_UNICAST_FRAMES_SENT … #define MVPP2_MIB_MULTICAST_FRAMES_SENT … #define MVPP2_MIB_BROADCAST_FRAMES_SENT … #define MVPP2_MIB_FC_SENT … #define MVPP2_MIB_FC_RCVD … #define MVPP2_MIB_RX_FIFO_OVERRUN … #define MVPP2_MIB_UNDERSIZE_RCVD … #define MVPP2_MIB_FRAGMENTS_RCVD … #define MVPP2_MIB_OVERSIZE_RCVD … #define MVPP2_MIB_JABBER_RCVD … #define MVPP2_MIB_MAC_RCV_ERROR … #define MVPP2_MIB_BAD_CRC_EVENT … #define MVPP2_MIB_COLLISION … #define MVPP2_MIB_LATE_COLLISION … #define MVPP2_MIB_COUNTERS_STATS_DELAY … #define MVPP2_DESC_DMA_MASK … /* Buffer header info bits */ #define MVPP2_B_HDR_INFO_MC_ID_MASK … #define MVPP2_B_HDR_INFO_MC_ID(info) … #define MVPP2_B_HDR_INFO_LAST_OFFS … #define MVPP2_B_HDR_INFO_LAST_MASK … #define MVPP2_B_HDR_INFO_IS_LAST(info) … struct mvpp2_tai; /* Definitions */ struct mvpp2_dbgfs_entries; struct mvpp2_rss_table { … }; struct mvpp2_buff_hdr { … }; /* Shared Packet Processor resources */ struct mvpp2 { … }; struct mvpp2_pcpu_stats { … }; /* Per-CPU port control */ struct mvpp2_port_pcpu { … }; struct mvpp2_queue_vector { … }; /* Internal represention of a Flow Steering rule */ struct mvpp2_rfs_rule { … }; struct mvpp2_ethtool_fs { … }; struct mvpp2_hwtstamp_queue { … }; struct mvpp2_port { … }; /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the * layout of the transmit and reception DMA descriptors, and their * layout is therefore defined by the hardware design */ #define MVPP2_TXD_L3_OFF_SHIFT … #define MVPP2_TXD_IP_HLEN_SHIFT … #define MVPP2_TXD_L4_CSUM_FRAG … #define MVPP2_TXD_L4_CSUM_NOT … #define MVPP2_TXD_IP_CSUM_DISABLE … #define MVPP2_TXD_PADDING_DISABLE … #define MVPP2_TXD_L4_UDP … #define MVPP2_TXD_L3_IP6 … #define MVPP2_TXD_L_DESC … #define MVPP2_TXD_F_DESC … #define MVPP2_RXD_ERR_SUMMARY … #define MVPP2_RXD_ERR_CODE_MASK … #define MVPP2_RXD_ERR_CRC … #define MVPP2_RXD_ERR_OVERRUN … #define MVPP2_RXD_ERR_RESOURCE … #define MVPP2_RXD_BM_POOL_ID_OFFS … #define MVPP2_RXD_BM_POOL_ID_MASK … #define MVPP2_RXD_HWF_SYNC … #define MVPP2_RXD_L4_CSUM_OK … #define MVPP2_RXD_IP4_HEADER_ERR … #define MVPP2_RXD_L4_TCP … #define MVPP2_RXD_L4_UDP … #define MVPP2_RXD_L3_IP4 … #define MVPP2_RXD_L3_IP6 … #define MVPP2_RXD_BUF_HDR … /* HW TX descriptor for PPv2.1 */ struct mvpp21_tx_desc { … }; /* HW RX descriptor for PPv2.1 */ struct mvpp21_rx_desc { … }; /* HW TX descriptor for PPv2.2 and PPv2.3 */ struct mvpp22_tx_desc { … }; /* HW RX descriptor for PPv2.2 and PPv2.3 */ struct mvpp22_rx_desc { … }; /* Opaque type used by the driver to manipulate the HW TX and RX * descriptors */ struct mvpp2_tx_desc { … }; struct mvpp2_rx_desc { … }; enum mvpp2_tx_buf_type { … }; struct mvpp2_txq_pcpu_buf { … }; /* Per-CPU Tx queue control */ struct mvpp2_txq_pcpu { … }; struct mvpp2_tx_queue { … }; struct mvpp2_rx_queue { … }; struct mvpp2_bm_pool { … }; #define IS_TSO_HEADER(txq_pcpu, addr) … #define MVPP2_DRIVER_NAME … #define MVPP2_DRIVER_VERSION … void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data); u32 mvpp2_read(struct mvpp2 *priv, u32 offset); void mvpp2_dbgfs_init(struct mvpp2 *priv, const char *name); void mvpp2_dbgfs_cleanup(struct mvpp2 *priv); void mvpp2_dbgfs_exit(void); void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en); #ifdef CONFIG_MVPP2_PTP int mvpp22_tai_probe(struct device *dev, struct mvpp2 *priv); void mvpp22_tai_tstamp(struct mvpp2_tai *tai, u32 tstamp, struct skb_shared_hwtstamps *hwtstamp); void mvpp22_tai_start(struct mvpp2_tai *tai); void mvpp22_tai_stop(struct mvpp2_tai *tai); int mvpp22_tai_ptp_clock_index(struct mvpp2_tai *tai); #else static inline int mvpp22_tai_probe(struct device *dev, struct mvpp2 *priv) { return 0; } static inline void mvpp22_tai_tstamp(struct mvpp2_tai *tai, u32 tstamp, struct skb_shared_hwtstamps *hwtstamp) { } static inline void mvpp22_tai_start(struct mvpp2_tai *tai) { } static inline void mvpp22_tai_stop(struct mvpp2_tai *tai) { } static inline int mvpp22_tai_ptp_clock_index(struct mvpp2_tai *tai) { return -1; } #endif static inline bool mvpp22_rx_hwtstamping(struct mvpp2_port *port) { … } #endif
Codebase Browser
linux