/* SPDX-License-Identifier: GPL-2.0 */ /* * Header Parser definitions for Marvell PPv2 Network Controller * * Copyright (C) 2014 Marvell * * Marcin Wojtas <[email protected]> */ #ifndef _MVPP2_PRS_H_ #define _MVPP2_PRS_H_ #include <linux/kernel.h> #include <linux/netdevice.h> #include <linux/platform_device.h> #include "mvpp2.h" /* Parser constants */ #define MVPP2_PRS_TCAM_SRAM_SIZE … #define MVPP2_PRS_TCAM_WORDS … #define MVPP2_PRS_SRAM_WORDS … #define MVPP2_PRS_FLOW_ID_SIZE … #define MVPP2_PRS_FLOW_ID_MASK … #define MVPP2_PRS_TCAM_ENTRY_INVALID … #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT … #define MVPP2_PRS_IPV4_HEAD … #define MVPP2_PRS_IPV4_HEAD_MASK … #define MVPP2_PRS_IPV4_MC … #define MVPP2_PRS_IPV4_MC_MASK … #define MVPP2_PRS_IPV4_BC_MASK … #define MVPP2_PRS_IPV4_IHL_MIN … #define MVPP2_PRS_IPV4_IHL_MAX … #define MVPP2_PRS_IPV4_IHL_MASK … #define MVPP2_PRS_IPV6_MC … #define MVPP2_PRS_IPV6_MC_MASK … #define MVPP2_PRS_IPV6_HOP_MASK … #define MVPP2_PRS_TCAM_PROTO_MASK … #define MVPP2_PRS_TCAM_PROTO_MASK_L … #define MVPP2_PRS_DBL_VLANS_MAX … #define MVPP2_PRS_CAST_MASK … #define MVPP2_PRS_MCAST_VAL … #define MVPP2_PRS_UCAST_VAL … /* Tcam structure: * - lookup ID - 4 bits * - port ID - 1 byte * - additional information - 1 byte * - header data - 8 bytes * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0). */ #define MVPP2_PRS_AI_BITS … #define MVPP2_PRS_AI_MASK … #define MVPP2_PRS_PORT_MASK … #define MVPP2_PRS_LU_MASK … /* TCAM entries in registers are accessed using 16 data bits + 16 enable bits */ #define MVPP2_PRS_BYTE_TO_WORD(byte) … #define MVPP2_PRS_BYTE_IN_WORD(byte) … #define MVPP2_PRS_TCAM_EN(data) … #define MVPP2_PRS_TCAM_AI_WORD … #define MVPP2_PRS_TCAM_AI(ai) … #define MVPP2_PRS_TCAM_AI_EN(ai) … #define MVPP2_PRS_TCAM_PORT_WORD … #define MVPP2_PRS_TCAM_PORT(p) … #define MVPP2_PRS_TCAM_PORT_EN(p) … #define MVPP2_PRS_TCAM_LU_WORD … #define MVPP2_PRS_TCAM_LU(lu) … #define MVPP2_PRS_TCAM_LU_EN(lu) … #define MVPP2_PRS_TCAM_INV_WORD … #define MVPP2_PRS_VID_TCAM_BYTE … /* TCAM range for unicast and multicast filtering. We have 25 entries per port, * with 4 dedicated to UC filtering and the rest to multicast filtering. * Additionnally we reserve one entry for the broadcast address, and one for * each port's own address. */ #define MVPP2_PRS_MAC_UC_MC_FILT_MAX … #define MVPP2_PRS_MAC_RANGE_SIZE … /* Number of entries per port dedicated to UC and MC filtering */ #define MVPP2_PRS_MAC_UC_FILT_MAX … #define MVPP2_PRS_MAC_MC_FILT_MAX … /* There is a TCAM range reserved for VLAN filtering entries, range size is 33 * 10 VLAN ID filter entries per port * 1 default VLAN filter entry per port * It is assumed that there are 3 ports for filter, not including loopback port */ #define MVPP2_PRS_VLAN_FILT_MAX … #define MVPP2_PRS_VLAN_FILT_RANGE_SIZE … #define MVPP2_PRS_VLAN_FILT_MAX_ENTRY … #define MVPP2_PRS_VLAN_FILT_DFLT_ENTRY … /* Tcam entries ID */ #define MVPP2_PE_DROP_ALL … #define MVPP2_PE_FIRST_FREE_TID … /* MAC filtering range */ #define MVPP2_PE_MAC_RANGE_END … #define MVPP2_PE_MAC_RANGE_START … /* VLAN filtering range */ #define MVPP2_PE_VID_FILT_RANGE_END … #define MVPP2_PE_VID_FILT_RANGE_START … #define MVPP2_PE_LAST_FREE_TID … #define MVPP2_PE_MH_SKIP_PRS … #define MVPP2_PE_IP6_EXT_PROTO_UN … #define MVPP2_PE_IP6_ADDR_UN … #define MVPP2_PE_IP4_ADDR_UN … #define MVPP2_PE_LAST_DEFAULT_FLOW … #define MVPP2_PE_FIRST_DEFAULT_FLOW … #define MVPP2_PE_EDSA_TAGGED … #define MVPP2_PE_EDSA_UNTAGGED … #define MVPP2_PE_DSA_TAGGED … #define MVPP2_PE_DSA_UNTAGGED … #define MVPP2_PE_ETYPE_EDSA_TAGGED … #define MVPP2_PE_ETYPE_EDSA_UNTAGGED … #define MVPP2_PE_ETYPE_DSA_TAGGED … #define MVPP2_PE_ETYPE_DSA_UNTAGGED … #define MVPP2_PE_MH_DEFAULT … #define MVPP2_PE_DSA_DEFAULT … #define MVPP2_PE_IP6_PROTO_UN … #define MVPP2_PE_IP4_PROTO_UN … #define MVPP2_PE_ETH_TYPE_UN … #define MVPP2_PE_VID_FLTR_DEFAULT … #define MVPP2_PE_VID_EDSA_FLTR_DEFAULT … #define MVPP2_PE_VLAN_DBL … #define MVPP2_PE_VLAN_NONE … #define MVPP2_PE_FC_DROP … #define MVPP2_PE_MAC_MC_PROMISCUOUS … #define MVPP2_PE_MAC_UC_PROMISCUOUS … #define MVPP2_PE_MAC_NON_PROMISCUOUS … #define MVPP2_PRS_VID_PORT_FIRST(port) … #define MVPP2_PRS_VID_PORT_LAST(port) … /* Index of default vid filter for given port */ #define MVPP2_PRS_VID_PORT_DFLT(port) … /* Sram structure * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0). */ #define MVPP2_PRS_SRAM_RI_OFFS … #define MVPP2_PRS_SRAM_RI_WORD … #define MVPP2_PRS_SRAM_RI_CTRL_OFFS … #define MVPP2_PRS_SRAM_RI_CTRL_WORD … #define MVPP2_PRS_SRAM_RI_CTRL_BITS … #define MVPP2_PRS_SRAM_SHIFT_OFFS … #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT … #define MVPP2_PRS_SRAM_SHIFT_MASK … #define MVPP2_PRS_SRAM_UDF_OFFS … #define MVPP2_PRS_SRAM_UDF_BITS … #define MVPP2_PRS_SRAM_UDF_MASK … #define MVPP2_PRS_SRAM_UDF_SIGN_BIT … #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS … #define MVPP2_PRS_SRAM_UDF_TYPE_MASK … #define MVPP2_PRS_SRAM_UDF_TYPE_L3 … #define MVPP2_PRS_SRAM_UDF_TYPE_L4 … #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS … #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK … #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD … #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD … #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD … #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS … #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS … #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK … #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD … #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD … #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD … #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS … #define MVPP2_PRS_SRAM_AI_OFFS … #define MVPP2_PRS_SRAM_AI_CTRL_OFFS … #define MVPP2_PRS_SRAM_AI_CTRL_BITS … #define MVPP2_PRS_SRAM_AI_MASK … #define MVPP2_PRS_SRAM_NEXT_LU_OFFS … #define MVPP2_PRS_SRAM_NEXT_LU_MASK … #define MVPP2_PRS_SRAM_LU_DONE_BIT … #define MVPP2_PRS_SRAM_LU_GEN_BIT … /* Sram result info bits assignment */ #define MVPP2_PRS_RI_MAC_ME_MASK … #define MVPP2_PRS_RI_DSA_MASK … #define MVPP2_PRS_RI_VLAN_MASK … #define MVPP2_PRS_RI_VLAN_NONE … #define MVPP2_PRS_RI_VLAN_SINGLE … #define MVPP2_PRS_RI_VLAN_DOUBLE … #define MVPP2_PRS_RI_VLAN_TRIPLE … #define MVPP2_PRS_RI_CPU_CODE_MASK … #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC … #define MVPP2_PRS_RI_L2_CAST_MASK … #define MVPP2_PRS_RI_L2_UCAST … #define MVPP2_PRS_RI_L2_MCAST … #define MVPP2_PRS_RI_L2_BCAST … #define MVPP2_PRS_RI_PPPOE_MASK … #define MVPP2_PRS_RI_L3_PROTO_MASK … #define MVPP2_PRS_RI_L3_UN … #define MVPP2_PRS_RI_L3_IP4 … #define MVPP2_PRS_RI_L3_IP4_OPT … #define MVPP2_PRS_RI_L3_IP4_OTHER … #define MVPP2_PRS_RI_L3_IP6 … #define MVPP2_PRS_RI_L3_IP6_EXT … #define MVPP2_PRS_RI_L3_ARP … #define MVPP2_PRS_RI_L3_ADDR_MASK … #define MVPP2_PRS_RI_L3_UCAST … #define MVPP2_PRS_RI_L3_MCAST … #define MVPP2_PRS_RI_L3_BCAST … #define MVPP2_PRS_RI_IP_FRAG_MASK … #define MVPP2_PRS_RI_IP_FRAG_TRUE … #define MVPP2_PRS_RI_UDF3_MASK … #define MVPP2_PRS_RI_UDF3_RX_SPECIAL … #define MVPP2_PRS_RI_L4_PROTO_MASK … #define MVPP2_PRS_RI_L4_TCP … #define MVPP2_PRS_RI_L4_UDP … #define MVPP2_PRS_RI_L4_OTHER … #define MVPP2_PRS_RI_UDF7_MASK … #define MVPP2_PRS_RI_UDF7_IP6_LITE … #define MVPP2_PRS_RI_DROP_MASK … #define MVPP2_PRS_IP_MASK … /* Sram additional info bits assignment */ #define MVPP2_PRS_IPV4_DIP_AI_BIT … #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT … #define MVPP2_PRS_IPV6_EXT_AI_BIT … #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT … #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT … #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT … #define MVPP2_PRS_SINGLE_VLAN_AI … #define MVPP2_PRS_DBL_VLAN_AI_BIT … #define MVPP2_PRS_EDSA_VID_AI_BIT … /* DSA/EDSA type */ #define MVPP2_PRS_TAGGED … #define MVPP2_PRS_UNTAGGED … #define MVPP2_PRS_EDSA … #define MVPP2_PRS_DSA … /* MAC entries, shadow udf */ enum mvpp2_prs_udf { … }; /* Lookup ID */ enum mvpp2_prs_lookup { … }; struct mvpp2_prs_entry { … }; struct mvpp2_prs_result_info { … }; struct mvpp2_prs_shadow { … }; int mvpp2_prs_default_init(struct platform_device *pdev, struct mvpp2 *priv); int mvpp2_prs_init_from_hw(struct mvpp2 *priv, struct mvpp2_prs_entry *pe, int tid); unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe); void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, unsigned int offs, unsigned char *byte, unsigned char *enable); int mvpp2_prs_mac_da_accept(struct mvpp2_port *port, const u8 *da, bool add); int mvpp2_prs_tag_mode_set(struct mvpp2 *priv, int port, int type); int mvpp2_prs_add_flow(struct mvpp2 *priv, int flow, u32 ri, u32 ri_mask); int mvpp2_prs_def_flow(struct mvpp2_port *port); void mvpp2_prs_vid_enable_filtering(struct mvpp2_port *port); void mvpp2_prs_vid_disable_filtering(struct mvpp2_port *port); int mvpp2_prs_vid_entry_add(struct mvpp2_port *port, u16 vid); void mvpp2_prs_vid_entry_remove(struct mvpp2_port *port, u16 vid); void mvpp2_prs_vid_remove_all(struct mvpp2_port *port); void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, enum mvpp2_prs_l2_cast l2_cast, bool add); void mvpp2_prs_mac_del_all(struct mvpp2_port *port); int mvpp2_prs_update_mac_da(struct net_device *dev, const u8 *da); int mvpp2_prs_hits(struct mvpp2 *priv, int index); #endif
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