/* SPDX-License-Identifier: GPL-2.0 */ /* Marvell Octeon EP (EndPoint) Ethernet Driver * * Copyright (C) 2020 Marvell. * */ #ifndef _OCTEP_CONFIG_H_ #define _OCTEP_CONFIG_H_ /* Tx instruction types by length */ #define OCTEP_32BYTE_INSTR … #define OCTEP_64BYTE_INSTR … /* Tx Queue: maximum descriptors per ring */ /* This needs to be a power of 2 */ #define OCTEP_IQ_MAX_DESCRIPTORS … /* Minimum input (Tx) requests to be enqueued to ring doorbell */ #define OCTEP_DB_MIN … /* Packet threshold for Tx queue interrupt */ #define OCTEP_IQ_INTR_THRESHOLD … /* Minimum watermark for backpressure */ #define OCTEP_OQ_WMARK_MIN … /* Rx Queue: maximum descriptors per ring */ #define OCTEP_OQ_MAX_DESCRIPTORS … /* Rx buffer size: Use page size buffers. * Build skb from allocated page buffer once the packet is received. * When a gathered packet is received, make head page as skb head and * page buffers in consecutive Rx descriptors as fragments. */ #define OCTEP_OQ_BUF_SIZE … #define OCTEP_OQ_PKTS_PER_INTR … #define OCTEP_OQ_REFILL_THRESHOLD … #define OCTEP_OQ_INTR_PKT_THRESHOLD … #define OCTEP_OQ_INTR_TIME_THRESHOLD … #define OCTEP_MSIX_NAME_SIZE … /* Tx Queue wake threshold * wakeup a stopped Tx queue if minimum 2 descriptors are available. * Even a skb with fragments consume only one Tx queue descriptor entry. */ #define OCTEP_WAKE_QUEUE_THRESHOLD … /* Minimum MTU supported by Octeon network interface */ #define OCTEP_MIN_MTU … /* Default MTU */ #define OCTEP_DEFAULT_MTU … /* pf heartbeat interval in milliseconds */ #define OCTEP_DEFAULT_FW_HB_INTERVAL … /* pf heartbeat miss count */ #define OCTEP_DEFAULT_FW_HB_MISS_COUNT … /* Macros to get octeon config params */ #define CFG_GET_IQ_CFG(cfg) … #define CFG_GET_IQ_NUM_DESC(cfg) … #define CFG_GET_IQ_INSTR_TYPE(cfg) … #define CFG_GET_IQ_INSTR_SIZE(cfg) … #define CFG_GET_IQ_DB_MIN(cfg) … #define CFG_GET_IQ_INTR_THRESHOLD(cfg) … #define CFG_GET_OQ_NUM_DESC(cfg) … #define CFG_GET_OQ_BUF_SIZE(cfg) … #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) … #define CFG_GET_OQ_INTR_PKT(cfg) … #define CFG_GET_OQ_INTR_TIME(cfg) … #define CFG_GET_OQ_WMARK(cfg) … #define CFG_GET_PORTS_MAX_IO_RINGS(cfg) … #define CFG_GET_PORTS_ACTIVE_IO_RINGS(cfg) … #define CFG_GET_PORTS_PF_SRN(cfg) … #define CFG_GET_CORE_TICS_PER_US(cfg) … #define CFG_GET_COPROC_TICS_PER_US(cfg) … #define CFG_GET_MAX_VFS(cfg) … #define CFG_GET_ACTIVE_VFS(cfg) … #define CFG_GET_MAX_RPVF(cfg) … #define CFG_GET_ACTIVE_RPVF(cfg) … #define CFG_GET_VF_SRN(cfg) … #define CFG_GET_IOQ_MSIX(cfg) … #define CFG_GET_NON_IOQ_MSIX(cfg) … #define CFG_GET_NON_IOQ_MSIX_NAMES(cfg) … #define CFG_GET_CTRL_MBOX_MEM_ADDR(cfg) … /* Hardware Tx Queue configuration. */ struct octep_iq_config { … }; /* Hardware Rx Queue configuration. */ struct octep_oq_config { … }; /* Tx/Rx configuration */ struct octep_pf_ring_config { … }; /* Octeon Hardware SRIOV config */ struct octep_sriov_config { … }; /* Octeon MSI-x config. */ struct octep_msix_config { … }; struct octep_ctrl_mbox_config { … }; /* Info from firmware */ struct octep_fw_info { … }; /* Data Structure to hold configuration limits and active config */ struct octep_config { … }; #endif /* _OCTEP_CONFIG_H_ */
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