/* SPDX-License-Identifier: GPL-2.0 */ /* Marvell Octeon EP (EndPoint) Ethernet Driver * * Copyright (C) 2020 Marvell. * */ #ifndef _OCTEP_MAIN_H_ #define _OCTEP_MAIN_H_ #include "octep_tx.h" #include "octep_rx.h" #include "octep_ctrl_mbox.h" #define OCTEP_DRV_NAME … #define OCTEP_DRV_STRING … #define OCTEP_PCIID_CN93_PF … #define OCTEP_PCIID_CN93_VF … #define OCTEP_PCI_DEVICE_ID_CN98_PF … #define OCTEP_PCI_DEVICE_ID_CN93_PF … #define OCTEP_PCI_DEVICE_ID_CN93_VF … #define OCTEP_PCI_DEVICE_ID_CNF95N_PF … #define OCTEP_PCI_DEVICE_ID_CN10KA_PF … #define OCTEP_PCI_DEVICE_ID_CNF10KA_PF … #define OCTEP_PCI_DEVICE_ID_CNF10KB_PF … #define OCTEP_PCI_DEVICE_ID_CN10KB_PF … #define OCTEP_MAX_QUEUES … #define OCTEP_MAX_IQ … #define OCTEP_MAX_OQ … #define OCTEP_MAX_VF … #define OCTEP_MAX_MSIX_VECTORS … /* Flags to disable and enable Interrupts */ #define OCTEP_INPUT_INTR … #define OCTEP_OUTPUT_INTR … #define OCTEP_MBOX_INTR … #define OCTEP_ALL_INTR … #define OCTEP_IQ_INTR_RESEND_BIT … #define OCTEP_OQ_INTR_RESEND_BIT … #define OCTEP_MMIO_REGIONS … #define IQ_INSTR_PENDING(iq) … #define IQ_INSTR_SPACE(iq) … /* PCI address space mapping information. * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of * Octeon gets mapped to different physical address spaces in * the kernel. */ struct octep_mmio { … }; struct octep_pci_win_regs { … }; struct octep_hw_ops { … }; /* Octeon mailbox data */ struct octep_mbox_data { … }; #define MAX_VF_PF_MBOX_DATA_SIZE … /* wrappers around work structs */ struct octep_pfvf_mbox_wk { … }; /* Octeon device mailbox */ struct octep_mbox { … }; /* Tx/Rx queue vector per interrupt. */ struct octep_ioq_vector { … }; /* Octeon hardware/firmware offload capability flags. */ #define OCTEP_CAP_TX_CHECKSUM … #define OCTEP_CAP_RX_CHECKSUM … #define OCTEP_CAP_TSO … /* Link modes */ enum octep_link_mode_bit_indices { … }; /* Hardware interface link state information. */ struct octep_iface_link_info { … }; /* The Octeon VF device specific info data structure.*/ struct octep_pfvf_info { … }; /* The Octeon device specific private data structure. * Each Octeon device has this structure to represent all its components. */ struct octep_device { … }; static inline u16 OCTEP_MAJOR_REV(struct octep_device *oct) { … } static inline u16 OCTEP_MINOR_REV(struct octep_device *oct) { … } /* Octeon CSR read/write access APIs */ #define octep_write_csr(octep_dev, reg_off, value) … #define octep_write_csr64(octep_dev, reg_off, val64) … #define octep_read_csr(octep_dev, reg_off) … #define octep_read_csr64(octep_dev, reg_off) … /* Read windowed register. * @param oct - pointer to the Octeon device. * @param addr - Address of the register to read. * * This routine is called to read from the indirectly accessed * Octeon registers that are visible through a PCI BAR0 mapped window * register. * @return - 64 bit value read from the register. */ static inline u64 OCTEP_PCI_WIN_READ(struct octep_device *oct, u64 addr) { … } /* Write windowed register. * @param oct - pointer to the Octeon device. * @param addr - Address of the register to write * @param val - Value to write * * This routine is called to write to the indirectly accessed * Octeon registers that are visible through a PCI BAR0 mapped window * register. * @return Nothing. */ static inline void OCTEP_PCI_WIN_WRITE(struct octep_device *oct, u64 addr, u64 val) { … } extern struct workqueue_struct *octep_wq; int octep_device_setup(struct octep_device *oct); int octep_setup_iqs(struct octep_device *oct); void octep_free_iqs(struct octep_device *oct); void octep_clean_iqs(struct octep_device *oct); int octep_setup_oqs(struct octep_device *oct); void octep_free_oqs(struct octep_device *oct); void octep_oq_dbell_init(struct octep_device *oct); void octep_device_setup_cn93_pf(struct octep_device *oct); void octep_device_setup_cnxk_pf(struct octep_device *oct); int octep_iq_process_completions(struct octep_iq *iq, u16 budget); int octep_oq_process_rx(struct octep_oq *oq, int budget); void octep_set_ethtool_ops(struct net_device *netdev); #endif /* _OCTEP_MAIN_H_ */
Codebase Browser
linux