/* SPDX-License-Identifier: GPL-2.0 */ /* Marvell Octeon EP (EndPoint) Ethernet Driver * * Copyright (C) 2020 Marvell. * */ #ifndef _OCTEP_REGS_CNXK_PF_H_ #define _OCTEP_REGS_CNXK_PF_H_ /* ############################ RST ######################### */ #define CNXK_RST_BOOT … #define CNXK_RST_CHIP_DOMAIN_W1S … #define CNXK_RST_CORE_DOMAIN_W1S … #define CNXK_RST_CORE_DOMAIN_W1C … #define CNXK_CONFIG_XPANSION_BAR … #define CNXK_CONFIG_PCIE_CAP … #define CNXK_CONFIG_PCIE_DEVCAP … #define CNXK_CONFIG_PCIE_DEVCTL … #define CNXK_CONFIG_PCIE_LINKCAP … #define CNXK_CONFIG_PCIE_LINKCTL … #define CNXK_CONFIG_PCIE_SLOTCAP … #define CNXK_CONFIG_PCIE_SLOTCTL … #define CNXK_PCIE_SRIOV_FDL … #define CNXK_PCIE_SRIOV_FDL_BIT_POS … #define CNXK_PCIE_SRIOV_FDL_MASK … #define CNXK_CONFIG_PCIE_FLTMSK … /* ################# Offsets of RING, EPF, MAC ######################### */ #define CNXK_RING_OFFSET … #define CNXK_EPF_OFFSET … #define CNXK_MAC_OFFSET … #define CNXK_BIT_ARRAY_OFFSET … #define CNXK_EPVF_RING_OFFSET … /* ################# Scratch Registers ######################### */ #define CNXK_SDP_EPF_SCRATCH … /* ################# Window Registers ######################### */ #define CNXK_SDP_WIN_WR_ADDR64 … #define CNXK_SDP_WIN_RD_ADDR64 … #define CNXK_SDP_WIN_WR_DATA64 … #define CNXK_SDP_WIN_WR_MASK_REG … #define CNXK_SDP_WIN_RD_DATA64 … #define CNXK_SDP_MAC_NUMBER … /* ################# Global Previliged registers ######################### */ #define CNXK_SDP_EPF_RINFO … #define CNXK_SDP_EPF_RINFO_SRN(val) … #define CNXK_SDP_EPF_RINFO_RPVF(val) … #define CNXK_SDP_EPF_RINFO_NVFS(val) … /* SDP Function select */ #define CNXK_SDP_FUNC_SEL_EPF_BIT_POS … #define CNXK_SDP_FUNC_SEL_FUNC_BIT_POS … /* ##### RING IN (Into device from PCI: Tx Ring) REGISTERS #### */ #define CNXK_SDP_R_IN_CONTROL_START … #define CNXK_SDP_R_IN_ENABLE_START … #define CNXK_SDP_R_IN_INSTR_BADDR_START … #define CNXK_SDP_R_IN_INSTR_RSIZE_START … #define CNXK_SDP_R_IN_INSTR_DBELL_START … #define CNXK_SDP_R_IN_CNTS_START … #define CNXK_SDP_R_IN_INT_LEVELS_START … #define CNXK_SDP_R_IN_PKT_CNT_START … #define CNXK_SDP_R_IN_BYTE_CNT_START … #define CNXK_SDP_R_IN_CONTROL(ring) … #define CNXK_SDP_R_IN_ENABLE(ring) … #define CNXK_SDP_R_IN_INSTR_BADDR(ring) … #define CNXK_SDP_R_IN_INSTR_RSIZE(ring) … #define CNXK_SDP_R_IN_INSTR_DBELL(ring) … #define CNXK_SDP_R_IN_CNTS(ring) … #define CNXK_SDP_R_IN_INT_LEVELS(ring) … #define CNXK_SDP_R_IN_PKT_CNT(ring) … #define CNXK_SDP_R_IN_BYTE_CNT(ring) … /* Rings per Virtual Function */ #define CNXK_R_IN_CTL_RPVF_MASK … #define CNXK_R_IN_CTL_RPVF_POS … /* Number of instructions to be read in one MAC read request. * setting to Max value(4) */ #define CNXK_R_IN_CTL_IDLE … #define CNXK_R_IN_CTL_RDSIZE … #define CNXK_R_IN_CTL_IS_64B … #define CNXK_R_IN_CTL_D_NSR … #define CNXK_R_IN_CTL_D_ESR … #define CNXK_R_IN_CTL_D_ROR … #define CNXK_R_IN_CTL_NSR … #define CNXK_R_IN_CTL_ESR … #define CNXK_R_IN_CTL_ROR … #define CNXK_R_IN_CTL_MASK … /* ##### RING OUT (out from device to PCI host: Rx Ring) REGISTERS #### */ #define CNXK_SDP_R_OUT_CNTS_START … #define CNXK_SDP_R_OUT_INT_LEVELS_START … #define CNXK_SDP_R_OUT_SLIST_BADDR_START … #define CNXK_SDP_R_OUT_SLIST_RSIZE_START … #define CNXK_SDP_R_OUT_SLIST_DBELL_START … #define CNXK_SDP_R_OUT_CONTROL_START … #define CNXK_SDP_R_OUT_WMARK_START … #define CNXK_SDP_R_OUT_ENABLE_START … #define CNXK_SDP_R_OUT_PKT_CNT_START … #define CNXK_SDP_R_OUT_BYTE_CNT_START … #define CNXK_SDP_R_OUT_CONTROL(ring) … #define CNXK_SDP_R_OUT_ENABLE(ring) … #define CNXK_SDP_R_OUT_SLIST_BADDR(ring) … #define CNXK_SDP_R_OUT_SLIST_RSIZE(ring) … #define CNXK_SDP_R_OUT_SLIST_DBELL(ring) … #define CNXK_SDP_R_OUT_WMARK(ring) … #define CNXK_SDP_R_OUT_CNTS(ring) … #define CNXK_SDP_R_OUT_INT_LEVELS(ring) … #define CNXK_SDP_R_OUT_PKT_CNT(ring) … #define CNXK_SDP_R_OUT_BYTE_CNT(ring) … /*------------------ R_OUT Masks ----------------*/ #define CNXK_R_OUT_INT_LEVELS_BMODE … #define CNXK_R_OUT_INT_LEVELS_TIMET … #define CNXK_R_OUT_CTL_IDLE … #define CNXK_R_OUT_CTL_ES_I … #define CNXK_R_OUT_CTL_NSR_I … #define CNXK_R_OUT_CTL_ROR_I … #define CNXK_R_OUT_CTL_ES_D … #define CNXK_R_OUT_CTL_NSR_D … #define CNXK_R_OUT_CTL_ROR_D … #define CNXK_R_OUT_CTL_ES_P … #define CNXK_R_OUT_CTL_NSR_P … #define CNXK_R_OUT_CTL_ROR_P … #define CNXK_R_OUT_CTL_IMODE … /* ############### Interrupt Moderation Registers ############### */ #define CNXK_SDP_R_IN_INT_MDRT_CTL0_START … #define CNXK_SDP_R_IN_INT_MDRT_CTL1_START … #define CNXK_SDP_R_IN_INT_MDRT_DBG_START … #define CNXK_SDP_R_OUT_INT_MDRT_CTL0_START … #define CNXK_SDP_R_OUT_INT_MDRT_CTL1_START … #define CNXK_SDP_R_OUT_INT_MDRT_DBG_START … #define CNXK_SDP_R_MBOX_ISM_START … #define CNXK_SDP_R_OUT_CNTS_ISM_START … #define CNXK_SDP_R_IN_CNTS_ISM_START … #define CNXK_SDP_R_IN_INT_MDRT_CTL0(ring) … #define CNXK_SDP_R_IN_INT_MDRT_CTL1(ring) … #define CNXK_SDP_R_IN_INT_MDRT_DBG(ring) … #define CNXK_SDP_R_OUT_INT_MDRT_CTL0(ring) … #define CNXK_SDP_R_OUT_INT_MDRT_CTL1(ring) … #define CNXK_SDP_R_OUT_INT_MDRT_DBG(ring) … #define CNXK_SDP_R_MBOX_ISM(ring) … #define CNXK_SDP_R_OUT_CNTS_ISM(ring) … #define CNXK_SDP_R_IN_CNTS_ISM(ring) … /* ##################### Mail Box Registers ########################## */ /* INT register for VF. when a MBOX write from PF happed to a VF, * corresponding bit will be set in this register as well as in * PF_VF_INT register. * * This is a RO register, the int can be cleared by writing 1 to PF_VF_INT */ /* Basically first 3 are from PF to VF. The last one is data from VF to PF */ #define CNXK_SDP_R_MBOX_PF_VF_DATA_START … #define CNXK_SDP_R_MBOX_PF_VF_INT_START … #define CNXK_SDP_R_MBOX_VF_PF_DATA_START … #define CNXK_SDP_MBOX_VF_PF_DATA_START … #define CNXK_SDP_MBOX_PF_VF_DATA_START … #define CNXK_SDP_R_MBOX_PF_VF_DATA(ring) … #define CNXK_SDP_R_MBOX_PF_VF_INT(ring) … #define CNXK_SDP_R_MBOX_VF_PF_DATA(ring) … #define CNXK_SDP_MBOX_VF_PF_DATA(ring) … #define CNXK_SDP_MBOX_PF_VF_DATA(ring) … /* ##################### Interrupt Registers ########################## */ #define CNXK_SDP_R_ERR_TYPE_START … #define CNXK_SDP_R_ERR_TYPE(ring) … #define CNXK_SDP_R_MBOX_ISM_START … #define CNXK_SDP_R_OUT_CNTS_ISM_START … #define CNXK_SDP_R_IN_CNTS_ISM_START … #define CNXK_SDP_R_MBOX_ISM(ring) … #define CNXK_SDP_R_OUT_CNTS_ISM(ring) … #define CNXK_SDP_R_IN_CNTS_ISM(ring) … #define CNXK_SDP_EPF_MBOX_RINT_START … #define CNXK_SDP_EPF_MBOX_RINT_W1S_START … #define CNXK_SDP_EPF_MBOX_RINT_ENA_W1C_START … #define CNXK_SDP_EPF_MBOX_RINT_ENA_W1S_START … #define CNXK_SDP_EPF_VFIRE_RINT_START … #define CNXK_SDP_EPF_VFIRE_RINT_W1S_START … #define CNXK_SDP_EPF_VFIRE_RINT_ENA_W1C_START … #define CNXK_SDP_EPF_VFIRE_RINT_ENA_W1S_START … #define CNXK_SDP_EPF_IRERR_RINT … #define CNXK_SDP_EPF_IRERR_RINT_W1S … #define CNXK_SDP_EPF_IRERR_RINT_ENA_W1C … #define CNXK_SDP_EPF_IRERR_RINT_ENA_W1S … #define CNXK_SDP_EPF_VFORE_RINT_START … #define CNXK_SDP_EPF_VFORE_RINT_W1S_START … #define CNXK_SDP_EPF_VFORE_RINT_ENA_W1C_START … #define CNXK_SDP_EPF_VFORE_RINT_ENA_W1S_START … #define CNXK_SDP_EPF_ORERR_RINT … #define CNXK_SDP_EPF_ORERR_RINT_W1S … #define CNXK_SDP_EPF_ORERR_RINT_ENA_W1C … #define CNXK_SDP_EPF_ORERR_RINT_ENA_W1S … #define CNXK_SDP_EPF_OEI_RINT … #define CNXK_SDP_EPF_OEI_RINT_W1S … #define CNXK_SDP_EPF_OEI_RINT_ENA_W1C … #define CNXK_SDP_EPF_OEI_RINT_ENA_W1S … #define CNXK_SDP_EPF_DMA_RINT … #define CNXK_SDP_EPF_DMA_RINT_W1S … #define CNXK_SDP_EPF_DMA_RINT_ENA_W1C … #define CNXK_SDP_EPF_DMA_RINT_ENA_W1S … #define CNXK_SDP_EPF_DMA_INT_LEVEL_START … #define CNXK_SDP_EPF_DMA_CNT_START … #define CNXK_SDP_EPF_DMA_TIM_START … #define CNXK_SDP_EPF_MISC_RINT … #define CNXK_SDP_EPF_MISC_RINT_W1S … #define CNXK_SDP_EPF_MISC_RINT_ENA_W1C … #define CNXK_SDP_EPF_MISC_RINT_ENA_W1S … #define CNXK_SDP_EPF_DMA_VF_RINT_START … #define CNXK_SDP_EPF_DMA_VF_RINT_W1S_START … #define CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1C_START … #define CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1S_START … #define CNXK_SDP_EPF_PP_VF_RINT_START … #define CNXK_SDP_EPF_PP_VF_RINT_W1S_START … #define CNXK_SDP_EPF_PP_VF_RINT_ENA_W1C_START … #define CNXK_SDP_EPF_PP_VF_RINT_ENA_W1S_START … #define CNXK_SDP_EPF_MBOX_RINT(index) … #define CNXK_SDP_EPF_MBOX_RINT_W1S(index) … #define CNXK_SDP_EPF_MBOX_RINT_ENA_W1C(index) … #define CNXK_SDP_EPF_MBOX_RINT_ENA_W1S(index) … #define CNXK_SDP_EPF_VFIRE_RINT(index) … #define CNXK_SDP_EPF_VFIRE_RINT_W1S(index) … #define CNXK_SDP_EPF_VFIRE_RINT_ENA_W1C(index) … #define CNXK_SDP_EPF_VFIRE_RINT_ENA_W1S(index) … #define CNXK_SDP_EPF_VFORE_RINT(index) … #define CNXK_SDP_EPF_VFORE_RINT_W1S(index) … #define CNXK_SDP_EPF_VFORE_RINT_ENA_W1C(index) … #define CNXK_SDP_EPF_VFORE_RINT_ENA_W1S(index) … #define CNXK_SDP_EPF_DMA_VF_RINT(index) … #define CNXK_SDP_EPF_DMA_VF_RINT_W1S(index) … #define CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1C(index) … #define CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1S(index) … #define CNXK_SDP_EPF_PP_VF_RINT(index) … #define CNXK_SDP_EPF_PP_VF_RINT_W1S(index) … #define CNXK_SDP_EPF_PP_VF_RINT_ENA_W1C(index) … #define CNXK_SDP_EPF_PP_VF_RINT_ENA_W1S(index) … /*------------------ Interrupt Masks ----------------*/ #define CNXK_INTR_R_SEND_ISM … #define CNXK_INTR_R_OUT_INT … #define CNXK_INTR_R_IN_INT … #define CNXK_INTR_R_MBOX_INT … #define CNXK_INTR_R_RESEND … #define CNXK_INTR_R_CLR_TIM … /* ####################### Ring Mapping Registers ################################## */ #define CNXK_SDP_EPVF_RING_START … #define CNXK_SDP_IN_RING_TB_MAP_START … #define CNXK_SDP_IN_RATE_LIMIT_START … #define CNXK_SDP_MAC_PF_RING_CTL_START … #define CNXK_SDP_EPVF_RING(ring) … #define CNXK_SDP_IN_RING_TB_MAP(ring) … #define CNXK_SDP_IN_RATE_LIMIT(ring) … #define CNXK_SDP_MAC_PF_RING_CTL(mac) … #define CNXK_SDP_MAC_PF_RING_CTL_NPFS(val) … #define CNXK_SDP_MAC_PF_RING_CTL_SRN(val) … #define CNXK_SDP_MAC_PF_RING_CTL_RPPF(val) … /* Number of non-queue interrupts in CNXKxx */ #define CNXK_NUM_NON_IOQ_INTR … /* bit 0 for control mbox interrupt */ #define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_MBOX … /* bit 1 for firmware heartbeat interrupt */ #define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT … #define FW_STATUS_RUNNING … #define CNXK_PEMX_PFX_CSX_PFCFGX(pem, pf, offset) … /* Register defines for use with CNXK_PEMX_PFX_CSX_PFCFGX */ #define CNXK_PCIEEP_VSECST_CTL … #define CNXK_PEM_BAR4_INDEX … #define CNXK_PEM_BAR4_INDEX_SIZE … #define CNXK_PEM_BAR4_INDEX_OFFSET … #endif /* _OCTEP_REGS_CNXK_PF_H_ */
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