linux/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

// SPDX-License-Identifier: GPL-2.0
/* Marvell Octeon EP (EndPoint) Ethernet Driver
 *
 * Copyright (C) 2020 Marvell.
 *
 */

#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>

#include "octep_config.h"
#include "octep_main.h"
#include "octep_regs_cnxk_pf.h"

/* We will support 128 pf's in control mbox */
#define CTRL_MBOX_MAX_PF …
#define CTRL_MBOX_SZ …

/* Names of Hardware non-queue generic interrupts */
static char *cnxk_non_ioq_msix_names[] = …;

/* Dump useful hardware CSRs for debug purpose */
static void cnxk_dump_regs(struct octep_device *oct, int qno)
{ … }

/* Reset Hardware Tx queue */
static int cnxk_reset_iq(struct octep_device *oct, int q_no)
{ … }

/* Reset Hardware Rx queue */
static void cnxk_reset_oq(struct octep_device *oct, int q_no)
{ … }

/* Reset all hardware Tx/Rx queues */
static void octep_reset_io_queues_cnxk_pf(struct octep_device *oct)
{ … }

/* Initialize windowed addresses to access some hardware registers */
static void octep_setup_pci_window_regs_cnxk_pf(struct octep_device *oct)
{ … }

/* Configure Hardware mapping: inform hardware which rings belong to PF. */
static void octep_configure_ring_mapping_cnxk_pf(struct octep_device *oct)
{ … }

/* Initialize configuration limits and initial active config */
static void octep_init_config_cnxk_pf(struct octep_device *oct)
{ … }

/* Setup registers for a hardware Tx Queue  */
static void octep_setup_iq_regs_cnxk_pf(struct octep_device *oct, int iq_no)
{ … }

/* Setup registers for a hardware Rx Queue  */
static void octep_setup_oq_regs_cnxk_pf(struct octep_device *oct, int oq_no)
{ … }

/* Setup registers for a PF mailbox */
static void octep_setup_mbox_regs_cnxk_pf(struct octep_device *oct, int q_no)
{ … }

static void octep_poll_pfvf_mailbox_cnxk_pf(struct octep_device *oct)
{ … }

static irqreturn_t octep_pfvf_mbox_intr_handler_cnxk_pf(void *dev)
{ … }

/* Poll OEI events like heartbeat */
static void octep_poll_oei_cnxk_pf(struct octep_device *oct)
{ … }

/* OEI interrupt handler */
static irqreturn_t octep_oei_intr_handler_cnxk_pf(void *dev)
{ … }

/* Process non-ioq interrupts required to keep pf interface running.
 * OEI_RINT is needed for control mailbox
 * MBOX_RINT is needed for pfvf mailbox
 */
static void octep_poll_non_ioq_interrupts_cnxk_pf(struct octep_device *oct)
{ … }

/* Interrupt handler for input ring error interrupts. */
static irqreturn_t octep_ire_intr_handler_cnxk_pf(void *dev)
{ … }

/* Interrupt handler for output ring error interrupts. */
static irqreturn_t octep_ore_intr_handler_cnxk_pf(void *dev)
{ … }

/* Interrupt handler for vf input ring error interrupts. */
static irqreturn_t octep_vfire_intr_handler_cnxk_pf(void *dev)
{ … }

/* Interrupt handler for vf output ring error interrupts. */
static irqreturn_t octep_vfore_intr_handler_cnxk_pf(void *dev)
{ … }

/* Interrupt handler for dpi dma related interrupts. */
static irqreturn_t octep_dma_intr_handler_cnxk_pf(void *dev)
{ … }

/* Interrupt handler for dpi dma transaction error interrupts for VFs  */
static irqreturn_t octep_dma_vf_intr_handler_cnxk_pf(void *dev)
{ … }

/* Interrupt handler for pp transaction error interrupts for VFs  */
static irqreturn_t octep_pp_vf_intr_handler_cnxk_pf(void *dev)
{ … }

/* Interrupt handler for mac related interrupts. */
static irqreturn_t octep_misc_intr_handler_cnxk_pf(void *dev)
{ … }

/* Interrupts handler for all reserved interrupts. */
static irqreturn_t octep_rsvd_intr_handler_cnxk_pf(void *dev)
{ … }

/* Tx/Rx queue interrupt handler */
static irqreturn_t octep_ioq_intr_handler_cnxk_pf(void *data)
{ … }

/* soft reset */
static int octep_soft_reset_cnxk_pf(struct octep_device *oct)
{ … }

/* Re-initialize Octeon hardware registers */
static void octep_reinit_regs_cnxk_pf(struct octep_device *oct)
{ … }

/* Enable all interrupts */
static void octep_enable_interrupts_cnxk_pf(struct octep_device *oct)
{ … }

/* Disable all interrupts */
static void octep_disable_interrupts_cnxk_pf(struct octep_device *oct)
{ … }

/* Get new Octeon Read Index: index of descriptor that Octeon reads next. */
static u32 octep_update_iq_read_index_cnxk_pf(struct octep_iq *iq)
{ … }

/* Enable a hardware Tx Queue */
static void octep_enable_iq_cnxk_pf(struct octep_device *oct, int iq_no)
{ … }

/* Enable a hardware Rx Queue */
static void octep_enable_oq_cnxk_pf(struct octep_device *oct, int oq_no)
{ … }

/* Enable all hardware Tx/Rx Queues assined to PF */
static void octep_enable_io_queues_cnxk_pf(struct octep_device *oct)
{ … }

/* Disable a hardware Tx Queue assined to PF */
static void octep_disable_iq_cnxk_pf(struct octep_device *oct, int iq_no)
{ … }

/* Disable a hardware Rx Queue assined to PF */
static void octep_disable_oq_cnxk_pf(struct octep_device *oct, int oq_no)
{ … }

/* Disable all hardware Tx/Rx Queues assined to PF */
static void octep_disable_io_queues_cnxk_pf(struct octep_device *oct)
{ … }

/* Dump hardware registers (including Tx/Rx queues) for debugging. */
static void octep_dump_registers_cnxk_pf(struct octep_device *oct)
{ … }

/**
 * octep_device_setup_cnxk_pf() - Setup Octeon device.
 *
 * @oct: Octeon device private data structure.
 *
 * - initialize hardware operations.
 * - get target side pcie port number for the device.
 * - setup window access to hardware registers.
 * - set initial configuration and max limits.
 * - setup hardware mapping of rings to the PF device.
 */
void octep_device_setup_cnxk_pf(struct octep_device *oct)
{ … }