/* SPDX-License-Identifier: GPL-2.0 */ /* Marvell RVU Admin Function driver * * Copyright (C) 2018 Marvell. */ #ifndef COMMON_H #define COMMON_H #include "rvu_struct.h" #define OTX2_ALIGN … #define Q_SIZE_16 … #define Q_SIZE_64 … #define Q_SIZE_256 … #define Q_SIZE_1K … #define Q_SIZE_4K … #define Q_SIZE_16K … #define Q_SIZE_64K … #define Q_SIZE_256K … #define Q_SIZE_1M … #define Q_SIZE_MIN … #define Q_SIZE_MAX … #define Q_COUNT(x) … #define Q_SIZE(x, n) … /* Admin queue info */ /* Since we intend to add only one instruction at a time, * keep queue size to it's minimum. */ #define AQ_SIZE … /* HW head & tail pointer mask */ #define AQ_PTR_MASK … struct qmem { … }; static inline int qmem_alloc(struct device *dev, struct qmem **q, int qsize, int entry_sz) { … } static inline void qmem_free(struct device *dev, struct qmem *qmem) { … } struct admin_queue { … }; /* NPA aura count */ enum npa_aura_sz { … }; #define NPA_AURA_COUNT(x) … /* NPA AQ result structure for init/read/write of aura HW contexts */ struct npa_aq_aura_res { … }; /* NPA AQ result structure for init/read/write of pool HW contexts */ struct npa_aq_pool_res { … }; /* NIX Transmit schedulers */ enum nix_scheduler { … }; #define TXSCH_RR_QTM_MAX … #define TXSCH_TL1_DFLT_RR_QTM … #define TXSCH_TL1_DFLT_RR_PRIO … #define CN10K_MAX_DWRR_WEIGHT … /* Don't change the order as on CN10K (except CN10KB) * SMQX_CFG[SDP] value should be 1 for SDP flows. */ #define SMQ_LINK_TYPE_RPM … #define SMQ_LINK_TYPE_SDP … #define SMQ_LINK_TYPE_LBK … /* Min/Max packet sizes, excluding FCS */ #define NIC_HW_MIN_FRS … #define NIC_HW_MAX_FRS … #define SDP_HW_MAX_FRS … #define CN10K_LMAC_LINK_MAX_FRS … #define CN10K_LBK_LINK_MAX_FRS … /* NIX RX action operation*/ #define NIX_RX_ACTIONOP_DROP … #define NIX_RX_ACTIONOP_UCAST … #define NIX_RX_ACTIONOP_UCAST_IPSEC … #define NIX_RX_ACTIONOP_MCAST … #define NIX_RX_ACTIONOP_RSS … /* Use the RX action set in the default unicast entry */ #define NIX_RX_ACTION_DEFAULT … /* NIX TX action operation*/ #define NIX_TX_ACTIONOP_DROP … #define NIX_TX_ACTIONOP_UCAST_DEFAULT … #define NIX_TX_ACTIONOP_UCAST_CHAN … #define NIX_TX_ACTIONOP_MCAST … #define NIX_TX_ACTIONOP_DROP_VIOL … #define NPC_MCAM_KEY_X1 … #define NPC_MCAM_KEY_X2 … #define NPC_MCAM_KEY_X4 … #define NIX_INTFX_RX(a) … #define NIX_INTFX_TX(a) … /* Default interfaces are NIX0_RX and NIX0_TX */ #define NIX_INTF_RX … #define NIX_INTF_TX … #define NIX_INTF_TYPE_CGX … #define NIX_INTF_TYPE_LBK … #define NIX_INTF_TYPE_SDP … #define MAX_LMAC_PKIND … #define NIX_LINK_CGX_LMAC(a, b) … #define NIX_LINK_LBK(a) … #define NIX_CHAN_CGX_LMAC_CHX(a, b, c) … #define NIX_CHAN_LBK_CHX(a, b) … #define NIX_CHAN_SDP_CH_START … #define NIX_CHAN_SDP_CHX(a) … #define NIX_CHAN_SDP_NUM_CHANS … #define NIX_CHAN_CPT_CH_START … /* The mask is to extract lower 10-bits of channel number * which CPT will pass to X2P. */ #define NIX_CHAN_CPT_X2P_MASK … /* NIX LSO format indices. * As of now TSO is the only one using, so statically assigning indices. */ #define NIX_LSO_FORMAT_IDX_TSOV4 … #define NIX_LSO_FORMAT_IDX_TSOV6 … /* RSS info */ #define MAX_RSS_GROUPS … /* Group 0 has to be used in default pkt forwarding MCAM entries * reserved for NIXLFs. Groups 1-7 can be used for RSS for ntuple * filters. */ #define DEFAULT_RSS_CONTEXT_GROUP … #define MAX_RSS_INDIR_TBL_SIZE … /* NDC info */ enum ndc_idx_e { … }; enum ndc_ctype_e { … }; #define NDC_MAX_PORT … #define NDC_READ_TRANS … #define NDC_WRITE_TRANS … #endif /* COMMON_H */
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