/* SPDX-License-Identifier: GPL-2.0 */ /* Marvell OcteonTx2 CGX driver * * Copyright (C) 2018 Marvell. * */ #ifndef CGX_H #define CGX_H #include "mbox.h" #include "cgx_fw_if.h" #include "rpm.h" /* PCI device IDs */ #define PCI_DEVID_OCTEONTX2_CGX … /* PCI BAR nos */ #define PCI_CFG_REG_BAR_NUM … #define CGX_ID_MASK … /* Registers */ #define CGXX_CMRX_CFG … #define CMR_P2X_SEL_MASK … #define CMR_P2X_SEL_SHIFT … #define CMR_P2X_SEL_NIX0 … #define CMR_P2X_SEL_NIX1 … #define DATA_PKT_TX_EN … #define DATA_PKT_RX_EN … #define CGX_LMAC_TYPE_SHIFT … #define CGX_LMAC_TYPE_MASK … #define CGXX_CMRX_INT … #define FW_CGX_INT … #define CGXX_CMRX_INT_ENA_W1S … #define CGXX_CMRX_RX_ID_MAP … #define CGXX_CMRX_RX_STAT0 … #define CGXX_CMRX_RX_LOGL_XON … #define CGXX_CMRX_RX_LMACS … #define CGXX_CMRX_RX_DMAC_CTL0 … #define CGX_DMAC_CTL0_CAM_ENABLE … #define CGX_DMAC_CAM_ACCEPT … #define CGX_DMAC_MCAST_MODE_CAM … #define CGX_DMAC_MCAST_MODE … #define CGX_DMAC_BCAST_MODE … #define CGXX_CMRX_RX_DMAC_CAM0 … #define CGX_DMAC_CAM_ADDR_ENABLE … #define CGX_DMAC_CAM_ENTRY_LMACID … #define CGXX_CMRX_RX_DMAC_CAM1 … #define CGX_RX_DMAC_ADR_MASK … #define CGXX_CMRX_TX_STAT0 … #define CGXX_SCRATCH0_REG … #define CGXX_SCRATCH1_REG … #define CGX_CONST … #define CGX_CONST_RXFIFO_SIZE … #define CGX_CONST_MAX_LMACS … #define CGXX_SPUX_CONTROL1 … #define CGXX_SPUX_LNX_FEC_CORR_BLOCKS … #define CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS … #define CGXX_SPUX_RSFEC_CORR … #define CGXX_SPUX_RSFEC_UNCORR … #define CGXX_SPUX_CONTROL1_LBK … #define CGXX_GMP_PCS_MRX_CTL … #define CGXX_GMP_PCS_MRX_CTL_LBK … #define CGXX_SMUX_RX_FRM_CTL … #define CGX_SMUX_RX_FRM_CTL_CTL_BCK … #define CGX_SMUX_RX_FRM_CTL_PTP_MODE … #define CGXX_GMP_GMI_RXX_FRM_CTL … #define CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK … #define CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE … #define CGXX_SMUX_TX_CTL … #define CGXX_SMUX_TX_PAUSE_PKT_TIME … #define CGXX_SMUX_TX_PAUSE_PKT_INTERVAL … #define CGXX_SMUX_SMAC … #define CGXX_SMUX_CBFC_CTL … #define CGXX_SMUX_CBFC_CTL_RX_EN … #define CGXX_SMUX_CBFC_CTL_TX_EN … #define CGXX_SMUX_CBFC_CTL_DRP_EN … #define CGXX_SMUX_CBFC_CTL_BCK_EN … #define CGX_PFC_CLASS_MASK … #define CGXX_GMP_GMI_TX_PAUSE_PKT_TIME … #define CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL … #define CGX_SMUX_TX_CTL_L2P_BP_CONV … #define CGXX_CMR_RX_OVR_BP … #define CGX_CMR_RX_OVR_BP_EN(X) … #define CGX_CMR_RX_OVR_BP_BP(X) … #define CGX_COMMAND_REG … #define CGX_EVENT_REG … #define CGX_CMD_TIMEOUT … #define DEFAULT_PAUSE_TIME … #define CGX_LMAC_FWI … enum cgx_nix_stat_type { … }; enum LMAC_TYPE { … }; struct cgx_link_event { … }; /** * struct cgx_event_cb * @notify_link_chg: callback for link change notification * @data: data passed to callback function */ struct cgx_event_cb { … }; extern struct pci_driver cgx_driver; int cgx_get_cgxcnt_max(void); int cgx_get_cgxid(void *cgxd); int cgx_get_lmac_cnt(void *cgxd); void *cgx_get_pdata(int cgx_id); int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind); int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id); int cgx_lmac_evh_unregister(void *cgxd, int lmac_id); int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat); int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat); int cgx_stats_reset(void *cgxd, int lmac_id); int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable); int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable); int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr); int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id); u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id); int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr); int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index); int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id); void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable); void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable); int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable); int cgx_get_link_info(void *cgxd, int lmac_id, struct cgx_link_user_info *linfo); int cgx_lmac_linkup_start(void *cgxd); int cgx_get_fwdata_base(u64 *base); int cgx_lmac_get_pause_frm(void *cgxd, int lmac_id, u8 *tx_pause, u8 *rx_pause); int cgx_lmac_set_pause_frm(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause); void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable); u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id); int cgx_set_fec(u64 fec, int cgx_id, int lmac_id); int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp); int cgx_get_phy_fec_stats(void *cgxd, int lmac_id); int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args, int cgx_id, int lmac_id); u64 cgx_features_get(void *cgxd); struct mac_ops *get_mac_ops(void *cgxd); int cgx_get_nr_lmacs(void *cgxd); u8 cgx_get_lmacid(void *cgxd, u8 lmac_index); unsigned long cgx_get_lmac_bmap(void *cgxd); void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val); u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset); int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index); u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id); u64 cgx_read_dmac_entry(void *cgxd, int index); int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause, u16 pfc_en); int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause, u8 *rx_pause); int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause, int pfvf_idx); int cgx_lmac_reset(void *cgxd, int lmac_id, u8 pf_req_flr); #endif /* CGX_H */
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