linux/drivers/net/ethernet/marvell/octeontx2/af/ptp.c

// SPDX-License-Identifier: GPL-2.0
/* Marvell PTP driver
 *
 * Copyright (C) 2020 Marvell.
 *
 */

#include <linux/bitfield.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/hrtimer.h>
#include <linux/ktime.h>

#include "mbox.h"
#include "ptp.h"
#include "rvu.h"

#define DRV_NAME …

#define PCI_DEVID_OCTEONTX2_PTP …
#define PCI_SUBSYS_DEVID_OCTX2_98xx_PTP …
#define PCI_SUBSYS_DEVID_OCTX2_96XX_PTP …
#define PCI_SUBSYS_DEVID_OCTX2_95XX_PTP …
#define PCI_SUBSYS_DEVID_OCTX2_95XXN_PTP …
#define PCI_SUBSYS_DEVID_OCTX2_95MM_PTP …
#define PCI_SUBSYS_DEVID_OCTX2_95XXO_PTP …
#define PCI_DEVID_OCTEONTX2_RST …
#define PCI_DEVID_CN10K_PTP …
#define PCI_SUBSYS_DEVID_CN10K_A_PTP …
#define PCI_SUBSYS_DEVID_CNF10K_A_PTP …
#define PCI_SUBSYS_DEVID_CNF10K_B_PTP …

#define PCI_PTP_BAR_NO …

#define PTP_CLOCK_CFG …
#define PTP_CLOCK_CFG_PTP_EN …
#define PTP_CLOCK_CFG_EXT_CLK_EN …
#define PTP_CLOCK_CFG_EXT_CLK_IN_MASK …
#define PTP_CLOCK_CFG_TSTMP_EDGE …
#define PTP_CLOCK_CFG_TSTMP_EN …
#define PTP_CLOCK_CFG_TSTMP_IN_MASK …
#define PTP_CLOCK_CFG_ATOMIC_OP_MASK …
#define PTP_CLOCK_CFG_PPS_EN …
#define PTP_CLOCK_CFG_PPS_INV …

#define PTP_PPS_HI_INCR …
#define PTP_PPS_LO_INCR …
#define PTP_PPS_THRESH_LO …
#define PTP_PPS_THRESH_HI …

#define PTP_CLOCK_LO …
#define PTP_CLOCK_HI …
#define PTP_CLOCK_COMP …
#define PTP_TIMESTAMP …
#define PTP_CLOCK_SEC …
#define PTP_SEC_ROLLOVER …
/* Atomic update related CSRs */
#define PTP_FRNS_TIMESTAMP …
#define PTP_NXT_ROLLOVER_SET …
#define PTP_CURR_ROLLOVER_SET …
#define PTP_NANO_TIMESTAMP …
#define PTP_SEC_TIMESTAMP …

#define CYCLE_MULT …

#define is_rev_A0(ptp) …
#define is_rev_A1(ptp) …

/* PTP atomic update operation type */
enum atomic_opcode { … };

static struct ptp *first_ptp_block;
static const struct pci_device_id ptp_id_table[];

static bool is_ptp_dev_cnf10ka(struct ptp *ptp)
{ … }

static bool is_ptp_dev_cn10ka(struct ptp *ptp)
{ … }

static bool cn10k_ptp_errata(struct ptp *ptp)
{ … }

static bool is_tstmp_atomic_update_supported(struct rvu *rvu)
{ … }

static enum hrtimer_restart ptp_reset_thresh(struct hrtimer *hrtimer)
{ … }

static void ptp_hrtimer_start(struct ptp *ptp, ktime_t start_ns)
{ … }

static u64 read_ptp_tstmp_sec_nsec(struct ptp *ptp)
{ … }

static u64 read_ptp_tstmp_nsec(struct ptp *ptp)
{ … }

static u64 ptp_calc_adjusted_comp(u64 ptp_clock_freq)
{ … }

struct ptp *ptp_get(void)
{ … }

void ptp_put(struct ptp *ptp)
{ … }

static void ptp_atomic_update(struct ptp *ptp, u64 timestamp)
{ … }

static void ptp_atomic_adjtime(struct ptp *ptp, s64 delta)
{ … }

static int ptp_adjfine(struct ptp *ptp, long scaled_ppm)
{ … }

static int ptp_get_clock(struct ptp *ptp, u64 *clk)
{ … }

void ptp_start(struct rvu *rvu, u64 sclk, u32 ext_clk_freq, u32 extts)
{ … }

static int ptp_get_tstmp(struct ptp *ptp, u64 *clk)
{ … }

static int ptp_set_thresh(struct ptp *ptp, u64 thresh)
{ … }

static int ptp_config_hrtimer(struct ptp *ptp, int on)
{ … }

static int ptp_pps_on(struct ptp *ptp, int on, u64 period)
{ … }

static int ptp_probe(struct pci_dev *pdev,
		     const struct pci_device_id *ent)
{ … }

static void ptp_remove(struct pci_dev *pdev)
{ … }

static const struct pci_device_id ptp_id_table[] = …;

struct pci_driver ptp_driver = …;

int rvu_mbox_handler_ptp_op(struct rvu *rvu, struct ptp_req *req,
			    struct ptp_rsp *rsp)
{ … }

int rvu_mbox_handler_ptp_get_cap(struct rvu *rvu, struct msg_req *req,
				 struct ptp_get_cap_rsp *rsp)
{ … }