/* SPDX-License-Identifier: GPL-2.0 */ /* Marvell RVU Admin Function driver * * Copyright (C) 2018 Marvell. * */ #ifndef RVU_H #define RVU_H #include <linux/pci.h> #include <net/devlink.h> #include "rvu_struct.h" #include "rvu_devlink.h" #include "common.h" #include "mbox.h" #include "npc.h" #include "rvu_reg.h" #include "ptp.h" /* PCI device IDs */ #define PCI_DEVID_OCTEONTX2_RVU_AF … #define PCI_DEVID_OCTEONTX2_LBK … /* Subsystem Device ID */ #define PCI_SUBSYS_DEVID_98XX … #define PCI_SUBSYS_DEVID_96XX … #define PCI_SUBSYS_DEVID_CN10K_A … #define PCI_SUBSYS_DEVID_CNF10K_A … #define PCI_SUBSYS_DEVID_CNF10K_B … #define PCI_SUBSYS_DEVID_CN10K_B … /* PCI BAR nos */ #define PCI_AF_REG_BAR_NUM … #define PCI_PF_REG_BAR_NUM … #define PCI_MBOX_BAR_NUM … #define NAME_SIZE … #define MAX_NIX_BLKS … #define MAX_CPT_BLKS … /* PF_FUNC */ #define RVU_PFVF_PF_SHIFT … #define RVU_PFVF_PF_MASK … #define RVU_PFVF_FUNC_SHIFT … #define RVU_PFVF_FUNC_MASK … #ifdef CONFIG_DEBUG_FS struct dump_ctx { … }; struct cpt_ctx { … }; struct rvu_debugfs { … }; #endif struct rvu_work { … }; struct rsrc_bmap { … }; struct rvu_block { … }; struct nix_mcast { … }; struct nix_mce_list { … }; struct nix_mcast_grp_elem { … }; struct nix_mcast_grp { … }; /* layer metadata to uniquely identify a packet header field */ struct npc_layer_mdata { … }; /* Structure to represent a field present in the * generated key. A key field may present anywhere and can * be of any size in the generated key. Once this structure * is populated for fields of interest then field's presence * and location (if present) can be known. */ struct npc_key_field { … }; struct npc_mcam { … }; /* Structure for per RVU func info ie PF/VF */ struct rvu_pfvf { … }; enum rvu_pfvf_flags { … }; #define RVU_CLEAR_VF_PERM … struct nix_bp { … }; struct nix_txsch { … }; struct nix_mark_format { … }; /* smq(flush) to tl1 cir/pir info */ struct nix_smq_tree_ctx { … }; /* smq flush context */ struct nix_smq_flush_ctx { … }; struct npc_pkind { … }; struct nix_flowkey { … }; struct nix_lso { … }; struct nix_txvlan { … }; struct nix_ipolicer { … }; struct nix_hw { … }; /* RVU block's capabilities or functionality, * which vary by silicon version/skew. */ struct hw_cap { … }; struct rvu_hwinfo { … }; struct mbox_wq_info { … }; struct channel_fwdata { … }; struct rvu_fwdata { … }; struct ptp; /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the * source where it came from. */ struct npc_kpu_profile_adapter { … }; #define RVU_SWITCH_LBK_CHAN … struct rvu_switch { … }; struct rvu { … }; static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) { … } static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) { … } static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) { … } static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) { … } static inline void rvu_bar2_sel_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) { … } /* Silicon revisions */ static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu) { … } static inline bool is_rvu_96xx_A0(struct rvu *rvu) { … } static inline bool is_rvu_96xx_B0(struct rvu *rvu) { … } static inline bool is_rvu_95xx_A0(struct rvu *rvu) { … } /* REVID for PCIe devices. * Bits 0..1: minor pass, bit 3..2: major pass * bits 7..4: midr id */ #define PCI_REVISION_ID_96XX … #define PCI_REVISION_ID_95XX … #define PCI_REVISION_ID_95XXN … #define PCI_REVISION_ID_98XX … #define PCI_REVISION_ID_95XXMM … #define PCI_REVISION_ID_95XXO … static inline bool is_rvu_otx2(struct rvu *rvu) { … } static inline bool is_cnf10ka_a0(struct rvu *rvu) { … } static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu) { … } static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid, u8 lmacid, u8 chan) { … } static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid, u8 chan) { … } static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan) { … } static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan) { … } static inline bool is_rvu_supports_nix1(struct rvu *rvu) { … } /* Function Prototypes * RVU */ #define RVU_LBK_VF_DEVID … static inline bool is_lbk_vf(struct rvu *rvu, u16 pcifunc) { … } static inline bool is_vf(u16 pcifunc) { … } /* check if PF_FUNC is AF */ static inline bool is_pffunc_af(u16 pcifunc) { … } static inline bool is_rvu_fwdata_valid(struct rvu *rvu) { … } int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); void rvu_free_bitmap(struct rsrc_bmap *rsrc); int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); bool is_rsrc_free(struct rsrc_bmap *rsrc, int id); int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start); bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr); int rvu_get_pf(u16 pcifunc); struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); int rvu_get_num_lbk_chans(void); int rvu_ndc_sync(struct rvu *rvu, int lfblkid, int lfidx, u64 lfoffset); int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc, u16 global_slot, u16 *slot_in_block); /* RVU HW reg validation */ enum regmap_block { … }; bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); /* NPA/NIX AQ APIs */ int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, int qsize, int inst_size, int res_size); void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); /* SDP APIs */ int rvu_sdp_init(struct rvu *rvu); bool is_sdp_pfvf(u16 pcifunc); bool is_sdp_pf(u16 pcifunc); bool is_sdp_vf(struct rvu *rvu, u16 pcifunc); /* CGX APIs */ static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) { … } static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) { … } static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc) { … } #define M … MBOX_MESSAGES #undef M int rvu_cgx_init(struct rvu *rvu); int rvu_cgx_exit(struct rvu *rvu); void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, int rxtxflag, u64 *stat); void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc); /* NPA APIs */ int rvu_npa_init(struct rvu *rvu); void rvu_npa_freemem(struct rvu *rvu); void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, struct npa_aq_enq_rsp *rsp); /* NIX APIs */ bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); int rvu_nix_init(struct rvu *rvu); int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr, u32 cfg); void rvu_nix_freemem(struct rvu *rvu); int rvu_get_nixlf_count(struct rvu *rvu); void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); int nix_update_mce_list(struct rvu *rvu, u16 pcifunc, struct nix_mce_list *mce_list, int mce_idx, int mcam_index, bool add); void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type, struct nix_mce_list **mce_list, int *mce_idx); struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr); int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr); void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc); int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc, struct nix_hw **nix_hw, int *blkaddr); int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc, u16 rq_idx, u16 match_id); int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw, struct nix_cn10k_aq_enq_req *aq_req, struct nix_cn10k_aq_enq_rsp *aq_rsp, u16 pcifunc, u8 ctype, u32 qidx); int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc); int nix_get_dwrr_mtu_reg(struct rvu_hwinfo *hw, int smq_link_type); u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu); u32 convert_bytes_to_dwrr_mtu(u32 bytes); void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc, struct nix_txsch *txsch, bool enable); void rvu_nix_mcast_flr_free_entries(struct rvu *rvu, u16 pcifunc); int rvu_nix_mcast_get_mce_index(struct rvu *rvu, u16 pcifunc, u32 mcast_grp_idx); int rvu_nix_mcast_update_mcam_entry(struct rvu *rvu, u16 pcifunc, u32 mcast_grp_idx, u16 mcam_index); void rvu_nix_flr_free_bpids(struct rvu *rvu, u16 pcifunc); /* NPC APIs */ void rvu_npc_freemem(struct rvu *rvu); int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, int nixlf, u64 chan, u8 *mac_addr); void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf, u64 chan, u8 chan_cnt); void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf, bool enable); void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, int nixlf, u64 chan); void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf, bool enable); void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, u64 chan); void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, bool enable); void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc, int nixlf, int type, bool enable); void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable); void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, int group, int alg_idx, int mcam_index); void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, int blkaddr, int *alloc_cnt, int *enable_cnt); void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, int blkaddr, int *alloc_cnt, int *enable_cnt); bool is_npc_intf_tx(u8 intf); bool is_npc_intf_rx(u8 intf); bool is_npc_interface_valid(struct rvu *rvu, u8 intf); int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena); int npc_flow_steering_init(struct rvu *rvu, int blkaddr); const char *npc_get_field_name(u8 hdr); int npc_get_bank(struct npc_mcam *mcam, int index); void npc_mcam_enable_flows(struct rvu *rvu, u16 target); void npc_mcam_disable_flows(struct rvu *rvu, u16 target); void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, int index, bool enable); u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, int index); void npc_set_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, int index, u64 cfg); void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, u16 src, struct mcam_entry *entry, u8 *intf, u8 *ena); bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc); bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature); u32 rvu_cgx_get_fifolen(struct rvu *rvu); void *rvu_first_cgx_pdata(struct rvu *rvu); int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id); int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable); int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable); int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause, u16 pfc_en); int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause); void rvu_mac_reset(struct rvu *rvu, u16 pcifunc); u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac); int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf, int type); bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, int index); int rvu_npc_init(struct rvu *rvu); int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx, u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask, u64 bcast_mcast_val, u64 bcast_mcast_mask); void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx); bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf); int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr); void npc_mcam_rsrcs_deinit(struct rvu *rvu); /* CPT APIs */ int rvu_cpt_register_interrupts(struct rvu *rvu); void rvu_cpt_unregister_interrupts(struct rvu *rvu); int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf, int slot); int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc); int rvu_cpt_init(struct rvu *rvu); #define NDC_AF_BANK_MASK … #define NDC_AF_BANK_LINE_MASK … /* CN10K RVU */ int rvu_set_channels_base(struct rvu *rvu); void rvu_program_channels(struct rvu *rvu); /* CN10K NIX */ void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw); /* CN10K RVU - LMT*/ void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc); void rvu_apr_block_cn10k_init(struct rvu *rvu); #ifdef CONFIG_DEBUG_FS void rvu_dbg_init(struct rvu *rvu); void rvu_dbg_exit(struct rvu *rvu); #else static inline void rvu_dbg_init(struct rvu *rvu) {} static inline void rvu_dbg_exit(struct rvu *rvu) {} #endif int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr); /* RVU Switch */ void rvu_switch_enable(struct rvu *rvu); void rvu_switch_disable(struct rvu *rvu); void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc); int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir, u64 pkind, u8 var_len_off, u8 var_len_off_mask, u8 shift_dir); int rvu_get_hwvf(struct rvu *rvu, int pcifunc); /* CN10K MCS */ int rvu_mcs_init(struct rvu *rvu); int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc); void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena); void rvu_mcs_exit(struct rvu *rvu); #endif /* RVU_H */
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