linux/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

// SPDX-License-Identifier: GPL-2.0
/* Marvell RVU Admin Function driver
 *
 * Copyright (C) 2018 Marvell.
 *
 */

#include <linux/module.h>
#include <linux/pci.h>

#include "rvu_struct.h"
#include "rvu_reg.h"
#include "rvu.h"
#include "npc.h"
#include "mcs.h"
#include "cgx.h"
#include "lmac_common.h"
#include "rvu_npc_hash.h"

static void nix_free_tx_vtag_entries(struct rvu *rvu, u16 pcifunc);
static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req,
			    int type, int chan_id);
static int nix_update_mce_rule(struct rvu *rvu, u16 pcifunc,
			       int type, bool add);
static int nix_setup_ipolicers(struct rvu *rvu,
			       struct nix_hw *nix_hw, int blkaddr);
static void nix_ipolicer_freemem(struct rvu *rvu, struct nix_hw *nix_hw);
static int nix_verify_bandprof(struct nix_cn10k_aq_enq_req *req,
			       struct nix_hw *nix_hw, u16 pcifunc);
static int nix_free_all_bandprof(struct rvu *rvu, u16 pcifunc);
static void nix_clear_ratelimit_aggr(struct rvu *rvu, struct nix_hw *nix_hw,
				     u32 leaf_prof);
static const char *nix_get_ctx_name(int ctype);

enum mc_tbl_sz { … };

enum mc_buf_cnt { … };

enum nix_makr_fmt_indexes { … };

/* For now considering MC resources needed for broadcast
 * pkt replication only. i.e 256 HWVFs + 12 PFs.
 */
#define MC_TBL_SIZE …
#define MC_BUF_CNT …

#define MC_TX_MAX …

struct mce { … };

int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr)
{ … }

bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc)
{ … }

int rvu_get_nixlf_count(struct rvu *rvu)
{ … }

int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr)
{ … }

int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc,
			struct nix_hw **nix_hw, int *blkaddr)
{ … }

static void nix_mce_list_init(struct nix_mce_list *list, int max)
{ … }

static int nix_alloc_mce_list(struct nix_mcast *mcast, int count, u8 dir)
{ … }

static void nix_free_mce_list(struct nix_mcast *mcast, int count, int start, u8 dir)
{ … }

struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr)
{ … }

int nix_get_dwrr_mtu_reg(struct rvu_hwinfo *hw, int smq_link_type)
{ … }

u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu)
{ … }

u32 convert_bytes_to_dwrr_mtu(u32 bytes)
{ … }

static void nix_rx_sync(struct rvu *rvu, int blkaddr)
{ … }

static bool is_valid_txschq(struct rvu *rvu, int blkaddr,
			    int lvl, u16 pcifunc, u16 schq)
{ … }

static int nix_interface_init(struct rvu *rvu, u16 pcifunc, int type, int nixlf,
			      struct nix_lf_alloc_rsp *rsp, bool loop)
{ … }

static void nix_interface_deinit(struct rvu *rvu, u16 pcifunc, u8 nixlf)
{ … }

#define NIX_BPIDS_PER_LMAC …
#define NIX_BPIDS_PER_CPT …
static int nix_setup_bpids(struct rvu *rvu, struct nix_hw *hw, int blkaddr)
{ … }

void rvu_nix_flr_free_bpids(struct rvu *rvu, u16 pcifunc)
{ … }

int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
				    struct nix_bp_cfg_req *req,
				    struct msg_rsp *rsp)
{ … }

static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req,
			    int type, int chan_id)
{ … }

int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu,
				   struct nix_bp_cfg_req *req,
				   struct nix_bp_cfg_rsp *rsp)
{ … }

static void nix_setup_lso_tso_l3(struct rvu *rvu, int blkaddr,
				 u64 format, bool v4, u64 *fidx)
{ … }

static void nix_setup_lso_tso_l4(struct rvu *rvu, int blkaddr,
				 u64 format, u64 *fidx)
{ … }

static void nix_setup_lso(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr)
{ … }

static void nix_ctx_free(struct rvu *rvu, struct rvu_pfvf *pfvf)
{ … }

static int nixlf_rss_ctx_init(struct rvu *rvu, int blkaddr,
			      struct rvu_pfvf *pfvf, int nixlf,
			      int rss_sz, int rss_grps, int hwctx_size,
			      u64 way_mask, bool tag_lsb_as_adder)
{ … }

static int nix_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block,
			       struct nix_aq_inst_s *inst)
{ … }

static void nix_get_aq_req_smq(struct rvu *rvu, struct nix_aq_enq_req *req,
			       u16 *smq, u16 *smq_mask)
{ … }

static int rvu_nix_blk_aq_enq_inst(struct rvu *rvu, struct nix_hw *nix_hw,
				   struct nix_aq_enq_req *req,
				   struct nix_aq_enq_rsp *rsp)
{ … }

static int rvu_nix_verify_aq_ctx(struct rvu *rvu, struct nix_hw *nix_hw,
				 struct nix_aq_enq_req *req, u8 ctype)
{ … }

static int rvu_nix_aq_enq_inst(struct rvu *rvu, struct nix_aq_enq_req *req,
			       struct nix_aq_enq_rsp *rsp)
{ … }

static const char *nix_get_ctx_name(int ctype)
{ … }

static int nix_lf_hwctx_disable(struct rvu *rvu, struct hwctx_disable_req *req)
{ … }

#ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING
static int nix_lf_hwctx_lockdown(struct rvu *rvu, struct nix_aq_enq_req *req)
{ … }

int rvu_mbox_handler_nix_aq_enq(struct rvu *rvu,
				struct nix_aq_enq_req *req,
				struct nix_aq_enq_rsp *rsp)
{ … }
#else

int rvu_mbox_handler_nix_aq_enq(struct rvu *rvu,
				struct nix_aq_enq_req *req,
				struct nix_aq_enq_rsp *rsp)
{
	return rvu_nix_aq_enq_inst(rvu, req, rsp);
}
#endif
/* CN10K mbox handler */
int rvu_mbox_handler_nix_cn10k_aq_enq(struct rvu *rvu,
				      struct nix_cn10k_aq_enq_req *req,
				      struct nix_cn10k_aq_enq_rsp *rsp)
{ … }

int rvu_mbox_handler_nix_hwctx_disable(struct rvu *rvu,
				       struct hwctx_disable_req *req,
				       struct msg_rsp *rsp)
{ … }

int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu,
				  struct nix_lf_alloc_req *req,
				  struct nix_lf_alloc_rsp *rsp)
{ … }

int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, struct nix_lf_free_req *req,
				 struct msg_rsp *rsp)
{ … }

int rvu_mbox_handler_nix_mark_format_cfg(struct rvu *rvu,
					 struct nix_mark_format_cfg  *req,
					 struct nix_mark_format_cfg_rsp *rsp)
{ … }

/* Handle shaper update specially for few revisions */
static bool
handle_txschq_shaper_update(struct rvu *rvu, int blkaddr, int nixlf,
			    int lvl, u64 reg, u64 regval)
{ … }

static void nix_reset_tx_schedule(struct rvu *rvu, int blkaddr,
				  int lvl, int schq)
{ … }

/* Disable shaping of pkts by a scheduler queue
 * at a given scheduler level.
 */
static void nix_reset_tx_shaping(struct rvu *rvu, int blkaddr,
				 int nixlf, int lvl, int schq)
{ … }

static void nix_reset_tx_linkcfg(struct rvu *rvu, int blkaddr,
				 int lvl, int schq)
{ … }

static void nix_clear_tx_xoff(struct rvu *rvu, int blkaddr,
			      int lvl, int schq)
{ … }

static int nix_get_tx_link(struct rvu *rvu, u16 pcifunc)
{ … }

static void nix_get_txschq_range(struct rvu *rvu, u16 pcifunc,
				 int link, int *start, int *end)
{ … }

static int nix_check_txschq_alloc_req(struct rvu *rvu, int lvl, u16 pcifunc,
				      struct nix_hw *nix_hw,
				      struct nix_txsch_alloc_req *req)
{ … }

static void nix_txsch_alloc(struct rvu *rvu, struct nix_txsch *txsch,
			    struct nix_txsch_alloc_rsp *rsp,
			    int lvl, int start, int end)
{ … }

int rvu_mbox_handler_nix_txsch_alloc(struct rvu *rvu,
				     struct nix_txsch_alloc_req *req,
				     struct nix_txsch_alloc_rsp *rsp)
{ … }

static void nix_smq_flush_fill_ctx(struct rvu *rvu, int blkaddr, int smq,
				   struct nix_smq_flush_ctx *smq_flush_ctx)
{ … }

static void nix_smq_flush_enadis_xoff(struct rvu *rvu, int blkaddr,
				      struct nix_smq_flush_ctx *smq_flush_ctx, bool enable)
{ … }

static void nix_smq_flush_enadis_rate(struct rvu *rvu, int blkaddr,
				      struct nix_smq_flush_ctx *smq_flush_ctx, bool enable)
{ … }

static int nix_smq_flush(struct rvu *rvu, int blkaddr,
			 int smq, u16 pcifunc, int nixlf)
{ … }

static int nix_txschq_free(struct rvu *rvu, u16 pcifunc)
{ … }

static int nix_txschq_free_one(struct rvu *rvu,
			       struct nix_txsch_free_req *req)
{ … }

int rvu_mbox_handler_nix_txsch_free(struct rvu *rvu,
				    struct nix_txsch_free_req *req,
				    struct msg_rsp *rsp)
{ … }

static bool is_txschq_hierarchy_valid(struct rvu *rvu, u16 pcifunc, int blkaddr,
				      int lvl, u64 reg, u64 regval)
{ … }

static bool is_txschq_shaping_valid(struct rvu_hwinfo *hw, int lvl, u64 reg)
{ … }

static void nix_tl1_default_cfg(struct rvu *rvu, struct nix_hw *nix_hw,
				u16 pcifunc, int blkaddr)
{ … }

/* Register offset - [15:0]
 * Scheduler Queue number - [25:16]
 */
#define NIX_TX_SCHQ_MASK …

static int nix_txschq_cfg_read(struct rvu *rvu, struct nix_hw *nix_hw,
			       int blkaddr, struct nix_txschq_config *req,
			       struct nix_txschq_config *rsp)
{ … }

void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc,
			struct nix_txsch *txsch, bool enable)
{ … }

int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu,
				    struct nix_txschq_config *req,
				    struct nix_txschq_config *rsp)
{ … }

static int nix_rx_vtag_cfg(struct rvu *rvu, int nixlf, int blkaddr,
			   struct nix_vtag_config *req)
{ … }

static int nix_tx_vtag_free(struct rvu *rvu, int blkaddr,
			    u16 pcifunc, int index)
{ … }

static void nix_free_tx_vtag_entries(struct rvu *rvu, u16 pcifunc)
{ … }

static int nix_tx_vtag_alloc(struct rvu *rvu, int blkaddr,
			     u64 vtag, u8 size)
{ … }

static int nix_tx_vtag_decfg(struct rvu *rvu, int blkaddr,
			     struct nix_vtag_config *req)
{ … }

static int nix_tx_vtag_cfg(struct rvu *rvu, int blkaddr,
			   struct nix_vtag_config *req,
			   struct nix_vtag_config_rsp *rsp)
{ … }

int rvu_mbox_handler_nix_vtag_cfg(struct rvu *rvu,
				  struct nix_vtag_config *req,
				  struct nix_vtag_config_rsp *rsp)
{ … }

static int nix_blk_setup_mce(struct rvu *rvu, struct nix_hw *nix_hw,
			     int mce, u8 op, u16 pcifunc, int next,
			     int index, u8 mce_op, bool eol)
{ … }

static void nix_delete_mcast_mce_list(struct nix_mce_list *mce_list)
{ … }

static int nix_get_last_mce_list_index(struct nix_mcast_grp_elem *elem)
{ … }

static int nix_update_ingress_mce_list_hw(struct rvu *rvu,
					  struct nix_hw *nix_hw,
					  struct nix_mcast_grp_elem *elem)
{ … }

static void nix_update_egress_mce_list_hw(struct rvu *rvu,
					  struct nix_hw *nix_hw,
					  struct nix_mcast_grp_elem *elem)
{ … }

static int nix_del_mce_list_entry(struct rvu *rvu,
				  struct nix_hw *nix_hw,
				  struct nix_mcast_grp_elem *elem,
				  struct nix_mcast_grp_update_req *req)
{ … }

static int nix_add_mce_list_entry(struct rvu *rvu,
				  struct nix_hw *nix_hw,
				  struct nix_mcast_grp_elem *elem,
				  struct nix_mcast_grp_update_req *req)
{ … }

static int nix_update_mce_list_entry(struct nix_mce_list *mce_list,
				     u16 pcifunc, bool add)
{ … }

int nix_update_mce_list(struct rvu *rvu, u16 pcifunc,
			struct nix_mce_list *mce_list,
			int mce_idx, int mcam_index, bool add)
{ … }

void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type,
		      struct nix_mce_list **mce_list, int *mce_idx)
{ … }

static int nix_update_mce_rule(struct rvu *rvu, u16 pcifunc,
			       int type, bool add)
{ … }

static void nix_setup_mcast_grp(struct nix_hw *nix_hw)
{ … }

static int nix_setup_mce_tables(struct rvu *rvu, struct nix_hw *nix_hw)
{ … }

static int nix_setup_mcast(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr)
{ … }

static int nix_setup_txvlan(struct rvu *rvu, struct nix_hw *nix_hw)
{ … }

static int nix_setup_txschq(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr)
{ … }

int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
				int blkaddr, u32 cfg)
{ … }

static int nix_af_mark_format_setup(struct rvu *rvu, struct nix_hw *nix_hw,
				    int blkaddr)
{ … }

static void rvu_get_lbk_link_max_frs(struct rvu *rvu,  u16 *max_mtu)
{ … }

static void rvu_get_lmac_link_max_frs(struct rvu *rvu, u16 *max_mtu)
{ … }

int rvu_mbox_handler_nix_get_hw_info(struct rvu *rvu, struct msg_req *req,
				     struct nix_hw_info *rsp)
{ … }

int rvu_mbox_handler_nix_stats_rst(struct rvu *rvu, struct msg_req *req,
				   struct msg_rsp *rsp)
{ … }

/* Returns the ALG index to be set into NPC_RX_ACTION */
static int get_flowkey_alg_idx(struct nix_hw *nix_hw, u32 flow_cfg)
{ … }

/* Mask to match ipv6(NPC_LT_LC_IP6) and ipv6 ext(NPC_LT_LC_IP6_EXT) */
#define NPC_LT_LC_IP6_MATCH_MSK …
/* Mask to match both ipv4(NPC_LT_LC_IP) and ipv4 ext(NPC_LT_LC_IP_OPT) */
#define NPC_LT_LC_IP_MATCH_MSK …

static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg)
{ … }

static int reserve_flowkey_alg_idx(struct rvu *rvu, int blkaddr, u32 flow_cfg)
{ … }

int rvu_mbox_handler_nix_rss_flowkey_cfg(struct rvu *rvu,
					 struct nix_rss_flowkey_cfg *req,
					 struct nix_rss_flowkey_cfg_rsp *rsp)
{ … }

static int nix_rx_flowkey_alg_cfg(struct rvu *rvu, int blkaddr)
{ … }

int rvu_mbox_handler_nix_set_mac_addr(struct rvu *rvu,
				      struct nix_set_mac_addr *req,
				      struct msg_rsp *rsp)
{ … }

int rvu_mbox_handler_nix_get_mac_addr(struct rvu *rvu,
				      struct msg_req *req,
				      struct nix_get_mac_addr_rsp *rsp)
{ … }

int rvu_mbox_handler_nix_set_rx_mode(struct rvu *rvu, struct nix_rx_mode *req,
				     struct msg_rsp *rsp)
{ … }

static void nix_find_link_frs(struct rvu *rvu,
			      struct nix_frs_cfg *req, u16 pcifunc)
{ … }

int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req,
				    struct msg_rsp *rsp)
{ … }

int rvu_mbox_handler_nix_set_rx_cfg(struct rvu *rvu, struct nix_rx_cfg *req,
				    struct msg_rsp *rsp)
{ … }

static u64 rvu_get_lbk_link_credits(struct rvu *rvu, u16 lbk_max_frs)
{ … }

static void nix_link_config(struct rvu *rvu, int blkaddr,
			    struct nix_hw *nix_hw)
{ … }

static int nix_calibrate_x2p(struct rvu *rvu, int blkaddr)
{ … }

static int nix_aq_init(struct rvu *rvu, struct rvu_block *block)
{ … }

static void rvu_nix_setup_capabilities(struct rvu *rvu, int blkaddr)
{ … }

static int rvu_nix_block_init(struct rvu *rvu, struct nix_hw *nix_hw)
{ … }

int rvu_nix_init(struct rvu *rvu)
{ … }

static void rvu_nix_block_freemem(struct rvu *rvu, int blkaddr,
				  struct rvu_block *block)
{ … }

void rvu_nix_freemem(struct rvu *rvu)
{ … }

static void nix_mcast_update_action(struct rvu *rvu,
				    struct nix_mcast_grp_elem *elem)
{ … }

static void nix_mcast_update_mce_entry(struct rvu *rvu, u16 pcifunc, u8 is_active)
{ … }

int rvu_mbox_handler_nix_lf_start_rx(struct rvu *rvu, struct msg_req *req,
				     struct msg_rsp *rsp)
{ … }

int rvu_mbox_handler_nix_lf_stop_rx(struct rvu *rvu, struct msg_req *req,
				    struct msg_rsp *rsp)
{ … }

#define RX_SA_BASE …

void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int nixlf)
{ … }

#define NIX_AF_LFX_TX_CFG_PTP_EN …

static int rvu_nix_lf_ptp_tx_cfg(struct rvu *rvu, u16 pcifunc, bool enable)
{ … }

int rvu_mbox_handler_nix_lf_ptp_tx_enable(struct rvu *rvu, struct msg_req *req,
					  struct msg_rsp *rsp)
{ … }

int rvu_mbox_handler_nix_lf_ptp_tx_disable(struct rvu *rvu, struct msg_req *req,
					   struct msg_rsp *rsp)
{ … }

int rvu_mbox_handler_nix_lso_format_cfg(struct rvu *rvu,
					struct nix_lso_format_cfg *req,
					struct nix_lso_format_cfg_rsp *rsp)
{ … }

#define IPSEC_GEN_CFG_EGRP …
#define IPSEC_GEN_CFG_OPCODE …
#define IPSEC_GEN_CFG_PARAM1 …
#define IPSEC_GEN_CFG_PARAM2 …

#define CPT_INST_QSEL_BLOCK …
#define CPT_INST_QSEL_PF_FUNC …
#define CPT_INST_QSEL_SLOT …

#define CPT_INST_CREDIT_TH …
#define CPT_INST_CREDIT_BPID …
#define CPT_INST_CREDIT_CNT …

static void nix_inline_ipsec_cfg(struct rvu *rvu, struct nix_inline_ipsec_cfg *req,
				 int blkaddr)
{ … }

int rvu_mbox_handler_nix_inline_ipsec_cfg(struct rvu *rvu,
					  struct nix_inline_ipsec_cfg *req,
					  struct msg_rsp *rsp)
{ … }

int rvu_mbox_handler_nix_read_inline_ipsec_cfg(struct rvu *rvu,
					       struct msg_req *req,
					       struct nix_inline_ipsec_cfg *rsp)

{ … }

int rvu_mbox_handler_nix_inline_ipsec_lf_cfg(struct rvu *rvu,
					     struct nix_inline_ipsec_lf_cfg *req,
					     struct msg_rsp *rsp)
{ … }

void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc)
{ … }

/* NIX ingress policers or bandwidth profiles APIs */
static void nix_config_rx_pkt_policer_precolor(struct rvu *rvu, int blkaddr)
{ … }

static int nix_init_policer_context(struct rvu *rvu, struct nix_hw *nix_hw,
				    int layer, int prof_idx)
{ … }

static int nix_setup_ipolicers(struct rvu *rvu,
			       struct nix_hw *nix_hw, int blkaddr)
{ … }

static void nix_ipolicer_freemem(struct rvu *rvu, struct nix_hw *nix_hw)
{ … }

static int nix_verify_bandprof(struct nix_cn10k_aq_enq_req *req,
			       struct nix_hw *nix_hw, u16 pcifunc)
{ … }

int rvu_mbox_handler_nix_bandprof_alloc(struct rvu *rvu,
					struct nix_bandprof_alloc_req *req,
					struct nix_bandprof_alloc_rsp *rsp)
{ … }

static int nix_free_all_bandprof(struct rvu *rvu, u16 pcifunc)
{ … }

int rvu_mbox_handler_nix_bandprof_free(struct rvu *rvu,
				       struct nix_bandprof_free_req *req,
				       struct msg_rsp *rsp)
{ … }

int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw,
			struct nix_cn10k_aq_enq_req *aq_req,
			struct nix_cn10k_aq_enq_rsp *aq_rsp,
			u16 pcifunc, u8 ctype, u32 qidx)
{ … }

static int nix_ipolicer_map_leaf_midprofs(struct rvu *rvu,
					  struct nix_hw *nix_hw,
					  struct nix_cn10k_aq_enq_req *aq_req,
					  struct nix_cn10k_aq_enq_rsp *aq_rsp,
					  u32 leaf_prof, u16 mid_prof)
{ … }

int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc,
				 u16 rq_idx, u16 match_id)
{ … }

/* Called with mutex rsrc_lock */
static void nix_clear_ratelimit_aggr(struct rvu *rvu, struct nix_hw *nix_hw,
				     u32 leaf_prof)
{ … }

int rvu_mbox_handler_nix_bandprof_get_hwinfo(struct rvu *rvu, struct msg_req *req,
					     struct nix_bandprof_get_hwinfo_rsp *rsp)
{ … }

static struct nix_mcast_grp_elem *rvu_nix_mcast_find_grp_elem(struct nix_mcast_grp *mcast_grp,
							      u32 mcast_grp_idx)
{ … }

int rvu_nix_mcast_get_mce_index(struct rvu *rvu, u16 pcifunc, u32 mcast_grp_idx)
{ … }

void rvu_nix_mcast_flr_free_entries(struct rvu *rvu, u16 pcifunc)
{ … }

int rvu_nix_mcast_update_mcam_entry(struct rvu *rvu, u16 pcifunc,
				    u32 mcast_grp_idx, u16 mcam_index)
{ … }

int rvu_mbox_handler_nix_mcast_grp_create(struct rvu *rvu,
					  struct nix_mcast_grp_create_req *req,
					  struct nix_mcast_grp_create_rsp *rsp)
{ … }

int rvu_mbox_handler_nix_mcast_grp_destroy(struct rvu *rvu,
					   struct nix_mcast_grp_destroy_req *req,
					   struct msg_rsp *rsp)
{ … }

int rvu_mbox_handler_nix_mcast_grp_update(struct rvu *rvu,
					  struct nix_mcast_grp_update_req *req,
					  struct nix_mcast_grp_update_rsp *rsp)
{ … }