linux/drivers/net/ethernet/marvell/octeontx2/af/mcs.c

// SPDX-License-Identifier: GPL-2.0
/* Marvell MCS driver
 *
 * Copyright (C) 2022 Marvell.
 */

#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/pci.h>

#include "mcs.h"
#include "mcs_reg.h"

#define DRV_NAME …

#define PCI_CFG_REG_BAR_NUM …

static const struct pci_device_id mcs_id_table[] = …;

static LIST_HEAD(mcs_list);

void mcs_get_tx_secy_stats(struct mcs *mcs, struct mcs_secy_stats *stats, int id)
{ … }

void mcs_get_rx_secy_stats(struct mcs *mcs, struct mcs_secy_stats *stats, int id)
{ … }

void mcs_get_flowid_stats(struct mcs *mcs, struct mcs_flowid_stats *stats,
			  int id, int dir)
{ … }

void mcs_get_port_stats(struct mcs *mcs, struct mcs_port_stats *stats,
			int id, int dir)
{ … }

void mcs_get_sa_stats(struct mcs *mcs, struct mcs_sa_stats *stats, int id, int dir)
{ … }

void mcs_get_sc_stats(struct mcs *mcs, struct mcs_sc_stats *stats,
		      int id, int dir)
{ … }

void mcs_clear_stats(struct mcs *mcs, u8 type, u8 id, int dir)
{ … }

int mcs_clear_all_stats(struct mcs *mcs, u16 pcifunc, int dir)
{ … }

void mcs_pn_table_write(struct mcs *mcs, u8 pn_id, u64 next_pn, u8 dir)
{ … }

void cn10kb_mcs_tx_sa_mem_map_write(struct mcs *mcs, struct mcs_tx_sc_sa_map *map)
{ … }

void cn10kb_mcs_rx_sa_mem_map_write(struct mcs *mcs, struct mcs_rx_sc_sa_map *map)
{ … }

void mcs_sa_plcy_write(struct mcs *mcs, u64 *plcy, int sa_id, int dir)
{ … }

void mcs_ena_dis_sc_cam_entry(struct mcs *mcs, int sc_id, int ena)
{ … }

void mcs_rx_sc_cam_write(struct mcs *mcs, u64 sci, u64 secy, int sc_id)
{ … }

void mcs_secy_plcy_write(struct mcs *mcs, u64 plcy, int secy_id, int dir)
{ … }

void cn10kb_mcs_flowid_secy_map(struct mcs *mcs, struct secy_mem_map *map, int dir)
{ … }

void mcs_ena_dis_flowid_entry(struct mcs *mcs, int flow_id, int dir, int ena)
{ … }

void mcs_flowid_entry_write(struct mcs *mcs, u64 *data, u64 *mask, int flow_id, int dir)
{ … }

int mcs_install_flowid_bypass_entry(struct mcs *mcs)
{ … }

void mcs_clear_secy_plcy(struct mcs *mcs, int secy_id, int dir)
{ … }

int mcs_alloc_ctrlpktrule(struct rsrc_bmap *rsrc, u16 *pf_map, u16 offset, u16 pcifunc)
{ … }

int mcs_free_ctrlpktrule(struct mcs *mcs, struct mcs_free_ctrl_pkt_rule_req *req)
{ … }

int mcs_ctrlpktrule_write(struct mcs *mcs, struct mcs_ctrl_pkt_rule_write_req *req)
{ … }

int mcs_free_rsrc(struct rsrc_bmap *rsrc, u16 *pf_map, int rsrc_id, u16 pcifunc)
{ … }

/* Free all the cam resources mapped to pf */
int mcs_free_all_rsrc(struct mcs *mcs, int dir, u16 pcifunc)
{ … }

int mcs_alloc_rsrc(struct rsrc_bmap *rsrc, u16 *pf_map, u16 pcifunc)
{ … }

int mcs_alloc_all_rsrc(struct mcs *mcs, u8 *flow_id, u8 *secy_id,
		       u8 *sc_id, u8 *sa1_id, u8 *sa2_id, u16 pcifunc, int dir)
{ … }

static void cn10kb_mcs_tx_pn_wrapped_handler(struct mcs *mcs)
{ … }

static void cn10kb_mcs_tx_pn_thresh_reached_handler(struct mcs *mcs)
{ … }

static void mcs_rx_pn_thresh_reached_handler(struct mcs *mcs)
{ … }

static void mcs_rx_misc_intr_handler(struct mcs *mcs, u64 intr)
{ … }

static void mcs_tx_misc_intr_handler(struct mcs *mcs, u64 intr)
{ … }

void cn10kb_mcs_bbe_intr_handler(struct mcs *mcs, u64 intr,
				 enum mcs_direction dir)
{ … }

void cn10kb_mcs_pab_intr_handler(struct mcs *mcs, u64 intr,
				 enum mcs_direction dir)
{ … }

static irqreturn_t mcs_ip_intr_handler(int irq, void *mcs_irq)
{ … }

static void *alloc_mem(struct mcs *mcs, int n)
{ … }

static int mcs_alloc_struct_mem(struct mcs *mcs, struct mcs_rsrc_map *res)
{ … }

static int mcs_register_interrupts(struct mcs *mcs)
{ … }

int mcs_get_blkcnt(void)
{ … }

struct mcs *mcs_get_pdata(int mcs_id)
{ … }

bool is_mcs_bypass(int mcs_id)
{ … }

void mcs_set_port_cfg(struct mcs *mcs, struct mcs_port_cfg_set_req *req)
{ … }

void mcs_get_port_cfg(struct mcs *mcs, struct mcs_port_cfg_get_req *req,
		      struct mcs_port_cfg_get_rsp *rsp)
{ … }

void mcs_get_custom_tag_cfg(struct mcs *mcs, struct mcs_custom_tag_cfg_get_req *req,
			    struct mcs_custom_tag_cfg_get_rsp *rsp)
{ … }

void mcs_reset_port(struct mcs *mcs, u8 port_id, u8 reset)
{ … }

/* Set lmac to bypass/operational mode */
void mcs_set_lmac_mode(struct mcs *mcs, int lmac_id, u8 mode)
{ … }

void mcs_pn_threshold_set(struct mcs *mcs, struct mcs_set_pn_threshold *pn)
{ … }

void cn10kb_mcs_parser_cfg(struct mcs *mcs)
{ … }

static void mcs_lmac_init(struct mcs *mcs, int lmac_id)
{ … }

int mcs_set_lmac_channels(int mcs_id, u16 base)
{ … }

static int mcs_x2p_calibration(struct mcs *mcs)
{ … }

static void mcs_set_external_bypass(struct mcs *mcs, bool bypass)
{ … }

static void mcs_global_cfg(struct mcs *mcs)
{ … }

void cn10kb_mcs_set_hw_capabilities(struct mcs *mcs)
{ … }

static struct mcs_ops cn10kb_mcs_ops = …;

static int mcs_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{ … }

static void mcs_remove(struct pci_dev *pdev)
{ … }

struct pci_driver mcs_driver = …;