/* SPDX-License-Identifier: GPL-2.0 */ /* * PCIe host controller driver for Mobiveil PCIe Host controller * * Copyright (c) 2018 Mobiveil Inc. * Copyright 2019 NXP * * Author: Subrahmanya Lingappa <[email protected]> * Hou Zhiqiang <[email protected]> */ #ifndef _PCIE_MOBIVEIL_H #define _PCIE_MOBIVEIL_H #include <linux/pci.h> #include <linux/irq.h> #include <linux/msi.h> #include "../../pci.h" /* register offsets and bit positions */ /* * translation tables are grouped into windows, each window registers are * grouped into blocks of 4 or 16 registers each */ #define PAB_REG_BLOCK_SIZE … #define PAB_EXT_REG_BLOCK_SIZE … #define PAB_REG_ADDR(offset, win) … #define PAB_EXT_REG_ADDR(offset, win) … #define LTSSM_STATUS … #define LTSSM_STATUS_L0_MASK … #define LTSSM_STATUS_L0 … #define PAB_CTRL … #define AMBA_PIO_ENABLE_SHIFT … #define PEX_PIO_ENABLE_SHIFT … #define PAGE_SEL_SHIFT … #define PAGE_SEL_MASK … #define PAGE_LO_MASK … #define PAGE_SEL_OFFSET_SHIFT … #define PAB_ACTIVITY_STAT … #define PAB_AXI_PIO_CTRL … #define APIO_EN_MASK … #define PAB_PEX_PIO_CTRL … #define PIO_ENABLE_SHIFT … #define PAB_INTP_AMBA_MISC_ENB … #define PAB_INTP_AMBA_MISC_STAT … #define PAB_INTP_RESET … #define PAB_INTP_MSI … #define PAB_INTP_INTA … #define PAB_INTP_INTB … #define PAB_INTP_INTC … #define PAB_INTP_INTD … #define PAB_INTP_PCIE_UE … #define PAB_INTP_IE_PMREDI … #define PAB_INTP_IE_EC … #define PAB_INTP_MSI_MASK … #define PAB_INTP_INTX_MASK … #define PAB_AXI_AMAP_CTRL(win) … #define WIN_ENABLE_SHIFT … #define WIN_TYPE_SHIFT … #define WIN_TYPE_MASK … #define WIN_SIZE_MASK … #define PAB_EXT_AXI_AMAP_SIZE(win) … #define PAB_EXT_AXI_AMAP_AXI_WIN(win) … #define PAB_AXI_AMAP_AXI_WIN(win) … #define AXI_WINDOW_ALIGN_MASK … #define PAB_AXI_AMAP_PEX_WIN_L(win) … #define PAB_BUS_SHIFT … #define PAB_DEVICE_SHIFT … #define PAB_FUNCTION_SHIFT … #define PAB_AXI_AMAP_PEX_WIN_H(win) … #define PAB_INTP_AXI_PIO_CLASS … #define PAB_PEX_AMAP_CTRL(win) … #define AMAP_CTRL_EN_SHIFT … #define AMAP_CTRL_TYPE_SHIFT … #define AMAP_CTRL_TYPE_MASK … #define PAB_EXT_PEX_AMAP_SIZEN(win) … #define PAB_EXT_PEX_AMAP_AXI_WIN(win) … #define PAB_PEX_AMAP_AXI_WIN(win) … #define PAB_PEX_AMAP_PEX_WIN_L(win) … #define PAB_PEX_AMAP_PEX_WIN_H(win) … /* starting offset of INTX bits in status register */ #define PAB_INTX_START … /* supported number of MSI interrupts */ #define PCI_NUM_MSI … /* MSI registers */ #define MSI_BASE_LO_OFFSET … #define MSI_BASE_HI_OFFSET … #define MSI_SIZE_OFFSET … #define MSI_ENABLE_OFFSET … #define MSI_STATUS_OFFSET … #define MSI_DATA_OFFSET … #define MSI_ADDR_L_OFFSET … #define MSI_ADDR_H_OFFSET … /* outbound and inbound window definitions */ #define WIN_NUM_0 … #define WIN_NUM_1 … #define CFG_WINDOW_TYPE … #define IO_WINDOW_TYPE … #define MEM_WINDOW_TYPE … #define IB_WIN_SIZE … #define MAX_PIO_WINDOWS … /* Parameters for the waiting for link up routine */ #define LINK_WAIT_MAX_RETRIES … #define LINK_WAIT_MIN … #define LINK_WAIT_MAX … #define PAGED_ADDR_BNDRY … #define OFFSET_TO_PAGE_ADDR(off) … #define OFFSET_TO_PAGE_IDX(off) … struct mobiveil_msi { … }; struct mobiveil_pcie; struct mobiveil_rp_ops { … }; struct mobiveil_root_port { … }; struct mobiveil_pab_ops { … }; struct mobiveil_pcie { … }; int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie); int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit); bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie); int mobiveil_bringup_link(struct mobiveil_pcie *pcie); void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr, u64 pci_addr, u32 type, u64 size); void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr, u64 pci_addr, u32 type, u64 size); u32 mobiveil_csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size); void mobiveil_csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size); static inline u32 mobiveil_csr_readl(struct mobiveil_pcie *pcie, u32 off) { … } static inline u16 mobiveil_csr_readw(struct mobiveil_pcie *pcie, u32 off) { … } static inline u8 mobiveil_csr_readb(struct mobiveil_pcie *pcie, u32 off) { … } static inline void mobiveil_csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off) { … } static inline void mobiveil_csr_writew(struct mobiveil_pcie *pcie, u16 val, u32 off) { … } static inline void mobiveil_csr_writeb(struct mobiveil_pcie *pcie, u8 val, u32 off) { … } #endif /* _PCIE_MOBIVEIL_H */
Codebase Browser
linux